KR101379047B1 - Multi-phase non-inverting buck boost voltage converter - Google Patents

Abstract

The multiphase, non-inverting buck boost voltage converter has a plurality of buck boost voltage regulators. Each regulator is associated with a separate phase to generate a regulated output voltage in response to the input voltage. The plurality of current sensors are each associated with one of the plurality of buck boost voltage regulators for monitoring the input current for the associated buck boost voltage regulator and for generating a current sense signal for the associated phase. A plurality of buck boost mode control circuits for controlling the associated buck boost voltage regulator using peak current mode control in buck mode of operation and valley current mode control in boost mode of operation in response to a common error voltage and associated current sense signal. Each associated with one of the buck boost regulators. Multiple buck boost mode control circuits provide current balancing between phases. The voltage error circuit generates an error voltage in response to the regulated output voltage.

Description

MULTI-PHASE NON-INVERTING BUCK BOOST VOLTAGE CONVERTER}

Cross reference to related application

This application is directed to US Patent Application No. 13 / 160,162, filed June 14, 2011, MULTI-LEVEL NON-INVERTING BB VOLTAGE CONVERTER Claim for non-inverting buck boost voltage converter (Non-INVERTING BUCK BOOST VOLTAGE CONVERTER) (Rep. Some continue to file.

The present invention relates to a buck boost voltage converter, and more particularly, to a system and method for controlling a non-inverting buck boost converter to provide a smooth transition between a buck mode and a boost mode of operation.

The non-inverting buck boost converter is capable of obtaining an output voltage that is higher or lower than its input voltage, depending on the mode of operation. As battery powered devices become more and more popular, these types of converters are becoming more attractive because they can take advantage of the discharge cycle of the battery. When the battery input voltage is higher than its output voltage, the buck boost converter operates in buck mode of operation. In the buck mode of operation, the converter reduces the input voltage to the level required for use at its output. When the battery input voltage is lower than the output voltage, the buck boost converter operates in boost mode of operation where the input voltage is increased to the level required at its output. Control in pure buck mode and pure boost mode of operation is obtained by turning on or off various associated power switches. The transition between buck mode and boost mode of operation presents a variety of control difficulties when the output voltage is close to the input voltage. Two difficulties from controlling the buck-boost converter during this transition between buck and boost modes of operation include the occurrence of line transients, which are dynamic responses, and the occurrence of output ripple, which is a steady state performance issue. The generated input voltage approaches the output voltage.

The problem to be solved by the present invention is to provide a multi-phase buck boost converter to avoid the difficulties of the prior art mentioned above.

The present invention includes, in one aspect thereof, a non-inverting buck boost converter, as disclosed and described herein. The buck boost converter includes a buck boost voltage regulation circuit for generating a regulated output voltage in response to the input voltage. The current sensor monitors the input current for the buck boost regulation circuit. The buck boost mode control circuit controls the buck boost voltage regulation circuit using deep current mode control in the buck mode of operation and active current mode control in the boost mode of operation in response to the monitored input current.

The present invention provides a method for controlling a non-inverting buck boost converter and obtaining a smooth transition between mode and line transients while still maintaining the lowest ripple voltage when the output voltage is close to the input voltage.

For a more complete understanding, reference is now made to the following description with reference to the accompanying drawings, in which:
1 is a schematic diagram of a buck boost converter;
2 shows a functional block diagram of a non-inverting buck boost converter of the present disclosure;
3 provides a more detailed block diagram of a non-inverting buck boost converter of the present disclosure;
4 is a flowchart illustrating operation of the non-inverting buck boost converter of FIG. 3;
5A-5C show waveforms of a buck boost converter operation when converting from a buck mode of operation to a boost mode of operation;
6A-6C show waveforms of a buck boost converter operation when converting from an boost mode of operation to a buck mode of operation;
7 is a functional block diagram of a multiphase non-inverting buck boost converter;
8 is a block diagram of a modulator and driver circuit of a multiphase buck boost converter;
9 is a more detailed block diagram of a multiphase non-inverting buck boost converter with inherent current sharing;
10 is a schematic block diagram of a modulator and driver circuit;
11 is a schematic block diagram of a maximum duty cycle detection and mode selection circuit;
12 illustrates the operation of a two phase non-inverting buck boost converter operating in a buck mode steady state;
13 shows a two phase non-inverting buck boost converter operating in a buck mode steady state; And
14 shows a two phase non-inverting buck boost converter operating in a boost mode steady state.

Referring now to the drawings, corresponding reference numerals are used herein to indicate corresponding components throughout, various aspects and embodiments of the non-inverting buck boost voltage converter are shown and described, and other possible embodiments are described. . The drawings are not necessarily drawn to scale, and in some instances the drawings are enlarged and / or simplified in various places for purposes of illustration only. Those skilled in the art will recognize many possible applications and variations based on the following examples of possible embodiments.

A non-inverting buck boost converter is capable of obtaining a positive output voltage that is higher or lower than its input voltage. As battery powered devices become more and more popular, this topology is becoming more attractive because it can take advantage of the discharge cycle of the battery. When the battery input voltage is higher than its output voltage, the buck boost converter operates in buck mode of operation. In the buck mode of operation, the converter reduces the input voltage to the level required for use at its output. When the battery input voltage is lower than the output voltage, the buck boost converter operates in boost mode of operation, where the input voltage is increased to the level required at the output. It is relatively easy to implement control in either the pure buck mode of operation or the pure boost mode of operation by leaving some power switches on or off. When the output voltage approaches the input voltage, the difficulty remains in the transition between the buck and boost modes of operation. There are two difficulties with controlling the buck boost converter during this transition between buck mode and boost mode of operation. One difficulty involves line transients, which is a dynamic response. Another difficulty is output ripple, which is a steady-state performance problem, and the generated input voltage approaches the output voltage.

The implementation described below is a scheme for controlling a non-inverting buck-boost converter and providing a smooth transition between mode and line transients while still maintaining the lowest ripple voltage when the output voltage is close to the input voltage. (scheme) is included. Only one integrated current sensor is used in the scheme instead of multiple sensors to reduce complexity and simplify the overall design. The controller uses peak current mode control in buck mode of operation and valley current control mode in boost mode of operation using cycle-by-cycle detection. This method provides smooth transitions and line transients in the converter. When the output voltage is close to the input voltage, the buck boost converter automatically switches from the buck mode of operation to the boost mode of operation or from the boolean mode of operation to the buck mode of operation by monitoring the maximum duty cycle. This simplifies the control of the buck-boost converter and reduces the output voltage ripple. Both buck mode operation and boost mode operation use the same integrated current sensor, which reduces system complexity and increases overall reliability.

A non-inverting buck boost converter is capable of obtaining a positive output voltage that is higher or lower than its input voltage. Many applications prefer non-inverting buck-boost converters, such as battery-powered devices that want to take advantage of the battery's discharge cycle. Battery powered electronics and battery powered vehicles experience inferior battery voltage due to conditions where load dump or cold cranking occurs. In these cases, the non-inverting buck boost converter is an ideal candidate. If the load power is high, the multiphase buck-boost converter requires low cost and low heat dissipation.

Referring now to the drawings, and more particularly to FIG. 1, there is a illustrated schematic diagram of a buck boost converter. The buck boost converter includes an input voltage node 102 to which an input voltage V _IN is applied. The high side buck transistor 104 includes a P-channel transistor having a source / drain path connected between the node 102 and the node 106. Low side buck transistor 108 includes an N-channel transistor having a drain / source path coupled between node 106 and ground. Inductor 110 is connected between node 106 and node 112. The high side P-channel boost transistor 114 has its source / drain path connected between the output voltage node V _OUT 116 and node 112. Low side boost transistor 118 includes an N-channel transistor having a source / drain path coupled between node 112 and ground. As will be appreciated by those skilled in the art, the high side buck transistor and the high side boost transistor can also be implemented by an N-channel transistor. All switching transistors can also be implemented by bipolar transistors or any other suitable controlled switching device. The output capacitance 120 is connected between the output voltage node 116 and ground. Output load resistor 122 is connected in parallel with capacitance 120 between node 116 and ground. Each of the high side buck transistor 104, low side buck transistor 108, high side boost transistor 114 and low side boost transistor 118 has their gate connected to the buck boost control circuit 124. The buck boost control circuit 124 generates a gate control signal through the plurality of outputs using internal control logic responsible for at least the output voltage V _OUT applied from the node 116. In the buck mode of operation, the duty cycle is defined as D = t _{on 104} / T, where t _on is the on-time of the switching transistor 104 and T is the switching period of the converter. T is the switching frequency, inverse of fsw, (T = 1 / fsw). During the boost operation, the duty cycle is defined to be D = t _{on 118} / T, ie the on-time of the synchronous high side boost transistor 114 divided by the switching period.

Referring now to FIG. 2, there is a illustrated functional block diagram of a non-inverted buck boost converter operating in accordance with the present disclosure. Buck boost converter circuit 202 receives input voltage V _IN at input node 204 and provides output voltage V _OUT at node 206. The switching transistor in the buck boost converter 202 is driven in accordance with the drive control signal provided by the drive logic 208. Drive logic 208 generates a drive control signal to the switching transistor in response to the PWM control signal provided by PWM control logic 210. The error amplifier and PWM control logic 210 generate a PWM control signal in response to the output voltage monitored at node 206 and also in response to the current control voltage VSUM provided at current slope control compensation logic 212. Current slope control compensation logic generates a VSUM voltage for the error amplifier and PWM control logic 210 in response to the monitored current in the buck boost converter 202 provided by the current sensor 214 and the mode control logic 216. Let's do it. Current sensor 214 measures the input current provided at input node 204 of buck boost converter 202. The mode control logic 216 determines whether the buck boost converter 202 operates in the buck mode of operation or in the boost mode of operation by monitoring the PWM signal provided by the PWM control logic 210. The mode control logic 216 additionally provides a mode control signal to the drive logic 208 to control the operation of the switching transistor in the buck boost converter 202.

Referring now to FIG. 3, there is a shown block diagram of a non-inverting buck boost converter of the present disclosure. Buck boost converter 302 includes an input voltage node 304 to which an input voltage V _IN is applied. Current sensor 306 senses input voltage current through node 304 and provides a sensed input current ISNS. The high side buck transistor 308 is coupled between the current sensor 306 and the node 310. The high side buck transistor 308 includes a P-channel transistor. The high side buck transistor 308 is coupled to receive the drive signal HD_BUCK. Low side buck transistor 312 includes an N-channel transistor having a drain / source path coupled between node 310 and ground node 314. The low side buck transistor 312 is coupled to receive the drive control signal LD_BUCK. Inductor 316 is coupled between node 310 and node 318.

High side boost transistor 320 includes a P-channel transistor having a source / drain path coupled between output voltage node V _OUT 322 and node 318. Low side boost transistor 321 includes an N-channel transistor having a drain / source path coupled between node 318 and node 314. The gate of transistor 324 is connected to receive drive control signal LD_BOOST. The gate of the high side boost transistor 320 is connected to receive the drive control signal HD_BOOST. Output capacitor 326 is connected to output voltage node 322 between output voltage node 322 and ground node 314. Additionally, load 328 is connected in parallel with output capacitance 326 between output voltage node 322 and ground node 314.

Drive control signals for each of the high side buck transistor 308, the low side buck transistor 312, the high side boost transistor 320, and the low side boost transistor 324 are buck mode current logic and driver 330 and boost. Mode control logic and driver 332 respectively. The buck mode control logic and driver 330 sends an HD_BUCK signal to the high side buck transistor 308 in response to the PWM signal PWM_BUCK provided by the SR latch 334 and the mode control signal provided by the mode control logic 336. Then, LD_BUCK signal is generated for the low side buck transistor 312. The boost mode control logic and driver 332 draws the HD_BOOST drive signal for the transistor 320 in response to the PWM control signal PWM_BOOST from the SR latch 338 and in response to the mode control signal from the mode control logic 336. An LD_BOOST drive signal is generated for the transistor 324. Transistor 308 and transistor 312 are power switches for buck boost converter 302 in the buck mode of operation. In the buck mode of operation, transistor 320 is always on and transistor 324 is always off. Similarly, in boost mode of operation, buck mode control logic and driver 330 and boost mode control logic and driver 332 control boost transistor 320 and boost transistor 324 to include a power FET switch. do. While transistor 312 is turned off in the boost mode of operation, transistor 308 is always turned on.

SR latch 334 is a buck PWM signal for buck mode control logic and driver 330 in response to a clock signal provided at the S input of SR latch 334 and a logic signal applied to the R input of SR latch 334. Generates. The PWM signal PMW_Boost is provided from the Q output of the SR latch 338 in response to a clock input provided to the R input of the SR latch 338 and a logic input provided to the S input of the SR latch 338. .

The mode control logic 336 provides a MODE signal to each of the buck mode control logic and driver 330 and the boost mode control logic and driver 332. The mode control logic 336 controls the buck mode control logic and driver 330 and boost mode control in response to the PWM_BUCK and PWM_BOOST signals provided from the outputs of the SR latch 334 and the SR latch 338, respectively. Generate an output control signal MODE in each of the logic and driver 332. The maximum duty cycle detection circuit 340 determines when a maximum duty cycle condition exists between the buck mode and the boost mode of operation in response to the output voltage V _OUT approaching the input voltage V _IN . When the maximum duty cycle condition is detected, the maximum duty cycle detection circuit 340 generates a logically "high" value for the MAX_D signal provided to the mode selection logic 342.

The mode selection logic 342 determines whether the buck boost converter 302 requires switching to either a buck mode of operation or a boost mode of operation and generates a mode control signal MODE to indicate this change. In order to switch smoothly from buck operation to boost operation or from boost operation to buck operation, the determination of the maximum duty cycle is introduced by the maximum duty cycle detection circuit 340 into the control scheme. Whenever the maximum duty cycle condition is detected, the MAX_D signal logically goes to the "high" level. This normally occurs when the input voltage VIN approaches the output voltage VOUT or when a load transient occurs at the output. The mode selection logic 342 determines whether the operation mode of the buck boost converter 302 is buck or boost. A simple control method is implemented as if the MAX_D logically "high" signal is detected, the operating mode toggles. More sophisticated control methods can be applied by using multiple MAX_D signals. There are two operating in a buck boost converter, either buck or boost, and only two modes. The output "MODE" signal of the mode select logic behaves like a multiplexer control signal that selects the operating circuit, e.g. current sensing and switch driver control logic, depending on whether the converter is in buck mode or boost mode of operation. Thus, the MODE control signal selects either the buck mode control logic driver 330 or the boost mode control logic and driver 332 according to the mode of operation, and also the current sense compensation signal provided from the output of the multiplexer 334. Select.

Multiplexer 344 is coupled to receive either a VSUM_BUCK signal or a VSUM_BOOST signal. The VSUM_BUCK signal includes the sum of the current sensed from the current sensor 306 added together in the adder circuit 346, the buck mode offset signal, and the buck slope compensation signal. A VSUM_BOOST signal is generated at the adder circuit 348 by adding together the ISNS input current measurement from the current sensor 306, the boost mode offset signal, and the boost slope compensation signal. The current ISNS sensed from the current sensor 306 is summed with a buck mode offset or boost mode offset to ensure that the error amplifier 352 is operating with a suitable DC bias. A buck or boost compensation slope is added to the sensed current to avoid sub harmonic oscillation in large duty cycle operation. Each of the VSUM_BUCK compensation signal and the VSUM_BOOST compensation signal is provided to one input of the multiplexer 344. Either VSUM_BUCK (buck mode) or VSUM_BOOST (boost mode) depends on the MODE signal at multiplexer 344 depending on whether the buck boost converter 302 is operating in buck mode of operation or in boost mode of operation. In response, the selected and selected signal is provided as the output current compensation signal V _SUM .

The V _SUM signal is provided to the inverting input of the PWM comparator 350 from the multiplexer 344. The non-inverting input of the PWM comparator 350 is connected to receive the voltage error signal V _COMP from the error amplifier 352. An output of the error amplifier 352 is connected to ground through a capacitor 354 in series with the resistor 356. The inverting input of the error amplifier 352 is connected to a node through a register divider consisting of a register 358 connected between node 322 and node 360 and a register connected between node 360 and ground. Monitor the output voltage V _OUT at 322. The inverting input of error amplifier 352 is connected to node 360. Error amplifier 352 compares the output feedback voltage from buck boost converter 302 with a reference voltage V _REF applied to its non-inverting input to generate an error signal V _COMP . The VCOMP signal is used to determine inductor current through inductor 316 in both peak current mode when the buck boost converter is operating in buck mode of operation and valley current mode when the buck boost converter is operating in boost mode of operation. do. The buck operation and the boost operation share the same voltage error signal. The comparison of the voltage error signal V _COMP and V _SUM from the output of the multiplexer 344 determines the on / off state of the power transistors 308, 312, 320 and 324.

Output V _COMPOUT of PWM comparator 350 is provided as an input to inverter 362 and to a first input of AND gate 364. The inverted output from inverter 362 is provided to a first input of OR gate 366. The other input of the OR gate 366 is connected to receive the MAX_D signal from the output of the maximum duty cycle detection circuit 340. The output of the OR gate 366 provides a logic signal to the R input of the latch 334 to enable generation of a buck PWM signal. The other input of AND gate 364 is connected to the output of inverter 368. The input of the inverter 368 is connected to receive the MAX_D signal from the maximum duty cycle protection circuit 340. The output of AND gate 364 is connected to another inverter 370. The output of interleaver 370 provides a logic signal to the S input of SR latch 338 to provide a boost PWM signal.

Referring now to FIG. 4, there is a schematic flow diagram illustrating the operation of the buck boost converter of FIG. 3. When the converter operation begins in step 402, the converter first operates in buck mode of operation in step 404 and in peak current control mode of operation. Inquiry step 406 monitors for the maximum duty cycle and if no maximum duty cycle is currently detected, control returns to step 404. When the maximum duty cycle is detected, the converter enters the boost mode of operation in step 408 and operates using the valley current control mode. Inquiry step 410 monitors for the maximum duty cycle and if no maximum duty cycle is detected, control returns to step 408. When the maximum duty cycle is detected, the converter again converts to operate in the buck mode of operation in step 404.

Referring now to FIG. 5, when the buck boost converter transitions from the buck mode of operation to the boost mode of operation, there are various illustrated waveforms associated with the buck boost converter 302. Transistor 308 and transistor 312 include a main power switch in the buck mode of operation. Transistor 320 is always on in buck mode of operation and transistor 324 is always off in buck mode of operation. As the input voltage V _IN 502 drops, the switching duty cycle increases because it is D to Vout / Vin. As the input voltage V _IN 502 drops to a certain value, the duty cycle reaches a maximum threshold (maximum duty cycle), and in one embodiment the maximum duty cycle detection circuit 340 comprising a digital comparator is at this condition. And logically set the signal MAX_D to the "high" level. At the same time, high side transistor 308 is turned off and transistor 312 is turned on. The mode select logic 342 knows the next cycle and when the clock signal appears at the input of the SR latch 334, the buck boost converter 302 will transition to boost mode. When the clock pulse arrives, the control signal MODE is logically set to the "high" level (boost) and the buck boost converter is now configured for boost operation. In this condition, however, the input voltage V _IN 502 is still slightly higher than the output voltage V _OUT 504, so that the boost mode of operation can pump too much energy into the load and also increase the output voltage V _OUT . have. Thus, the buck boost converter 302 returns to the buck mode of operation after the boost cycle and remains in the buck mode of operation for more than one cycle until the output voltage V _OUT 504 drops below the input voltage V _IN . . In this way a smooth transition from the buck mode of operation to the boost mode of operation is provided. 5 also shows the output of multiplexer 344, the V _SUM 506, the output of error amplifier V _COMP 508, and the inductor current 510.

Referring now to FIG. 6, there is a conversion of the illustrated buck boost converter 302 from the boost mode of operation to the buck mode of operation. When the input voltage V _IN 602 is much lower than the output voltage V _OUT 604, the buck boost converter operates in the pure boost mode of operation. Transistor 320 and transistor 324 include a main power switch in the boost mode of operation while transistor 308 is always on and transistor 312 is always off. As the input voltage V _IN 602 increases, the switching duty cycle increases because the buck boost converter 302 is in valley control mode of operation. As the input voltage V _IN 602 increases to a certain level where the duty cycle reaches the maximum threshold level (maximum duty cycle), the maximum duty cycle detection circuit 340 including the digital comparator responds to this condition and logically Set signal MAX_D to the "high" level. At the same time, the high side transistor 320 is turned off and the low side transistor 324 is turned on. Mode select logic 342 knows the next cycle, and when the clock signal appears, the converter will transmit in buck mode. When the clock signal reaches the buck mode of operation, the signal "MODE" is logically set to the "low" level (buck mode) and the entire buck boost converter is configured for buck mode of operation. In this condition, however, the input voltage V _IN 602 is still lower than the output voltage V _OUT 604. Thus, the buck mode of operation can attract too much energy to the load and the output voltage V _OUT 604 is reduced. Thus, the buck boost converter 302 returns to the boost mode of operation after the buck cycle and remains in the boost mode of operation for one or more cycles until the output voltage 604 increases. As the input voltage V _IN 602 increases further, there may be more buck cycles. In this way, a smooth transition from boost to buck is provided.

The illustration of FIG. 6 also shows the output V _SUM 606, the error amplifier output V _COMP 608, and the inductor current 610 of the multiplexer 344.

When the output voltage V _OUT approaches the input voltage V _IN , the buck boost converter 302 switches from buck to boost and from buck mode to boost. Independent Buck-Boost Mode There are no buck and boost modes. The control method uses a peak current control mode in the buck mode of operation and a valley current control mode in the boost mode of operation to ensure smooth transitions. The main advantage of this method is that the error signal V _COMP does not have any sudden change during mode transition. Since the V _COMP signal is a direct function (function) of the output voltage V _OUT, the output voltage V _OUT is stabilized If the error signal V _COMP is stable. As mentioned earlier, the output of the multiplexer V _SUM is the _sum of the input current ISNS buck or boost mode offset and slope compensation signals. In the buck and boost modes of operation, different values of the offset are selected based on the maximum slope compensation at full cycle. In general, the other value of the offset is twice the maximum slope compensation voltage. For example, if the slope compensation is 1V / us and the switching frequency is 1MHz, the other value of the offset is 1V / us * 1us * 2, which is 2V. So if the offset in buck mode is Vos, then the offset for boost mode is Vos + 2V). System operation in this manner provides line transients that are superior in both light and heavy loading conditions. When the output voltage is close to the input voltage, the voltage ripple is also small. The control method simply requires only a single integrated current sensor and cycle to cycle detection.

Referring now to FIG. 7, there is a illustrated block diagram of a multiphase non-inverting buck boost converter. Error amplifier 702 provides feedback voltage divider and loop compensation to the multiphase non-inverting buck boost converter. The error amplifier 702 generates a compensation signal V _COMP provided to each of the modulator and driver circuit 704 associated with each phase of the polyphase non-inverting buck boost converter. The modulator and driver circuit 704 generates a drive signal for the associated buck boost converter 706 in response to the current signal I _SNS from the current sensor 708 associated with the V _COMP signal from the error amplifier 702. Current sensor 708 monitors the input current for associated buck boost converter 706 to generate an I _SNS voltage signal to associated modulator and driver 704. The buck boost converter 706 generates the output voltage V _OUT monitored by the error amplifier 702 to generate the compensation voltage V _COMP .

Referring now to FIG. 8, there is a block diagram of the illustrated modulator and driver circuit 704 associated with each phase of a polyphase non-inverting buck boost converter. PWM logic 802 generates a PWM control signal with drive logic 804 and mode control logic 806. Drive logic 804 generates a drive signal to the switching transistor of the associated buck boost converter in response to the PWM control signal provided by PWM logic 802. The mode control logic 806 determines whether the buck boost converter operates in the buck mode of operation or in the boost mode of operation by monitoring the PWM signal from the PWM logic 802. The mode control logic 806 additionally provides a mode control signal to the drive logic 804 to control the operation of the switching transistors in the buck boost converter. Current slope compensation circuit 808 generates V _SUM voltage to PWM logic 802 in response to current I _SNS monitored from buck boost converter by current sensor 708 (FIG. 7).

Referring now to FIG. 9, there is a more detailed block diagram provided for a multiphase non-inverting buck boost converter that provides inherent current sharing between different phases of the buck boost converter. As described above, the error amplifier section 702 monitors the output voltage from the combined output of the multi-phase of the buck boost converter 706 at node 902. Error amplifier circuit 702 includes a voltage divider consisting of a resistor 904 coupled between node 902 and node 906 and a resistor 908 coupled between node 906 and ground. The feedback voltage V _FB is monitored at node 906 by the inverting input of error amplifier 910. The non-inverting input of the error amplifier 910 receives a reference voltage V _REF for comparison with the feedback voltage V _FB . The output of error amplifier 910 is coupled to node 912 to provide a V _COMP input to each of the modulators and drivers 704 associated with each phase of the polyphase non-inverting buck boost converter. The serial connection of comparator 914 and register 916 is connected between node 912 and ground. Comparator 914 is connected between node 912 and node 918 and register 916 is connected between node 918 and ground. The error amplifier 910 includes a transconductance amplifier that generates a compensation signal V _COMP that is supplied to each of the modulator and driver circuit 704. Only a single error amplifier 910 is needed for the system. However, multiple error amplifiers 910 can be placed in parallel and the total gain of the error amplifier can include the sum of each of the error amplifiers.

The second part of the system shown in FIG. 9 includes a modulator and a driver 704. These are respectively connected to receive from the error amplifier 910 a current sense signal I _SNSN associated with the sensed signal V _COMP and the sensed input current at the input voltage node of the buck boost converter associated with the desired phase of the polyphase converter. Each phase of the converter requires a separate modulator because the clock signal for each phase is different to produce less output and input ripple than the interleaved inductor current and single phase converter. The N-phase converter can ideally have a phase shift of 360 / n between adjacent phases. Each phase also has independent current sensing from I _SNS1 to I _SNSn . This structure provides a unique current balancing mechanism. In either peak current mode in the buck mode of operation or valley current mode control in the boost mode of operation, the sense current voltage I _SNSn is compared with the compensation signal V _COMP . Since VCOMP is a common signal between each modulator, the signal balances current for each phase. While acquiring higher performance, this is a huge benefit in polyphase converters, which reduces design complexity. Each phase has its own maximum duty cycle detection circuit and mode selection circuit. When VIN is close to VOUT, while some phases operate in boost mode, others can operate in buck mode. The modulator and driver circuit 704 for each phase generates HD_BUCKn, LD_BUCKn, HD_BOOSTn and LD_BOOSTn for each of the switching transistors associated with the buck boost converter for the associated phase.

These driver outputs are provided to the associated power switching transistors of the buck boost converter 706. Each buck boost converter 706 includes an input voltage node 915 provided with a regulated input voltage. Current sensor 917 senses input voltage current through node 915 and provides a sensed input current voltage I _SNSn . The high side buck transistor 919 is coupled between the current sensor 917 and the node 920. High side buck transistor 919 includes a P-channel transistor. The high side buck transistor 919 is connected to receive the drive signal HD_BUCKn. Low side buck transistor 922 includes an N-channel transistor having a drain / source path coupled between node 920 and ground node 924. The low side buck transistor 922 is coupled to receive the drive control signal LD_BUCKn. Inductor 926 is coupled between node 920 and node 928.

High side boost transistor 930 includes a P-channel transistor having a source / drain path coupled between output voltage node V _OUT 932 and node 928. Low side boost transistor 934 includes an N-channel transistor having a drain / source path coupled between node 928 and ground node 924. The gate of transistor 934 is connected to receive drive control signal HD_BOOSTn. The high and low side buck and boost switching transistors and current sensors are identical in each of the buck boost converters associated with each phase of the multiphase buck boost converter. Each buck boost converter has its output connected to node 932. In addition, a load consisting of registers 935 is coupled between node 932 and ground. Capacitor 936 is connected in parallel with resistor 935 coupled between node 932 and ground.

Drive control signals for each of the high side buck transistor 918, low side buck transistor 922, high side boost transistor 930, and low side boost transistor 934 are provided from modulator and driver circuit 704. Referring now to FIG. 10, there is a schematic block diagram of a modulator and driver circuit 704 for generating these gate drive switching signals shown in more detail. The buck mode control logic and driver 1002 is coupled to the high side buck transistor 918 in response to the PWM signal PWM_BUCK provided from the SR latch 1004 and the mode control signal provided from the maximum duty cycle detection and mode selection logic 1006. Generates an HD_BUCKn signal and generates an LD_BUCKn signal for the low side buck transistor 922.

The boost mode control logic and driver 1008 sends HD to the transistor 930 in response to the PWM control signal PWM_BOOST from the SR latch 1010 and the mode control signal from the maximum duty cycle detection and mode selection logic 1006. A boost n drive signal and an LD_BOOSTn drive signal for transistor 934. Transistors 918 and 922 are power switches for the buck boost converter in the buck mode of operation. In the buck mode of operation, transistor 930 is always on and transistor 934 is always off. Similarly, in boost mode of operation, buck mode control logic and driver 1002 and boost mode control logic and driver control boost transistor 320 and boost transistor 324, which include power FET switches. In the boost mode of operation, transistor 918 is always on while transistor 922 is always off. The SR latch 1004 generates a PWM_BUCK signal for the buck mode control logic and driver 1002 in response to a clock signal provided to the S input of the SR latch 1004 and a logic signal applied to the R input of the SR latch 1004. Generate. The PWM signal PWM_BOOST is provided from the Q output of the SR latch 1010 in response to a clock input received at the R input of the SR latch 1010 and a logic input provided to the S input.

Maximum duty cycle detection and mode selection logic 1006 provides a mode signal to each of buck mode control logic and driver 1002 and boost mode control logic and driver 1008. The maximum duty cycle detection and mode selection logic 1006 is in response to the PWM_BUCK and PWM_BOOST signals provided from the outputs of the SR latches 1004 and 1010, respectively, and the buck mode control logic and driver 1002 and the boost mode control logic and driver 1008. Generates an output control signal MODE for each of them. The maximum duty cycle detection and mode selection logic 1006 determines when a maximum duty cycle condition exists between the buck and boost modes of operation in response to the output voltage V _OUT approaching the input voltage V _IN . When the maximum duty cycle condition is detected, the maximum duty cycle detection and mode selection logic 1006 generates a logically "high" value for the MAX_D signal.

Maximum duty cycle detection and mode selection logic 1006 requires the buck boost converter to switch to either the buck mode of operation or the boost mode of operation and whether to generate a mode control signal MODE to indicate this change. Judge. In order to switch smoothly from buck operation to boost operation or from boost operation to buck operation, the determination of the maximum duty cycle is introduced into the control scheme by the maximum duty cycle detection and mode selection logic 1006. Whenever a maximum duty cycle condition is detected, the MAX_D signal logically goes to a "high" state. This typically occurs when the input voltage V _IN is close to the output voltage V _OUT or when a load transient occurs at the output. The maximum duty cycle detection and mode selection logic 1006 determines whether the operation mode of the buck boost converter is buck or boost. Each time a MAX_D logically "high" signal is detected, a simple control method is implemented, such as the operating mode toggled. More sophisticated control methods can be applied by using multiple MAX_D signals. There are two operating in the buck boost converter, either buck or boost, and only two modes.

The mode output "MODE" signal of the maximum duty cycle detection and mode selection logic 1006 may drive the operating circuit, e.g., current sensing and switch driver control logic, depending on whether the converter is in buck mode or boost mode of operation. It behaves like the multiplexer control signal you select. Thus, the mode control signal selects either the buck mode control logic driver 1002 or the boost mode control logic and driver 1008 according to the mode of operation and also provides a current sense compensation signal provided from the output of the multiplexer 1012. Select.

Multiplexer 1012 is connected to output either of the two V _SUM _BUCK signal or a signal V _SUM _BOOST. The V _SUM _ BUCK signal includes the _sum of the current sensed from the current sensor 916, the buck mode offset signal, and the buck slope compensation signal added together in the adder circuit 1014. V _SUM _BOOST signal is generated from the adder 1016 by adding the ISNS input current measurement signal, the boost mode, the offset signal and the boost slope compensation signal from the current sensor 916 together. The current voltage I _SNS sensed from the current sensor 916 is summed together with the buck mode offset or boost mode offset to ensure that the error amplifier 910 operates with a suitable DC bias. A buck compensation slope or boost compensation slope is added to the sensed current to avoid low frequency oscillations in large duty cycle operation. Each of the V _SUM _ BOCK compensation signal and the V _SUM _ BOOST compensation signal is provided to an input of the multiplexer 1012. Depending on whether the buck-boost converter is operating in the buck mode of operation or in the boost mode of operation, either V _{SUM _ BUCK} (buck mode) or V _{SUM _ BOOST} (boost mode) is determined by the multiplexer 1012. Selected in response to the mode signal, the selected signal is provided as the output current compensation signal V _SUM .

The V _SUM signal is provided to the inverting input of the PWM comparator 1015. The non-inverting input of the PWM comparator 1015 is connected to receive the voltage error signal V _COMP from the error amplifier 910. The V _COMP signal is used as described above in connection with the single phase mode of operation in the polyphase mode of operation. The output of the PWM comparator 1015 is provided as an input to the inverter 1017. The inverted output from inverter 1017 is provided to a first input of OR gate 1018 and a first input of AND gate 1020. The other input of the OR gate 1018 is coupled to receive the MAX_D signal from the output of the maximum duty cycle detection and mode selection logic 1006. The other input of AND gate 1020 is connected to receive the inverted MAX_D signal from inverter 1022. The output of the OR gate 1018 provides a logic signal to the R input of the SR latch 1004 to enable generation of a buck PWM signal. The output of AND gate 1020 is provided to inverter 1024. The output of inverter 1024 provides an S input to SR latch 1010 to assist in the generation of a boost PWM signal. Maximum duty cycle detection and mode selection logic 1006 generates a MAX_D control signal and a mode control signal in response to a PWM_BUCK signal from the output of the SR latch 1004, a PWM_BOOST signal from the SR latch 1010, and a clock input signal. .

Referring now to FIG. 11, there is an implementation of the illustrated maximum duty cycle detection and mode selection logic 1006. The MAX_D signal is provided to the S input of SR latch 1102. The clock input CLK is provided to the R input of the SR latch 1102. The Q output of the SR latch 1102 is provided to one input of the pair of AND gates 1104 and 1106. AND gate 1104 receives at its input a PWM_BUCK signal, an inverted mode signal input from inverter 1108 and an output of SR latch 1102. Similarly, AND gate 1106 receives the output of SR latch 1102, the mode signal, and an inverted version of the PWM_BOOST signal from inverter 1110 at the input of AND gate 1106. The output of AND gate 1104 is provided to the S input of SR latch 1112. The R input of the SR latch receives the output of AND gate 1106. The Q output of SR latch 1112 provides the MODE_PRE signal provided to the D input of delay latch 1114. The clock input of delay latch 1114 is connected to receive the CLK signal and the Q output of delay latch 1114 provides a MODE signal.

The basic operation of the circuit of FIG. 11 is as follows. When V _IN approaches V _OUT , the duty cycle approaches 100%. In order to maintain switching for each cycle, the maximum duty cycle signal MAX_D is preset. Whenever the PWM signals PWM_BUCK and PWM_BOOST reach the MAX_D value, the signal MODE_PRE is set or reset according to the current operating mode (buck or boost). However, MODE_PRE is not first applied to the modulator but only valid upon receipt of the next clock signal pulse, and the rising edge of the clock sets the mode signal and adjusts the modulator's operating mode. Each modulator has its own independent decision circuit.

Referring now to FIG. 12, there are two phase non-inverting buck boost converters operating in the illustrated buck mode steady state where V _IN is greater than V _OUT . These waveforms show the buck boost mode operating in buck mode, where V _IN is greater than V _OUT . Inductor currents are interleaved to obtain current sharing and small output ripple. The current is balanced in each phase.

Referring now to FIG. 13, there are two phase non-inverting buck boost converters in the buck mode of the illustrated operation. Inductor currents are interleaved in a more complicated way than pure buck mode and pure boost mode. In this operating region, the converter moves back and forth between buck and boost modes to regulate the output voltage. In this way, one phase can operate in buck mode while another phase operates in boost mode. In this way, output ripple is reduced.

Referring now to FIG. 14, there are two phase non-inverting buck boost converters operating in the illustrated buck mode, where V _IN is smaller than V _OUT . Inductor currents are interleaved to obtain current sharing and small output ripple. In each phase, the current is balanced.

Thus, by placing multiple buck boost power stages in parallel, more power is obtained. The design obtains current balancing without the addition of additional circuitry required to obtain current balancing results. Smooth line transitions are also provided between all with small output ripple.

It will be appreciated by those skilled in the art having the benefit of this disclosure that this non-inverting buck boost voltage converter provides improved operation when transitioning between buck and boost modes of operation. It is to be understood that the drawings and detailed description are to be regarded in an illustrative rather than a restrictive sense, and are not intended to be limited to the particular forms and examples disclosed. On the contrary, any further modifications, changes, rearrangements, alternatives, alternatives, design choices, and embodiments apparent to those skilled in the art are included without departing from the spirit and scope of the invention, as defined by the following claims. . Accordingly, it is intended that the following claims be interpreted to include all such alternative variations, modifications, rearrangements, substitutions, alternatives, design choices, and examples.

124: buck boost control
202: buck / boost converter
208: driver logic
210: error amplifier and PWM control logic
212 current slope compensation circuit
214: current sensor
216: mode control logic
330: Buck Mode Control Logic and Driver
332: Boost Mode Control Logic and Driver
340: Maximum duty cycle detection
342: mode selection logic
344, 1012: multiplexer
702: error amplifier
704 modulators and drivers
706: buck boost converter
708: current sensor
802: PWM logic
804: drive logic
806: mode control logic
808: current slope compensation circuit
1002: Buck Mode Control Logic and Driver
1006: Maximum Duty Cycle Detection and Mode Selection
1008: Boost Mode Control Logic and Driver

Claims (23)

Each of the plurality of buck boost converters for generating a regulated output voltage in response to an input voltage associated with a separate phase of the multiphase non-inverting buck boost voltage converter;
Said plurality of current sensors of a plurality of current sensors coupled to an associated buck boost converter of said plurality of buck boost converters, said plurality of current sensors for monitoring input current to an associated buck boost converter and generating a current sense signal for an associated phase. Current sensor;
Draw and operate peak current mode control in the buck mode of operation in response to an error voltage and a current sense signal for the associated phase, each buck boost mode control circuit of the plurality of buck boost mode control circuits coupled to an associated buck boost converter. The plurality of buck boost mode control circuits to provide inter-phase current balancing for controlling the associated buck boost converter using valley current mode control in a boost mode of the control mode; And
And a voltage error circuit coupled to said plurality of mode control circuits and said plurality of buck boost converters for generating said error voltage in response to said regulated output voltage. . The method according to claim 1,
And the voltage error circuit further comprises an error amplifier for generating the error voltage in response to the regulated output and reference voltages. The method according to claim 1,
Each buck boost mode control circuit of the plurality of buck boost mode control circuits is:
PWM control logic for generating a buck PWM control signal and a boost PWM control signal in response to a maximum duty cycle detection signal, the error voltage and the current sense signal;
A buck mode control and drive circuit coupled to the PWM control logic to generate a high side buck switching transistor control signal and a low side buck switching transistor control signal in response to the buck PWM control signal and mode signal;
A boost mode control and drive circuit coupled to the PWM control logic to generate a high side boost switching transistor control signal and a low side boost switching transistor control signal in response to the boost PWM control signal and the mode signal; And
Mode control logic coupled to the buck mode control and drive circuit and the boost mode control and drive circuit for generating the maximum duty cycle detection signal and the mode signal in response to the buck PWM control signal and the boost PWM control signal. The multi-phase non-inverting buck boost voltage converter further comprising. The method of claim 3,
A current control compensation circuit for generating a compensation voltage, wherein in response to the mode signal in a first state, the compensation voltage is generated in response to a monitored input current, a buck mode offset signal and a buck mode slope compensation signal; And in response to the mode signal in a second state, the compensation voltage is generated in response to the monitored input current, boost mode offset signal, and boost mode slope compensation signal. 5. The method of claim 4,
The current control compensation circuit is:
A first adder for adding the monitored input current, the buck mode offset signal and the buck mode slope compensation signal to generate a buck voltage compensation signal;
A second adder for adding the monitored input current, the boost mode offset signal and the boost mode slope compensation signal to generate a boost voltage compensation signal; And
And a multiplexer for selecting the buck voltage compensation signal or the boost voltage compensation signal as the voltage compensation signal in response to the mode signal. The method of claim 3,
The mode control logic is:
A maximum duty cycle detection circuit for detecting a maximum duty cycle condition and generating the maximum duty cycle detection signal in response to the buck PWM control signal and the boost PWM control signal; And
And a mode selection circuit for generating said mode signal indicative of operation in said boost mode or said buck mode in response to said maximum duty cycle detection signal and a clock signal. The method of claim 3,
The mode control logic is:
First control logic to set a first value in response to the buck PWM control signal or the boost PWM control signal reaching a maximum duty cycle value; And
And a second control logic for outputting the first value as the mode signal in response to a clock signal. The method of claim 3,
Each buck boost converter of the plurality of buck boost converters is:
High side buck switching transistors;
Low side buck switching transistor;
High side boost switching transistors; And
Further comprising a low side boost switching transistor,
In response to the high side boost switching transistor control signal and the low side boost switching transistor control signal in the buck mode of operation, the high side boost switching transistor turns on and the low side boost switching transistor turns off, and the high side buck switching A transistor and the low side buck switching transistor are selectively switched in response to the high side buck switching transistor control signal and the low side buck switching transistor control signal, and
In the boost mode of operation, in response to the high side buck switching transistor control signal and the low side buck switching transistor control signal, the high side buck switching transistor is turned on and the low side buck switching transistor is turned off, and the high side boost And the switching transistor and the low side boost switching transistor are selectively switched in response to the high side boost switching transistor control signal and the low side boost switching transistor control signal. 5. The method of claim 4,
The PWM control logic is:
A PWM comparator for comparing said compensation voltage with said error voltage and generating a first PWM signal in response thereto;
PWM control logic for generating a second PWM signal and a third PWM signal in response to the first PWM signal and the maximum duty cycle detection signal;
A first latch for generating the buck PWM control signal in response to the second PWM signal and a clock signal; And
And a second latch for generating said boost PWM control signal in response to said third PWM signal and said clock signal. The method according to claim 1,
And said error voltage provided to each buck boost mode control circuit of said plurality of buck boost mode control circuits provides said current balancing between said phases. A method for controlling a multiphase non-inverting buck boost voltage converter,
Each buck boost converter of the plurality of buck boost converters generating a regulated output voltage in response to an input voltage to the plurality of buck boost converters associated with a separate phase of the multiphase non-inverting buck boost voltage converter;
Monitoring an input current for each buck boost converter;
Generating a current sense signal for each of the buck boost converters;
Controlling each of the buck boost converters using peak current mode control in a buck mode of operation and valley current mode control in a boost mode of operation in response to an error voltage and the current sense signal associated with the buck boost converter; And
Balancing a plurality of phase currents between the plurality of buck boost converters in response to the error voltage and the current sense signal for each of the buck boost converters. Control method. 12. The method of claim 11,
And generating the error voltage in response to the regulated output voltage and a reference voltage. 12. The method of claim 11,
The controlling step is:
Generating a buck PWM control signal in response to a maximum duty cycle detection signal, the error voltage and a compensation voltage; And
Generating a high side buck switching transistor control signal and a low side buck switching transistor control signal in response to the buck PWM control signal and the mode signal. 12. The method of claim 11,
In the boost mode of operation the controlling step is:
Generating a buck PWM control signal in response to the maximum duty cycle detection signal, error voltage and compensation voltage;
Generating a boost PWM control signal in response to the maximum duty cycle detection signal, the error voltage, and the compensation voltage;
Generating a high side boost switching transistor control signal and a low side boost switching transistor control signal in response to the boost PWM control signal and a mode signal; And
And generating the maximum duty cycle detection signal and the mode signal in response to the buck PWM control signal and the boost PWM control signal. 15. The method of claim 14,
Generating the compensation voltage, wherein in response to the mode signal in a first state, the compensation voltage comprises a monitored input current, a buck mode offset signal and a buck mode slope compensation signal, and a second In response to the mode signal in a state, the compensation voltage comprises the monitored input current, a boost mode offset signal, and a boost mode slope compensation signal. 16. The method of claim 15,
Generating the compensation voltage may include:
Adding the monitored input current, the buck mode offset signal and the buck mode slope compensation signal to generate a buck voltage compensation signal;
Adding the monitored input current, the boost mode offset signal and the boost mode slope compensation signal to generate a boost voltage compensation signal;
Selecting the buck voltage compensation signal or the boost voltage compensation signal as the voltage compensation signal in response to the first state or the second state. . 15. The method of claim 14,
The generating of the maximum duty cycle detection signal and the mode signal includes:
Detecting a maximum duty cycle condition in response to the buck PWM control signal and the boost PWM control signal;
Generating the maximum duty cycle detection signal in response to the detected maximum duty cycle condition; And
Generating the mode signal indicative of operation in the boost mode or the buck mode in response to the maximum duty cycle detection signal and a clock signal. 15. The method of claim 14,
Generating the buck PWM control signal and the boost PWM control signal may include:
Comparing the compensation voltage with the error voltage and generating a first PWM signal in response thereto;
Generating a second PWM signal and a third PWM signal in response to the first PWM signal and the maximum duty cycle detection signal;
Generating the buck PWM control signal in response to the second PWM signal and a clock signal; And
And generating the boost PWM control signal in response to the third PWM signal and the clock signal. 14. The method of claim 13,
The controlling step is:
Comparing the compensation voltage with the error voltage and generating a first PWM signal in response thereto;
Generating a second PWM signal and a third PWM signal in response to the first PWM signal and the maximum duty cycle detection signal;
Generating the buck PWM control signal in response to the second PWM signal and a clock signal; And
And generating the boost PWM control signal in response to the third PWM signal and the clock signal. 12. The method of claim 11,
The balancing step further includes comparing the current sense signal for each buck boost converter with the error voltage associated with the phase of the multiphase non-inverted buck boost voltage converter. Control method of the voltage converter. Monitoring the input current of the buck boost voltage converter to the first buck boost converter;
Generating a first current sense signal in response to the input current;
Monitoring the output voltage of the buck boost voltage converter;
Generating a compensation voltage signal in response to the output voltage;
Generating a first plurality of drive signals in response to the compensation voltage signal and the first current sense signal;
Generating the output voltage in response to a first plurality of drive signals and a first current sense signal;
Monitoring the input current of the buck boost voltage converter to a second buck boost converter;
Generating a second current sense signal in response to the input current;
Generating a second plurality of drive signals in response to the compensation voltage signal and the second current sense signal; And
Generating the output voltage in response to the second plurality of drive signals and the second current sense signal. Operating the buck boost converter in a first mode;
Determining whether a first maximum duty cycle condition is detected;
Operating the buck boost converter in a second mode if the first maximum duty cycle condition is detected;
Determining whether a second maximum duty cycle condition is detected; And
If the second maximum duty cycle condition is detected, operating a buck boost converter in the first mode. 23. The method of claim 22,
The first mode is a peak current control mode of operation, the second mode is a valley current control mode of operation, and the determining operation is performed by a mode control logic unit.

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