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TWI452640B - Semiconductor package and method for packaging the same - Google Patents

Semiconductor package and method for packaging the same Download PDF

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Publication number
TWI452640B
TWI452640B TW098120387A TW98120387A TWI452640B TW I452640 B TWI452640 B TW I452640B TW 098120387 A TW098120387 A TW 098120387A TW 98120387 A TW98120387 A TW 98120387A TW I452640 B TWI452640 B TW I452640B
Authority
TW
Taiwan
Prior art keywords
semiconductor package
package structure
wire
pad
carrier
Prior art date
Application number
TW098120387A
Other languages
Chinese (zh)
Other versions
TW201030866A (en
Inventor
Wen Pin Huang
Cheng Tsung Hsu
Cheng Lan Tseng
Chih Cheng Hung
Original Assignee
Advanced Semiconductor Eng
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Semiconductor Eng filed Critical Advanced Semiconductor Eng
Priority to US12/642,081 priority Critical patent/US20100200981A1/en
Publication of TW201030866A publication Critical patent/TW201030866A/en
Application granted granted Critical
Publication of TWI452640B publication Critical patent/TWI452640B/en

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  • Wire Bonding (AREA)

Description

半導體封裝構造及其封裝方法Semiconductor package structure and packaging method thereof

本發明係有關於一種半導體封裝方法，更特別有關於一種半導體封裝方法之銲線接合製程，在銅銲線之球狀部的電燒製程時，使用惰性氣體可有效地阻隔氧氣與銅接觸。The present invention relates to a semiconductor packaging method, and more particularly to a wire bonding process for a semiconductor packaging method. In an electro-burning process of a ball portion of a copper bonding wire, an inert gas is used to effectively block oxygen from contacting the copper.

參考第1圖，在半導體封裝構造製程中，銲線接合方法的技術廣泛地將銲線14應用於晶片10之接墊11與基板12之接墊13間的電性連接。打線接合製程是以金線為主，但銅線具有低成本的優勢。相較於金，銅具有較佳的導電性及導熱性，可使銅銲線之線徑較細及散熱效率較佳。然而，銅具有延性不足及易氧化的缺點，使銅製銲線在應用上仍有所限制。Referring to FIG. 1, in the semiconductor package structure process, the wire bonding method widely applies the bonding wire 14 to the electrical connection between the pads 11 of the wafer 10 and the pads 13 of the substrate 12. The wire bonding process is mainly gold wire, but the copper wire has the advantage of low cost. Compared with gold, copper has better conductivity and thermal conductivity, which makes the wire diameter of the brazing wire thinner and the heat dissipation efficiency better. However, copper has the disadvantages of insufficient ductility and easy oxidation, which makes the copper bonding wire still limited in application.

目前，銅銲線只能應用在大尺寸之晶片接墊或低介電值材料(low-K)晶圓之晶片接墊，其原因在於銅銲線接合製程之成功將取決於晶片接墊之結構強度。為了避免銅銲線接合製程之失敗，小尺寸晶片接墊將被限制。At present, copper bonding wires can only be applied to wafer pads of large size wafer pads or low dielectric material (low-K) wafers because the success of the brazing wire bonding process will depend on the wafer pads. Structural strength. In order to avoid the failure of the brazing wire bonding process, small-sized wafer pads will be limited.

參考第2至4圖，其顯示習知銅銲線接合方法。參考第2圖，藉由一打線機，提供一銅銲線20，其包括一銅線22。然後，將該銅線22之一線端電燒形成一銅球24而連接於該銅線22。參考第3圖，將該銅球24施壓而變形。參考第4圖，藉由一振動製程，將該銅球24接合於一鋁接墊32。Referring to Figures 2 through 4, there is shown a conventional brazing wire joining method. Referring to Figure 2, a wire bond wire 20 is provided which includes a copper wire 22 by a wire machine. Then, one of the copper wires 22 is electrically fired to form a copper ball 24 and is connected to the copper wire 22. Referring to Fig. 3, the copper ball 24 is pressed and deformed. Referring to FIG. 4, the copper ball 24 is bonded to an aluminum pad 32 by a vibration process.

然而，在該銅球24之電燒製程時，由於電燒溫度高，因此銅容易發生氧化，進而造成該銅球24之球形失敗(亦即非球形)。再者，在該銅球24之施壓製程時，由於銅之硬度較大，因此施壓時該銅銲線20所造成之力將可能擠出該鋁接墊32之鋁材料34至該銅球24之周圍。However, in the electrocalging process of the copper ball 24, since the electrosintering temperature is high, copper is easily oxidized, thereby causing the spherical failure of the copper ball 24 (i.e., non-spherical). Moreover, during the pressing process of the copper ball 24, since the hardness of the copper is large, the force caused by the brazing wire 20 during the pressing will likely extrude the aluminum material 34 of the aluminum pad 32 to the copper. Around the ball 24.

因此，便有需要提供一種半導體封裝方法之銲線接合製程，能夠解決前述的問題。Therefore, there is a need to provide a wire bonding process for a semiconductor packaging method that can solve the aforementioned problems.

本發明提供一種半導體封裝方法，包含下列步驟：提供一承載件；設置一晶片於該承載件上，其中該晶片具有一主動表面及一相對背面；設置一接墊於該晶片之該主動表面上；提供一銅銲線，具有一線狀部；通過一惰性氣體於該線狀部之一線端的周圍，並將該線狀部之該線端形成一球狀部，其中該球狀部連接於該線狀部，該球狀部每一邊緣到該銅銲線中心線之距離大體上相等，該線狀部及該球狀部分別具有線徑D1及球徑D2，且 ；將該銅銲線之該球狀部接合於該接墊，其中接合後該球狀部形成一弧狀接合部，該弧狀接合部每一邊緣到該銅銲線中心線之距離大體上相等，接合後之線狀部具有截面直徑D1’，該弧狀接合部具有截面直徑D2’，且3×D1’；以及以一封膠，包覆該晶片和該銅銲線，並覆蓋該承載件，使該封膠、該晶片及該承載件形成一封裝體。The present invention provides a semiconductor package method comprising the steps of: providing a carrier; providing a wafer on the carrier, wherein the wafer has an active surface and an opposite back surface; and a pad is disposed on the active surface of the wafer Providing a copper bonding wire having a linear portion; passing an inert gas around a wire end of the linear portion, and forming the wire end of the linear portion into a spherical portion, wherein the spherical portion is connected to the wire portion a linear portion, each edge of the spherical portion is substantially equal to a distance from a center line of the brazing wire, and the linear portion and the spherical portion respectively have a wire diameter D1 and a ball diameter D2, and Bonding the ball portion of the brazing wire to the pad, wherein the ball portion forms an arcuate joint portion after joining, the distance from each edge of the arcuate joint portion to the center line of the brazing wire is substantially Equally, the joined linear portion has a cross-sectional diameter D1', and the arcuate joint has a cross-sectional diameter D2', and 3×D1′; and coating the wafer and the brazing wire with a glue and covering the carrier to form the encapsulant, the wafer and the carrier into a package.

在本發明之銅銲線的球狀部之電燒製程時，由於該惰性氣體可有效地阻隔氧氣與銅接觸，因此即使電燒溫度高，銅將不容易發生氧化，進而造成該球狀部之球形成功。In the electro-burning process of the spherical portion of the brazing wire of the present invention, since the inert gas can effectively block the contact between oxygen and copper, even if the electric firing temperature is high, the copper will not easily oxidize, thereby causing the spherical portion. The sphere is successful.

為了讓本發明之上述和其他目的、特徵、和優點能更明顯，下文將配合所附圖示，作詳細說明如下。The above and other objects, features, and advantages of the present invention will become more apparent from the accompanying drawings.

參考第5至12圖，其顯示本發明之一實施例之半導體封裝方法。參考第5圖，提供一承載件112，具有上表面113與相對之下表面114。設置一晶片110於該承載件112之上表面上，其中該晶片110具有主動表面115及相對背面116。設置一接墊132(諸如鋁接墊)於該晶片110之主動表面115上。參考第6圖，在本實施例中，藉由一打線機102，提供一銅銲線120，其包括一線狀部122。參考第7圖，將惰性氣體140通過該線狀部122之一線端123的周圍，並藉由一電燒製程，諸如具有高壓電之電子燒球器(electrical flame-off；EFO)104的放電製程，將該線狀部122之一線端123形成一球狀部124。詳細而言，當該電子燒球器104之點火電極106朝該線狀部122之一線端123移動，且間隙逐漸縮小至一預定值內，則該點火電極106與該線狀部122之間會瞬間產生高壓放電。此一高壓放電會使該線狀部122之一線端123迅速熔融，並在表面張力與重力作用下形成球狀。該銅銲線120之含銅重量百分比可為99.9%(3N)、99.99%(4N)或99.999%(5N)。在本發明之銅銲線的球狀部124之電燒製程時，由於該惰性氣體140(諸如包括氮氣)可有效地阻隔氧氣與銅接觸，因此即使電燒溫度高，銅將不容易發生氧化，進而造成該球狀部之球形成功。較佳地，當該惰性氣體140包括氮氣及氫氣之混合氣時，則可更有效地阻隔氧氣與銅接觸。Referring to Figures 5 through 12, there is shown a semiconductor package method in accordance with one embodiment of the present invention. Referring to Figure 5, a carrier 112 is provided having an upper surface 113 and an opposite lower surface 114. A wafer 110 is disposed on an upper surface of the carrier 112, wherein the wafer 110 has an active surface 115 and an opposite back surface 116. A pad 132 (such as an aluminum pad) is disposed on the active surface 115 of the wafer 110. Referring to Fig. 6, in the present embodiment, a wire bonding wire 120 is provided by a wire bonding machine 102, which includes a linear portion 122. Referring to FIG. 7, the inert gas 140 is passed around the line end 123 of the linear portion 122 and is subjected to an electro-burning process such as an electrical flame-off (EFO) 104 having a high voltage. In the discharge process, one of the line ends 123 of the linear portion 122 forms a spherical portion 124. In detail, when the ignition electrode 106 of the electronic ball washer 104 moves toward the line end 123 of the linear portion 122 and the gap gradually decreases to a predetermined value, between the ignition electrode 106 and the linear portion 122 A high voltage discharge will occur instantaneously. This high voltage discharge causes the wire end 123 of the linear portion 122 to rapidly melt and form a spherical shape under the action of surface tension and gravity. The copper wire 120 may have a copper content percentage of 99.9% (3N), 99.99% (4N), or 99.999% (5N). In the electro-burning process of the spherical portion 124 of the brazing wire of the present invention, since the inert gas 140 (such as including nitrogen) can effectively block the contact of oxygen with copper, even if the electric firing temperature is high, copper will not easily oxidize. , which in turn causes the spherical shape of the spherical portion to succeed. Preferably, when the inert gas 140 comprises a mixture of nitrogen and hydrogen, the oxygen can be more effectively blocked from contacting the copper.

參考第8圖，該銅銲線120之球狀部124連接於該線狀部122，該球狀部124之剖面面積大於該線狀部122之剖面面積。該球狀部124之球形成功表示該球狀部124每一邊緣到銅銲線120中心線之距離D大體上相等。由於該球狀部124之球形成功，因此該線狀部122之線徑D1及該球狀部124之球徑D2將會符合的關係，如下表1：電子燒球器104之電燒電流及時間及銲線120之線狀部122線徑D1及球狀部124球徑D2的數據。Referring to FIG. 8, the spherical portion 124 of the brazing wire 120 is connected to the linear portion 122, and the cross-sectional area of the spherical portion 124 is larger than the cross-sectional area of the linear portion 122. The spherical success of the bulb 124 indicates that the distance D from each edge of the bulb 124 to the centerline of the brazing wire 120 is substantially equal. Since the spherical shape of the spherical portion 124 is successful, the wire diameter D1 of the linear portion 122 and the spherical diameter D2 of the spherical portion 124 will conform to The relationship between the electric burning current and time of the electronic ball washer 104 and the wire diameter D1 of the linear portion 122 of the bonding wire 120 and the spherical diameter D2 of the spherical portion 124 are as follows.

參考第9圖，在另一實施例中，該銅銲線120之線狀部122外圍係包覆一抗氧化金屬層。該抗氧化金屬層可為鈀，亦即該銅銲線120可置換為銅鈀銲線120’。該線狀部122’包括一銅本體122a及一鈀層122b，該鈀層122b包覆該銅本體122a。該球狀部124’包括銅及鈀金屬。該銅銲線120含鈀重量百分比為0.8%~2.7%。Referring to FIG. 9, in another embodiment, the outer portion of the linear portion 122 of the brazing wire 120 is coated with an anti-oxidation metal layer. The anti-oxidation metal layer may be palladium, that is, the braze wire 120 may be replaced with a copper palladium wire 120'. The linear portion 122' includes a copper body 122a and a palladium layer 122b, and the palladium layer 122b covers the copper body 122a. The spherical portion 124' includes copper and palladium metal. The brazing wire 120 has a palladium weight percentage of 0.8% to 2.7%.

將該銅銲線120之球狀部124接合於該接墊132，如此以完成本發明之銲線接合製程。詳細而言，參考第10圖，該銲線120之球狀部124係位於該接墊132上方，然後將該球狀部124施壓而變形成一弧狀接合部124”。參考第11圖，然後藉由一振動製程(諸如超音波振動製程)，將該弧狀接合部124”接合於該接墊132，如此以形成本發明之銲線接合結構。在該球狀部124接合於該接墊132後，該線狀部122及弧狀接合部124”分別具有截面直徑D1’及截面直徑D2’。通常接合後之該線狀部之線徑D1’維持與D1相同。此時，該線狀部122之截面直徑D1’及該弧狀接合部124”之截面直徑D2’將符合的關係，如下表2：接合後之該銅銲線120之線狀部122之截面直徑D1’及該弧狀接合部124”之截面直徑D2’的數據。The ball portion 124 of the brazing wire 120 is bonded to the pad 132 to complete the wire bonding process of the present invention. In detail, referring to FIG. 10, the spherical portion 124 of the bonding wire 120 is located above the pad 132, and then the ball portion 124 is pressed to form an arcuate joint portion 124". Referring to FIG. The arcuate joint 124" is then joined to the pad 132 by a vibratory process (such as an ultrasonic vibration process) to form the wire bond structure of the present invention. After the spherical portion 124 is joined to the pad 132, the linear portion 122 and the arcuate joint portion 124" respectively have a cross-sectional diameter D1' and a cross-sectional diameter D2'. The wire diameter D1 of the linear portion after the normal joint 'Maintains the same as D1. At this time, the cross-sectional diameter D1' of the linear portion 122 and the cross-sectional diameter D2' of the arc-shaped joint portion 124" will conform to The relationship is as follows: Table 2: Data of the cross-sectional diameter D1' of the linear portion 122 of the brazing wire 120 after joining and the cross-sectional diameter D2' of the arc-shaped engaging portion 124".

再者，在該球狀部之施壓及振動製程時，由於銅之硬度較大，因此施壓及振動時該銅銲線120所造成之力將可能將金屬擠出殘留物134，諸如該接墊132(諸如鋁接墊)之鋁材料或該銅銲線120之銅材料至該弧狀接合部124”之周圍，如第11圖所示。該晶片包括一保護層136，其形成於該主動表面115上，並暴露出該接墊132，而使該接墊132具有一裸露區域A。若接合前之該接墊132之厚度T介於約0.8與約2.5μm之間，則該弧狀接合部124”之邊緣可與該接墊132裸露區域A之邊緣的間距G≧4μm，如此以避免施壓時該銅銲線120所造成之力將可能將金屬擠出殘留物134至其他接墊或銲線，進而造成電性短路。或者，若接合前之該接墊132係下方具有至少一銅層(或鋁層)及低介電材料層(圖未示)上方，接合前之該鋁接墊132、銅層(或鋁層)及低介電材料層的總厚度係介於約1.2與約1.5μm之間)，則接合後之該弧狀接合部124”及接墊132亦符合該弧狀接合部124”之邊緣與該接墊132裸露區域A之邊緣的間距G≧4μm。再者，參考第12圖，該弧狀接合部124”每一邊緣到該銅銲線120中心線之距離D’大體上相等。Moreover, during the pressing and vibrating process of the spherical portion, since the hardness of the copper is large, the force caused by the brazing wire 120 during pressing and vibration may cause the metal to extrude the residue 134, such as the An aluminum material of the pad 132 (such as an aluminum pad) or a copper material of the brazing wire 120 is formed around the arcuate joint portion 124" as shown in Fig. 11. The wafer includes a protective layer 136 formed on The pad 132 is exposed on the active surface 115, and the pad 132 has a bare area A. If the thickness T of the pad 132 before bonding is between about 0.8 and about 2.5 μm, the The edge of the arcuate joint portion 124" may be spaced from the edge of the exposed portion A of the pad 132 by a distance G ≧ 4 μm, so as to avoid the force caused by the brazing wire 120 when the pressure is applied, the metal may be squeezed to the residue 134 to Other pads or wire bonds, which in turn cause electrical shorts. Alternatively, if the pad 132 before bonding has at least one copper layer (or aluminum layer) and a low dielectric material layer (not shown) underneath, the aluminum pad 132, copper layer (or aluminum layer) before bonding. And the total thickness of the low dielectric material layer is between about 1.2 and about 1.5 μm), then the arcuate joint 124" and the pad 132 after bonding also conform to the edge of the arcuate joint 124" The pitch of the edge of the exposed area A of the pad 132 is G ≧ 4 μm. Further, referring to Fig. 12, the distance D' of each edge of the arcuate joint portion 124" to the center line of the brazing wire 120 is substantially equal.

另外，在另一實施例中，若該銅銲線120置換為銅鈀銲線120’(如第9圖所示)，則該弧狀接合部124”(如第12圖所示)成份為銅和鈀混合物。In addition, in another embodiment, if the brazing wire 120 is replaced by a copper palladium wire 120' (as shown in FIG. 9), the arcuate joint portion 124" (as shown in FIG. 12) is A mixture of copper and palladium.

參考第13圖，在本實施例中，該承載件112為基板112a。該銅銲線120之一線端電性連接於該晶片110之接墊132(亦即第一接墊)，該銲線120之另一線端電性連接於該基板112a之接墊142(亦即第二接墊)。該第一接墊及第二接墊可為複數個。該晶片110之接墊132電性連接於該晶片之線路(圖未示)。該基板112a包括一對外電性連接點146，其位於該下表面114。Referring to Figure 13, in the present embodiment, the carrier 112 is a substrate 112a. One end of the wire bonding wire 120 is electrically connected to the pad 132 of the chip 110 (ie, the first pad), and the other wire end of the bonding wire 120 is electrically connected to the pad 142 of the substrate 112a (ie, Second pad). The first pad and the second pad may be plural. The pads 132 of the wafer 110 are electrically connected to the wiring of the wafer (not shown). The substrate 112a includes an external electrical connection point 146 that is located on the lower surface 114.

再參考第13圖，最後以一封膠138，包覆該晶片110和該銅銲線120，並覆蓋該承載件112，使該封膠138、該晶片110及該承載件112形成一球格陣列封裝體(BGA package)，亦即本發明之半導體封裝構造100。該封膠138組成成分包括氯離子和鈉離子，如此可使該銅銲線120不易被氧化。該封膠138之組成成分更包括溴離子。該封膠138之pH值可介於4~7之間。Referring again to FIG. 13, the wafer 110 and the brazing wire 120 are covered with a glue 138, and the carrier 112 is covered to form the ball 138, the wafer 110 and the carrier 112 into a ball. A package package (BGA package), that is, a semiconductor package structure 100 of the present invention. The composition of the sealant 138 includes chloride ions and sodium ions, so that the brazing wire 120 can be prevented from being oxidized. The composition of the sealant 138 further includes bromide ions. The pH of the sealant 138 can be between 4 and 7.

再參考第13圖，該半導體封裝構造100包括該承載件112、晶片110、接墊132(諸如鋁接墊)、銅銲線120及封膠138。該承載件112具有一上表面113(亦即承載表面)與相對之一上表面114。該晶片110具有一主動表面115與相對之一背面116，該晶片110的背面116係設置於該承載件112之該上表面113上，亦即該晶片110之背面116係設置於該承載件112之承載表面。該接墊132設置於該晶片110之主動表面115上。該銅銲線120係電性連接於該晶片110與該承載件112，該銅銲線120包含一線狀部122及一弧狀接合部124”，該弧狀接合部接合於該鋁接墊，其中該線狀部具有一截面直徑D1’，該弧狀接合部具有一截面直徑D2’，且，其中該弧狀接合部124”之邊緣與接墊132之邊緣的間距≧4μm。該封膠138包覆該晶片110、該銅銲線120和覆蓋該承載件112。Referring again to FIG. 13, the semiconductor package construction 100 includes the carrier 112, the wafer 110, the pads 132 (such as aluminum pads), the braze wires 120, and the sealant 138. The carrier 112 has an upper surface 113 (ie, a bearing surface) and an opposite upper surface 114. The wafer 110 has an active surface 115 and an opposite back surface 116. The back surface 116 of the wafer 110 is disposed on the upper surface 113 of the carrier 112, that is, the back surface 116 of the wafer 110 is disposed on the carrier 112. Bearing surface. The pad 132 is disposed on the active surface 115 of the wafer 110. The brazing wire 120 is electrically connected to the wafer 110 and the carrier 112. The brazing wire 120 includes a linear portion 122 and an arcuate joint portion 124". The arcuate joint portion is joined to the aluminum pad. Wherein the linear portion has a cross-sectional diameter D1', the arcuate joint has a cross-sectional diameter D2', and The edge of the arcuate joint portion 124" is spaced apart from the edge of the pad 132 by 4 μm. The sealant 138 covers the wafer 110, the brazing wire 120, and covers the carrier 112.

該接墊132具有一銲線接觸區及一非銲線接觸區，其中該非銲線接觸區包含銅銲線120和接墊132接合後之金屬擠出殘留物134。該金屬擠出殘留物134可為鋁或銅，如第11圖所示。The pad 132 has a bonding wire contact region and a non-bonding wire contact region, wherein the non-bonding wire contact region comprises a copper bonding wire 120 and a metal extrusion residue 134 joined by the bonding pad 132. The metal extrusion residue 134 can be aluminum or copper as shown in FIG.

參考第14圖，在另一實施例中，本發明之銲線接合結構可應用於凹槽向下(cavity down)型的封裝構造，諸如W型球格陣列封裝構造(WBGA package)，亦即本發明之另一半導體封裝構造100’。該半導體封裝構造100’大體上類似於該半導體封裝構造100，其兩者主要差異係在於該晶片110’的主動表面115係設置於該承載件112(諸如基板112a’)之上表面113上。該基板112b包括貫穿開口117，其由該上表面113延伸至該下表面114。該銅銲線120通過該貫穿開口117，該銅銲線120之一線端電性連接於該晶片110’之接墊132(亦即第一接墊)，該銲線120之另一線端電性連接於該基板112a’之接墊142(亦即第二接墊)。該第一接墊及第二接墊可為複數個。該晶片110’之接墊132電性連接於該晶片之線路(圖未示)。該基板112a’包括一對外電性連接點146，其位於該下表面114。Referring to FIG. 14, in another embodiment, the wire bonding structure of the present invention can be applied to a groove down type package structure such as a WBGA package, that is, Another semiconductor package construction 100' of the present invention. The semiconductor package construction 100' is substantially similar to the semiconductor package construction 100, the main difference of which is that the active surface 115 of the wafer 110' is disposed on the upper surface 113 of the carrier 112 (such as the substrate 112a'). The substrate 112b includes a through opening 117 that extends from the upper surface 113 to the lower surface 114. The wire bonding wire 120 passes through the through opening 117. One wire end of the copper bonding wire 120 is electrically connected to the pad 132 of the wafer 110' (ie, the first pad), and the other wire end of the bonding wire 120 is electrically connected. Connected to the pad 142 of the substrate 112a' (ie, the second pad). The first pad and the second pad may be plural. The pads 132 of the wafer 110' are electrically connected to the wiring of the wafer (not shown). The substrate 112a' includes an outer electrical connection point 146 that is located on the lower surface 114.

參考第15圖，在又一實施例中，本發明之銲線接合結構可應用於具有釘架的封裝構造，亦即本發明之又一半導體封裝構造100”。該半導體封裝構造100”大體上類似於該半導體封裝構造100，其兩者主要差異係在於該承載件112為釘架112b(leadframe)。該半導體封裝構造110”更包括一引腳接墊142”及一金屬層144。該引腳接墊142’設置於該釘架112b上。該金屬層144係覆蓋該引腳接墊142”上，該金屬層144可為銀、金或鈀之一。該引腳接墊142”係與該銅銲線120電性連接。Referring to Fig. 15, in still another embodiment, the wire bonding structure of the present invention can be applied to a package structure having a staple frame, that is, another semiconductor package structure 100" of the present invention. The semiconductor package structure 100" is substantially Similar to the semiconductor package construction 100, the main difference between the two is that the carrier 112 is a lead frame 112b. The semiconductor package structure 110" further includes a pin pad 142" and a metal layer 144. The pin pad 142' is disposed on the stud 112b. The metal layer 144 is covered by the lead pad 142 ′. The metal layer 144 can be one of silver, gold or palladium. The lead pad 142 ′′ is electrically connected to the brazing wire 120 .

雖然本發明已以前述實施例揭示，然其並非用以限定本發明，任何本發明所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作各種之更動與修改。因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。The present invention has been disclosed in the foregoing embodiments, and is not intended to limit the present invention. Any of the ordinary skill in the art to which the invention pertains can be modified and modified without departing from the spirit and scope of the invention. . Therefore, the scope of the invention is defined by the scope of the appended claims.

10．．．晶片10. . . Wafer

11．．．接墊11. . . Pad

12．．．基板12. . . Substrate

13．．．接墊13. . . Pad

14．．．銲線14. . . Welding wire

20．．．銲線20. . . Welding wire

22．．．銅線twenty two. . . Copper wire

24．．．銅球twenty four. . . Copper ball

32．．．接墊32. . . Pad

34．．．鋁材料34. . . Aluminum material

100．．．半導體封裝構造100. . . Semiconductor package construction

100’．．．半導體封裝構造100’. . . Semiconductor package construction

100”．．．半導體封裝構造100"...semiconductor package construction

102．．．打線機102. . . Wire machine

104．．．電子燒球器104. . . Electronic ball killer

106．．．點火電極106. . . Ignition electrode

110．．．晶片110. . . Wafer

110’．．．晶片110’. . . Wafer

112．．．承載件112. . . Carrier

112a．．．基板112a. . . Substrate

112a’．．．基板112a’. . . Substrate

122b．．．釘架122b. . . Nail frame

113．．．上表面113. . . Upper surface

114．．．下表面114. . . lower surface

115．．．主動表面115. . . Active surface

116．．．背面116. . . back

117．．．貫穿開口117. . . Through opening

120．．．銲線120. . . Welding wire

122．．．線狀部122. . . Linear part

122’．．．線狀部122’. . . Linear part

123．．．線端123. . . Line end

124．．．球狀部124. . . Spherical part

124’．．．球狀部124’. . . Spherical part

124”．．．弧狀接合部124"...arc joint

132．．．接墊132. . . Pad

134．．．擠出殘留物134. . . Extrusion residue

136．．．保護層136. . . The protective layer

138．．．封膠138. . . Plastic closures

140．．．惰性氣體140. . . Inert gas

142．．．接墊142. . . Pad

142’．．．接墊142’. . . Pad

142”．．．引腳接墊142"...pin pads

144．．．金屬層144. . . Metal layer

146．．．電性連接點146. . . Electrical connection point

A．．．裸露區域A. . . Bare area

G．．．間距G. . . spacing

D．．．距離D. . . distance

D’．．．距離D’. . . distance

D1．．．線徑D1. . . Wire diameter

D1’．．．線徑D1’. . . Wire diameter

D2．．．球徑D2. . . Ball diameter

D2’．．．球徑D2’. . . Ball diameter

T．．．厚度T. . . thickness

第1圖為先前技術之銲線接合方法之剖面示意圖。Figure 1 is a schematic cross-sectional view of a prior art wire bonding method.

第2至4圖為先前技術之銅銲線接合方法之剖面示意圖。2 to 4 are schematic cross-sectional views showing a prior art brazing wire bonding method.

第5圖為本發明之一實施例之半導體封裝方法之剖面示意圖，其顯示承載件及晶片。FIG. 5 is a cross-sectional view showing a semiconductor package method according to an embodiment of the present invention, showing a carrier and a wafer.

第6圖為本發明之一實施例之半導體封裝方法之剖面示意圖，其顯示電燒前之銲線。Figure 6 is a cross-sectional view showing a semiconductor package method according to an embodiment of the present invention, showing a bonding wire before electro-burning.

第7圖為本發明之一實施例之半導體封裝方法之剖面示意圖，其顯示電燒後之銅銲線。Figure 7 is a cross-sectional view showing a semiconductor package method according to an embodiment of the present invention, showing a copper bonding wire after electrospinning.

第8圖為本發明之一實施例之半導體封裝方法之剖面示意圖，其顯示電燒後之銲線之線狀部及球狀部。Fig. 8 is a schematic cross-sectional view showing a semiconductor package method according to an embodiment of the present invention, showing a linear portion and a spherical portion of a bonding wire after electro-burning.

第9圖為本發明之另一實施例之半導體封裝方法之剖面示意圖，其顯示電燒後之銅鈀銲線。Figure 9 is a cross-sectional view showing a semiconductor package method according to another embodiment of the present invention, showing a copper-palladium bonding wire after electrospinning.

第10圖為本發明之一實施例之半導體封裝方法之剖面示意圖，其顯示施壓後之銲線。Figure 10 is a cross-sectional view showing a semiconductor package method according to an embodiment of the present invention, showing a bonding wire after pressing.

第11圖為本發明之一實施例之半導體封裝方法之剖面示意圖，其顯示接合後之銲線。Figure 11 is a cross-sectional view showing a semiconductor package method according to an embodiment of the present invention, showing a bonding wire after bonding.

第12圖為本發明之一實施例之半導體封裝方法之剖面示意圖，其顯示接合後之銲線之線狀部及弧狀接合部。Fig. 12 is a schematic cross-sectional view showing a semiconductor package method according to an embodiment of the present invention, showing a linear portion and a curved joint portion of a bonding wire after bonding.

第13圖為本發明之一實施例之半導體封裝方法之剖面示意圖，其顯示封膠包覆該晶片和該銅銲線，並覆蓋基板。Figure 13 is a cross-sectional view showing a semiconductor package method according to an embodiment of the present invention, showing a sealant covering the wafer and the brazing wire, and covering the substrate.

第14圖為本發明之另一實施例之半導體封裝構造之剖面示意圖。Figure 14 is a cross-sectional view showing a semiconductor package structure according to another embodiment of the present invention.

第15圖為本發明之又一實施例之半導體封裝構造之剖面示意圖。Figure 15 is a cross-sectional view showing a semiconductor package structure according to still another embodiment of the present invention.

102．．．打線機102. . . Wire machine

104．．．電子燒球器104. . . Electronic ball killer

106．．．點火電極106. . . Ignition electrode

120．．．銲線120. . . Welding wire

122．．．線狀部122. . . Linear part

123．．．線端123. . . Line end

124．．．球狀部124. . . Spherical part

140．．．惰性氣體140. . . Inert gas

Claims (44)

一種半導體封裝構造，包括：一承載件；一晶片，具有一第一表面與相對之一第二表面，該晶片係設置於該承載件上；一接墊，設置於該晶片之該第一表面上；一銅銲線，電性連接於該晶片與該承載件，該銅銲線包含一線狀部及一弧狀接合部，該弧狀接合部接合於該接墊，其中該線狀部具有一截面直徑D1’，該弧狀接合部具有一截面直徑D2’， ，該弧狀接合部每一邊緣到該銅銲線中心線之距離大體上相等，且該弧狀接合部之邊緣與該接墊裸露區域之邊緣的間距≧4μm；以及一封膠，包覆該晶片、該銅銲線和覆蓋該承載件。A semiconductor package structure includes: a carrier; a wafer having a first surface and a second surface opposite to the carrier; the wafer is disposed on the carrier; a pad disposed on the first surface of the wafer a brazing wire electrically connected to the wafer and the carrier, the brazing wire comprising a linear portion and an arcuate joint, the arcuate joint being joined to the pad, wherein the wire has a cross-sectional diameter D1', the arcuate joint having a cross-sectional diameter D2', The distance from each edge of the arcuate joint to the centerline of the brazing wire is substantially equal, and the edge of the arcuate joint is spaced from the edge of the exposed area of the pad by 4 μm; and a glue, coated The wafer, the brazing wire, and the carrier are covered. 依申請專利範圍第1項所述之半導體封裝構造，其中該接墊具有一銲線接觸區及一非銲線接觸區，其中該非銲線接觸區包含銅銲線和接墊接合後之金屬擠出殘留物。The semiconductor package structure according to claim 1, wherein the pad has a bonding wire contact region and a non-bonding wire contact region, wherein the non-bonding wire contact region comprises a copper bonding wire and a metal extrusion after the bonding of the pads Residues. 依申請專利範圍第2項所述之半導體封裝構造，其中該金屬擠出殘留物為鋁或銅之其中一者。The semiconductor package structure of claim 2, wherein the metal extrusion residue is one of aluminum or copper. 依申請專利範圍第1項所述之半導體封裝構造，更包括：一保護層，形成於該晶片之該第一表面上，並暴露出該接墊之裸露區域。The semiconductor package structure of claim 1, further comprising: a protective layer formed on the first surface of the wafer and exposing the exposed area of the pad. 依申請專利範圍第1項所述之半導體封裝構造，其中該銅銲線含銅重量百分比為99.9%、99.99%或99.999%之其中一者。The semiconductor package structure according to claim 1, wherein the brazing wire has a copper percentage by weight of 99.9%, 99.99% or 99.999%. 依申請專利範圍第1項所述之半導體封裝構造，其中該銅銲線線狀部外圍係包覆一抗氧化金屬層。The semiconductor package structure according to claim 1, wherein the outer portion of the wire portion of the brazing wire is coated with an anti-oxidation metal layer. 依申請專利範圍第6項所述之半導體封裝構造，其中該抗氧化金屬層為鈀。The semiconductor package structure of claim 6, wherein the oxidation resistant metal layer is palladium. 依申請專利範圍第7項所述之半導體封裝構造，其中該銅銲線含鈀重量百分比為0.8%~2.7%。The semiconductor package structure according to claim 7, wherein the brazing wire has a palladium weight percentage of 0.8% to 2.7%. 依申請專利範圍第7項所述之半導體封裝構造，其中該弧狀接合部成份為銅和鈀混合物。The semiconductor package structure of claim 7, wherein the arcuate joint component is a mixture of copper and palladium. 依申請專利範圍第1項所述之半導體封裝構造，其中該接墊之厚度係介於0.8μm與2.5μm之間。The semiconductor package structure according to claim 1, wherein the thickness of the pad is between 0.8 μm and 2.5 μm. 依申請專利範圍第1項所述之半導體封裝構造，其中該接墊係下方具有至少一銅層及至少一介電材料層，其中該銅層及該介電材料層之總厚度係介於1.2μm與1.5μm之間。The semiconductor package structure of claim 1, wherein the pad has at least one copper layer and at least one dielectric material layer, wherein the total thickness of the copper layer and the dielectric material layer is 1.2. Between μm and 1.5 μm. 依申請專利範圍第1項所述之半導體封裝構造，其中該接墊係下方具有至少一鋁層及至少一介電材料層，其中該銅層及該介電材料層之總厚度係介於1.2μm與1.5μm之間。The semiconductor package structure of claim 1, wherein the pad has at least one aluminum layer and at least one dielectric material layer, wherein the total thickness of the copper layer and the dielectric material layer is 1.2 Between μm and 1.5 μm. 依申請專利範圍第1項所述之半導體封裝構造，其中該接墊層為鋁。The semiconductor package structure of claim 1, wherein the pad layer is aluminum. 依申請專利範圍第1項所述之半導體封裝構造，其中該封膠組成成分包括氯離子、溴離子和鈉離子。The semiconductor package structure of claim 1, wherein the sealant composition comprises chloride ions, bromide ions and sodium ions. 依申請專利範圍第1項所述之半導體封裝構造，其中該封膠pH值介於4~7之間。The semiconductor package structure according to claim 1, wherein the sealant has a pH between 4 and 7. 依申請專利範圍第1項所述之半導體封裝構造，其中該承載件為基板。The semiconductor package structure of claim 1, wherein the carrier is a substrate. 依申請專利範圍第1項所述之半導體封裝構造，其中該承載件更包括：一對外電性連接點。The semiconductor package structure of claim 1, wherein the carrier further comprises: an external electrical connection point. 依申請專利範圍第1項所述之半導體封裝構造，其中該承載件為釘架。The semiconductor package structure of claim 1, wherein the carrier is a staple holder. 依申請專利範圍第18項所述之半導體封裝構造，更包括：一引腳接墊，設置於該釘架上；以及一金屬層，覆蓋該引腳接墊上，其中該引腳接墊係與該銅銲線電性連接。The semiconductor package structure according to claim 18, further comprising: a pin pad disposed on the nail frame; and a metal layer covering the pin pad, wherein the pin pad is The brazing wire is electrically connected. 依申請專利範圍第19項所述之半導體封裝構造，其中該金屬層為銀、金或鈀之一。The semiconductor package structure of claim 19, wherein the metal layer is one of silver, gold or palladium. 一種半導體封裝構造，包括：一晶片，具有一主動表面、一相對之背面，及複數個第一接墊；一承載件，具有一承載表面，及複數個第二接墊，其中該晶片之該背面係設置於該承載件之該承載表面；複數個銅銲線，電性連接相對應之該些第一接墊及該些第二接墊，該些銅銲線之每一包含一線狀部及一弧狀接合部，其中該弧狀接合部每一邊緣到該銅銲線中心線之距離大體上相等，該線狀部具有一截面直徑D1’，該弧狀接合部具有一截面直徑D2’，且1.8×D1’D2’3×D1’，該弧狀接合部之邊緣與相對應之第一接墊裸露區域之邊緣的間距≧4μm，該些第一接墊之每一具有一銲線接觸區及一非銲線接觸區，且該非銲線接觸區包含銅銲線和接墊接合後之金屬擠出殘留物；以及一封膠，包覆該晶片、該些銅銲線和覆蓋該承載件。A semiconductor package structure comprising: a wafer having an active surface, an opposite back surface, and a plurality of first pads; a carrier having a carrier surface and a plurality of second pads, wherein the wafer The back surface is disposed on the bearing surface of the carrier; the plurality of copper bonding wires are electrically connected to the corresponding first pads and the second pads, and each of the brazing wires comprises a linear portion And an arc-shaped joint, wherein each edge of the arc-shaped joint is substantially equal to a distance from a center line of the brazing wire, the wire portion has a cross-sectional diameter D1', and the arc-shaped joint has a cross-sectional diameter D2 ', and 1.8 × D1' D2' 3×D1′, the edge of the arcuate joint has a spacing of 4 μm from the edge of the corresponding exposed area of the first pad, and each of the first pads has a wire contact area and a non-wire contact And the non-bonded wire contact region comprises a brazing wire and a metal extrusion residue after the bonding of the pads; and a glue covering the wafer, the brazing wires and covering the carrier. 依申請專利範圍第21項所述之半導體封裝構造，其中該金屬擠出殘留物為鋁或銅之其中一者。 The semiconductor package structure of claim 21, wherein the metal extrusion residue is one of aluminum or copper. 依申請專利範圍第21項所述之半導體封裝構造，更包括： 一保護層，形成於該晶片之該主動表面上，並暴露出該接墊之裸露區域。 According to the semiconductor package structure described in claim 21 of the patent application, the method further includes: A protective layer is formed on the active surface of the wafer and exposes the exposed areas of the pads. 依申請專利範圍第21項所述之半導體封裝構造，其中該銅銲線含銅重量百分比為99.9%、99.99%或99.999%。 The semiconductor package structure according to claim 21, wherein the brazing wire has a copper percentage by weight of 99.9%, 99.99% or 99.999%. 依申請專利範圍第21項所述之半導體封裝構造，其中該銅銲線線狀部外圍係包覆一抗氧化金屬層。 The semiconductor package structure according to claim 21, wherein the outer portion of the wire portion of the brazing wire is coated with an anti-oxidation metal layer. 依申請專利範圍第25項所述之半導體封裝構造，其中該抗氧化金屬層為鈀。 The semiconductor package structure of claim 25, wherein the oxidation resistant metal layer is palladium. 依申請專利範圍第26項所述之半導體封裝構造，其中該銅銲線含鈀重量百分比為0.8%~2.7%。 The semiconductor package structure according to claim 26, wherein the brazing wire has a palladium weight percentage of 0.8% to 2.7%. 依申請專利範圍第26項所述之半導體封裝構造，其中該弧狀接合部成份為銅和鈀混合物。 The semiconductor package structure of claim 26, wherein the arcuate joint component is a mixture of copper and palladium. 依申請專利範圍第21項所述之半導體封裝構造，其中該接墊之厚度係介於0.8μm與2.5μm之間。 The semiconductor package structure according to claim 21, wherein the thickness of the pad is between 0.8 μm and 2.5 μm. 依申請專利範圍第21項所述之半導體封裝構造，其中該接墊係下方具有至少一銅層及至少一介電材料層，其中該銅層及該介電材料層之總厚度係介於1.2μm與1.5μm之間。 The semiconductor package structure according to claim 21, wherein the pad has at least one copper layer and at least one dielectric material layer, wherein the total thickness of the copper layer and the dielectric material layer is 1.2. Between μm and 1.5 μm. 依申請專利範圍第21項所述之半導體封裝構造，其中該接墊係下方具有至少一鋁層及至少一介電材料層，其中該銅層及該介電材料層之總厚度係介 於1.2μm與1.5μm之間。 The semiconductor package structure according to claim 21, wherein the underlayer has at least one aluminum layer and at least one dielectric material layer, wherein the total thickness of the copper layer and the dielectric material layer is Between 1.2 μm and 1.5 μm. 依申請專利範圍第21項所述之半導體封裝構造，其中該接墊層為鋁。 The semiconductor package structure of claim 21, wherein the pad layer is aluminum. 依申請專利範圍第21項所述之半導體封裝構造，其中該封膠組成成分包括氯離子和鈉離子。 The semiconductor package structure of claim 21, wherein the sealant composition comprises chloride ions and sodium ions. 依申請專利範圍第33項所述之半導體封裝構造，其中該封膠組成成分更包括：溴離子。 The semiconductor package structure of claim 33, wherein the sealant composition further comprises: bromide ions. 依申請專利範圍第21項所述之半導體封裝構造，其中該封膠pH值介於4~7之間。 The semiconductor package structure according to claim 21, wherein the sealant has a pH between 4 and 7. 如申請專利範圍第21項所述之半導體封裝構造，其中該承載件為基板。 The semiconductor package structure of claim 21, wherein the carrier is a substrate. 依申請專利範圍第21項所述之半導體封裝構造，其中該承載件為釘架。 The semiconductor package structure of claim 21, wherein the carrier is a staple holder. 依申請專利範圍第37項所述之半導體封裝構造，更包括：一引腳接墊，設置於該釘架上；及一金屬層，覆蓋該引腳接墊上，其中該引腳接墊係與該銅銲線電性連接。 The semiconductor package structure according to claim 37, further comprising: a pin pad disposed on the nail frame; and a metal layer covering the pin pad, wherein the pin pad is The brazing wire is electrically connected. 依申請專利範圍第38項所述之半導體封裝構造，其中該金屬層為銀。 The semiconductor package structure of claim 38, wherein the metal layer is silver. 一種半導體封裝方法，包含下列步驟： 提供一承載件；設置一晶片於該承載件上，其中該晶片具有一主動表面及一相對背面；設置一接墊於該晶片之該主動表面上；提供一銅銲線，具有一線狀部；通過一惰性氣體於該線狀部之一線端的周圍，並將該線狀部之該線端形成一球狀部，其中該球狀部連接於該線狀部，該球狀部每一邊緣到該銅銲線中心線之距離大體上相等，且該線狀部及該球狀部分別具有線徑D1及球徑D2，且2×D1D22.5×D1；將該銅銲線之該球狀部接合於該接墊，其中接合後該球狀部形成一弧狀接合部，該弧狀接合部每一邊緣到該銅銲線中心線之距離大體上相等，接合後之線狀部具有截面直徑D1’，該弧狀接合部具有截面直徑D2’，且1.8×D1’D2’3×D1’；以及以一封膠，包覆該晶片和該銅銲線，並覆蓋該承載件，使該封膠、該晶片及該承載件形成一封裝體。A semiconductor packaging method comprising the steps of: providing a carrier; providing a wafer on the carrier, wherein the wafer has an active surface and an opposite back surface; a pad is disposed on the active surface of the wafer; a brazing wire having a linear portion; an inert gas is disposed around a wire end of the linear portion, and the wire end of the linear portion is formed into a spherical portion, wherein the spherical portion is coupled to the linear portion The distance from each edge of the spherical portion to the center line of the brazing wire is substantially equal, and the linear portion and the spherical portion respectively have a wire diameter D1 and a ball diameter D2, and 2×D1 D2 2.5×D1; the spherical portion of the brazing wire is joined to the pad, wherein the spherical portion forms an arcuate joint after joining, and each edge of the arcuate joint reaches the center line of the brazing wire The distance is substantially equal, and the joined linear portion has a cross-sectional diameter D1' having a cross-sectional diameter D2' and 1.8 x D1' D2' 3×D1′; and coating the wafer and the brazing wire with a glue and covering the carrier to form the encapsulant, the wafer and the carrier into a package. 依申請專利範圍第40項之半導體封裝方法，其中該惰性氣體包含氮氣。 The semiconductor packaging method of claim 40, wherein the inert gas comprises nitrogen. 依申請專利範圍第40項之半導體封裝方法，其中該惰性氣體包含氮氣和氫氣之混合氣。 The semiconductor packaging method according to claim 40, wherein the inert gas comprises a mixture of nitrogen and hydrogen. 依申請專利範圍第40項之半導體封裝方法，其 中該線狀部之一線端藉由一電燒製程而形成該球狀部。 According to the semiconductor packaging method of claim 40, One of the linear ends of the linear portion is formed by an electro-burning process. 依申請專利範圍第43項之半導體封裝方法，其中該電燒製程為一放電製程。The semiconductor packaging method according to claim 43 of the patent application, wherein the electro-burning process is a discharge process.
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Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102226991B (en) * 2011-06-12 2012-11-28 徐云管 Copper palladium alloy monocrystal bonding wire and manufacturing method thereof
SG190480A1 (en) * 2011-12-01 2013-06-28 Heraeus Materials Tech Gmbh 3n copper wire with trace additions for bonding in microelectronics device
CN104511703B (en) * 2013-09-30 2017-02-15 北京中电科电子装备有限公司 Ceramic head and lead wire bonder
CN104889592B (en) * 2015-04-28 2018-01-16 太仓巨仁光伏材料有限公司 A kind of solder on the mutual latticing of solar cell module
CN107301989A (en) * 2017-06-06 2017-10-27 深圳国民飞骧科技有限公司 A kind of method for determining bonding wire chip surface pad spacing
CN112242316A (en) * 2019-07-16 2021-01-19 中芯长电半导体（江阴）有限公司 Wire bonding equipment and wire bonding method

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4733289A (en) * 1980-04-25 1988-03-22 Hitachi, Ltd. Resin-molded semiconductor device using polyimide and nitride films for the passivation film
TW200304209A (en) * 2002-03-14 2003-09-16 Fairchild Kr Semiconductor Ltd Semiconductor package having oxidation-free copper wire
TW200636966A (en) * 2005-04-08 2006-10-16 Micron Technology Inc Method and system for fabricating semiconductor components with through wire interconnects
CN101123230A (en) * 2007-09-03 2008-02-13 葵和精密电子（上海）有限公司 Internal lead structure for semiconductor part
TW200901415A (en) * 2007-06-29 2009-01-01 Siliconware Precision Industries Co Ltd Semiconductor package using copper wires and wire bonding method for the same

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6139977A (en) * 1998-06-10 2000-10-31 Lucent Technologies Inc. Palladium surface coating suitable for wirebonding and process for forming palladium surface coatings
US6358847B1 (en) * 1999-03-31 2002-03-19 Lam Research Corporation Method for enabling conventional wire bonding to copper-based bond pad features
JP2004064033A (en) * 2001-10-23 2004-02-26 Sumitomo Electric Wintec Inc Bonding wire
US6972152B2 (en) * 2003-06-27 2005-12-06 Intel Corporation Use of direct gold surface finish on a copper wire-bond substrate, methods of making same, and methods of testing same
WO2006013751A1 (en) * 2004-08-05 2006-02-09 Seiko Epson Corporation Bonding structure, wire bonding method, actuator device and liquid injecting head
CN100336191C (en) * 2005-03-04 2007-09-05 汕头华汕电子器件有限公司 Method for forming semiconductor device intraconnection by copper wire
KR101398732B1 (en) * 2006-10-06 2014-05-27 스미토모 베이클리트 컴퍼니 리미티드 Epoxy resin composition for sealing of semiconductor and semiconductor device
CN101339931A (en) * 2007-07-05 2009-01-07 矽品精密工业股份有限公司 Semiconductor packaging part with copper wire and routing method thereof

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4733289A (en) * 1980-04-25 1988-03-22 Hitachi, Ltd. Resin-molded semiconductor device using polyimide and nitride films for the passivation film
TW200304209A (en) * 2002-03-14 2003-09-16 Fairchild Kr Semiconductor Ltd Semiconductor package having oxidation-free copper wire
TW200636966A (en) * 2005-04-08 2006-10-16 Micron Technology Inc Method and system for fabricating semiconductor components with through wire interconnects
TW200901415A (en) * 2007-06-29 2009-01-01 Siliconware Precision Industries Co Ltd Semiconductor package using copper wires and wire bonding method for the same
CN101123230A (en) * 2007-09-03 2008-02-13 葵和精密电子（上海）有限公司 Internal lead structure for semiconductor part

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