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TW201030867A - Semiconductor package and method for packaging the same - Google Patents

Semiconductor package and method for packaging the same Download PDF

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Publication number
TW201030867A
TW201030867A TW098121318A TW98121318A TW201030867A TW 201030867 A TW201030867 A TW 201030867A TW 098121318 A TW098121318 A TW 098121318A TW 98121318 A TW98121318 A TW 98121318A TW 201030867 A TW201030867 A TW 201030867A
Authority
TW
Taiwan
Prior art keywords
wire
pad
semiconductor package
carrier
copper
Prior art date
Application number
TW098121318A
Other languages
Chinese (zh)
Other versions
TWI405276B (en
Inventor
Wen-Pin Huang
Cheng-Tsung Hsu
Cheng-Lan Tseng
Chih-Cheng Hung
Yu-Chi Chen
Original Assignee
Advanced Semiconductor Eng
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Semiconductor Eng filed Critical Advanced Semiconductor Eng
Priority to US12/686,979 priority Critical patent/US8357998B2/en
Publication of TW201030867A publication Critical patent/TW201030867A/en
Application granted granted Critical
Publication of TWI405276B publication Critical patent/TWI405276B/en

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

A process for bonding a bonding wire includes the following steps of: bonding a first end of the bonding wire to a first pad so as to form a first bond portion; bonding a second end of the bonding wire to a second pad, wherein an interface between the bonding wire and the second pad has a first connecting area; scrubbing the second end of the bonding wire in the direction parallel to the interface, so as to form a second bond portion, wherein new interface between the bonding wire and the second pad has a second connecting area being bigger than the first connecting area; and separating the rest of the bonding wire from the second bond portion.

Description

201030867 、 六、發明說明： ' 【發明所屬之技術領域】 有係有關於—種半導體封裝方法，更特別 就銲線之第^:二方:之料接合製程，其， 有較大接:二…言’鲜線與接势之間具 【先前技術】 ^ 拉入參考第1圖，在半導體封裝構造製財，料 . 接&方法的技術廣泛地將鋒線20應用於晶片1〇; • 絲12之㈣34(或導㈣之内_間 -接。打線接合製程是以金線為主，但銅線 /、有低成本的優勢。相較於金，銅具有較佳的導電 性及導熱性’可使銅銲線之線徑較細及散熱效率較 佳。 ❹ 參考第2至4圖，其顯示習知銅銲線接合方法。 多考第2目’ 一打線機！ 6提供一銅銲線，其包 含一銅線22。然後，將該銅銲線2〇之第一線端 電燒形成一銅球24,而連接於該銅線22。參考第3 圖，遠打線機16之銲針（capiiiary)18將該銅球24, 施壓而變形成一弧狀接合部24。參考第4圖，藉由 —振動製程，將該弧狀接合部24接合於一晶片接墊 32，以形成一第一銲點（first b〇nd)部分。參考第$ 圖’將該銲針18上升至一預定高度。參考第6圖， 201030867 該鲜針！8將該銅銲線 的長卢由w 成形。所需之銅銲線 彻it 6自動送出。參考第7圖， 二:該銅銲線2〇之第二線端25施屡，並 合於—基板接墊34，以^ 線端25接 —部分26。來 h弟-銲點(咖_1 他部分胸第I::該銅銲線2〇之其 習知銅鲜線接合社構。…。刀離，如此以形成 之第1,山Μ : 考圖，在該銅銲線20 罘一線知25的接合及分離| 2〇與基板接墊34之間且有^ ”銅辉線 二銲點部分26之接入面積，亦即該第 2〇之望的一之錢曰面積。該銲針Μ將該銅銲線 弟—、，泉端25形成有一銲線魚尾區28，該在田 28緊鄰於該銅1导線2G與基板接塾 間的接合面，亦即 签__ 魚尾區28，W^C°h 26包含該銲線 何凸起fh.m Γ 之剖面並未包含任 工（（h 111 )，亦即該銲線魚尾區2 8之剖面包含 平滑弧線。 』匕3 — d執就習知銅銲線接合方法而言，該銅銲線 二基板接墊之間的接合面積竭常不夠大 麵銲線與基板接塾之間的接合力及強度不夠大以 I能會造成該銅銲線脫落。若是該銅銲線脫落， 包路會形成開路（〇penloop)，將使得晶片功能失效、。 口此，便有需要提供一種半導體封裝方法之鋥 201030867 γ:合製程，能夠解決前述的問題。 【务明内容j 本發明提供一種丰導辦 驟：設置-曰片於W 方法，包含下列步 第一表面與相對之一第二表面，_ 片具有— 墊，該第一接墊位於兮第χ日9匕3一弟—接 饮：促y 5亥罘—表面，且 —第三表面與相對之一第 。祆載件具有 二接墊，爷第一接執 H亥承载件包含-第 銅銲線，其包含第一線 楚 ，美仏至>、一 之览地 弟&及弟二線端，·將該銅_ 之弟—線端接合於該第—接墊， _ ]干、泉 卹八.⑽ 以形成一第一銲點 邛分，將該銅銲線之第-蟪#拉人 杆”占 i击斗Α 弟一線立而接合於該第二接墊， 接:_銲線與第二接墊之間的接合面具有 銲岭w & 接&面之方向將接合後之該 ❹ 中：如：端擠壓’以形成一第二銲點部分，其 …δ銲線與第二接墊之間的新接合面 — =積，其大於該第一接合面積；將該銅銲 八他部分與第二銲點部分分離，此Bi # 八 1刀刀離，此日守该弟二銲點部 ^二薛線魚尾區和一鲜線切斷區，該銲線魚 毛°Π匕3至少—擠壓凸^ ;以及以-封膠，包覆續 晶片和該銅銲線，並覆蓋該承載件，使該封膠、該晶 片及該承載件形成一封裝體。 、根據本發明之第二銲點（second bond)部分，由 於接合後之該銅銲線之第二線端被擠壓，因此該 201030867 銅知線之第二銲點部分之 含至少—擠壓凸 :、干、、泉…、尾區的剖面包 間具有較大接合面積，二銅：線與第二接墊之 接墊之間的接合力及強度。…銅鮮線與第二 為了讓本發明之上述和其他目 點能更明晶員，下玄脾阶人ή 、知'徵、和優 下。下文將配合所附圖示’作詳細說明如 【實施方式】 i考第1 〇至16圖，其顯示本發明之—每 之半導體封裝方法。參考第1〇圖 〇 於一承載件⑴上，其中該晶片11〇具有_：主片動^ :115與相對之—背自116，該晶片m包含—第 接墊132(諸如鋁接墊或銅接墊），該第—接墊 132位於該主動表面115，該承載件ιΐ2具有—上表 面113與相對之一下表面114，該承載件ιΐ2包含一x 第二接墊m(諸如紹接墊或銅接墊），該第二接墊 132位於該上表面113，且該晶片11〇的背面us 位於該承載件之上表面113。該晶片11〇包含—保 5蒦層I36，其形成於該晶片no之主動表面ι15， 亚恭露出該第一接墊i 32，而使該第一接墊丨32 具有一裸露面積。參考第n圖，在本實施例中， 一打線機102提供至少一銲線12〇。該銲線12〇可 為銅鮮線’該銅銲線之含銅重量百分比可為 201030867 99.9%(3N)、99.99%(4N)或 99.999%(5N)。然後，201030867, VI, invention description: 'The technical field of the invention belongs to the semiconductor packaging method, more specifically the welding wire of the ^: two: material bonding process, which has a larger connection: two ... 言 ' between the fresh line and the potential [previous technology] ^ pull in the reference to Figure 1, in the semiconductor package structure to make money, material. The technology of the method is widely applied to the wafer 1 〇; The wire (4) 34 (or the inner (four) of the wire 12). The wire bonding process is mainly gold wire, but the copper wire / has the advantage of low cost. Compared with gold, copper has better conductivity and heat conduction. The 'skill' can make the wire diameter of the brazing wire finer and the heat dissipation efficiency is better. ❹ Refer to Figures 2 to 4, which show the conventional copper wire bonding method. Multi-test 2nd item 'One wire machine! 6 Provide a copper a bonding wire comprising a copper wire 22. Then, the first wire end of the copper bonding wire 2 is electrically fired to form a copper ball 24 and is connected to the copper wire 22. Referring to Figure 3, the remote wire bonding machine 16 A capijary 18 presses the copper ball 24 to form an arcuate joint portion 24. Referring to Fig. 4, by the vibration process The arcuate joint portion 24 is bonded to a die pad 32 to form a first solder joint portion. The solder pin 18 is raised to a predetermined height with reference to FIG. , 201030867 The fresh needle! 8 The long wire of the brazing wire is formed by w. The required brazing wire is automatically sent out by it 6. Refer to Fig. 7, two: the second wire end of the brazing wire 2 Repeatedly, the same is applied to the substrate pad 34, and the wire terminal 25 is connected to the portion 26. The h-the solder joint (Cai_1 part of the chest I:: the copper wire 2 is the conventional copper The fresh wire joins the structure....the knife is separated, so as to form the first, the mountain: the test, in the bonding and separation of the copper wire 20, the wire 25 and the substrate pad 34 ^ "The access area of the second solder joint portion 26 of the Tonghui line, that is, the area of the second 〇 〇 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 In the fish tail region 28, the field 28 is adjacent to the joint surface between the copper 1 wire 2G and the substrate joint, that is, the sign __ fishtail region 28, and W^C°h 26 includes the wire bond protrusion fh.m Γ The profile does not contain work ((h 111 ), That is, the cross section of the wire tail region of the wire has a smooth arc. 』匕3 — d In terms of the conventional copper wire bonding method, the joint area between the two substrate pads of the brazing wire is often insufficient for large surface welding. The bonding force and strength between the wire and the substrate are not large enough to cause the brazing wire to fall off. If the brazing wire falls off, the bypass will form an open circuit, which will invalidate the function of the wafer. Therefore, there is a need to provide a semiconductor packaging method 鋥 201030867 γ: a manufacturing process that can solve the aforementioned problems. [Care for the content of the present invention] The present invention provides a method for setting up a slab to the W method, comprising the following steps: a first surface and a second surface opposite to each other, the _ sheet having a pad, the first pad being located at the first The next day, 9匕3, a younger brother, pick up the drink: promote y 5 罘 罘 - surface, and - the third surface and the opposite one. The 祆 carrier has two pads, and the first keeper of the H-Hui carrier includes a - brazed wire, which includes the first line Chu, the beautiful 仏 to the >, the one to see the brother & and the second line, · Bonding the copper wire to the first pad, _ _ dry, spring shirt eight (10) to form a first solder joint, the second wire of the brazing wire "The i-striker is joined to the second pad in a line, and the joint surface between the wire and the second pad has a weld ridge w & ❹ medium: such as: end extrusion 'to form a second solder joint portion, ... the new joint between the δ bond wire and the second pad - = product, which is greater than the first joint area; the brazing The part of the eight parts is separated from the second part of the solder joint. The Bi # 八一刀刀 is off, this day guards the second solder joint of the brother, the second Xue line fish tail area and a fresh line cut area, the welding line fish hair °Π匕3 at least - squeezing the embossing; and sealing the wafer and the brazing wire with a sealant, and covering the carrier, so that the sealant, the wafer and the carrier form a package. Second welding of invention (second bond) portion, since the second wire end of the brazing wire after the bonding is extruded, the second solder joint portion of the 201030867 copper wire contains at least - extruded convex, dry, spring... The cross-section of the tail zone has a large joint area, the joint force and strength between the two copper: wire and the pad of the second pad. The copper fresh wire and the second are to enable the above and other objects of the present invention. More clearly, the spleen and the spleen, the spleen and the spleen, the singularity, and the superiority. The following will be described in conjunction with the attached drawing'. [Embodiment] i test 1st to 16th, which shows the present invention - each semiconductor packaging method. Referring to Figure 1 on a carrier (1), wherein the wafer 11 has _: main film movement: 115 and opposite - back from 116, the wafer m contains - the first pad 132 (such as an aluminum pad or a copper pad), the first pad 132 is located on the active surface 115, the carrier ι 2 has an upper surface 113 and an opposite lower surface 114, the carrier ι 2 includes an x second connection a pad m (such as a pad or a copper pad), the second pad 132 is located on the upper surface 113, and the wafer 11 The back surface of the crucible is located on the upper surface 113 of the carrier. The wafer 11A includes a protective layer I36 formed on the active surface ι15 of the wafer no, and the first pad i 32 is exposed. The first pad 32 has a bare area. Referring to the nth figure, in the embodiment, a wire bonding machine 102 provides at least one bonding wire 12〇. The bonding wire 12〇 can be a copper wire “the copper wire” The weight percentage of copper may be 2010.30867, 99.9% (3N), 99.99% (4N) or 99.999% (5N). Then,

將該銲線120之第一線端123接合於一第一接墊 132 ’以形成一第一銲點（first bond)部分121。詳 =而言，該銲線120與第一接墊132之間的接合 =程包含下列步驟：將該銲線12〇之第一線端123 包I形成一球狀部而連接於一線狀部丨。然後， 该2線機116之銲針（capillary)U8將該球狀部施壓 ，變形成-弧狀接合部124。然後，藉由一振動製 程（諸如超音波振動製程），將該弧狀接合部124合 於該第一接墊132,以形成該第一銲點部分12ι: 在實施例中，該銲線120之線狀部122外圍可 包覆一抗氧化金屬層。該抗氧化金屬層可 :;:二2。可置換為銅桃線。該銅峨 3纪重置百分比為〇.8〇/〇〜2.7〇/。。 多考第12圖，將該銲線12〇之 接合於該第二接墊134，如第13 7泉:而125 古，兮力日仏 口 W不。洋細而 120與第二接墊134之間的接合製程 匕各下列步驟：將該銲針118上升至— 然後’該鮮針118將_線12G =二 10Π λα , 少取狐形。所需之 、，泉120的長度由該打線機自動送出。 針118將該銲線12〇之第 Μ、 盐丄 忒而125施壓。然德， 曰’一振動製程，將該銲線120之第二線浐 合於該第二接墊134。參考第 、而 接 之第^弟13圖’在該銲線120 泉而125的接合製程之後，該銲、線120與第 201030867 二接墊134之間的接合面具有—第一接合面積 。該銲針U8將該銲線120之第二線端125形 成有如線魚尾區128，該銲線魚尾區〗28緊鄰於 ，線m與第二接墊134之間的接合面：且該 知線魚尾區128之剖面並未包含任何凸起（卜⑴）， 亦即該銲線魚尾區128之剖面包含—平滑弧線。 再者，該銲針118在該第二接墊134冑義有一鮮線 切斷區12 7。 % 參考第Η圖，將該第二接墊134之表面定義 =法向量Ν，並利用該銲針⑽沿垂直於該法向 …4〇,或者將該輝針118沿平行於該銲 線2〇與弟二接墊134之間的接合面之方向140, 將接合後之該銲線12G之第二㈣125擠壓 二响’以形成一第二銲點（似⑽^ b〇nd)部分 〇 參考第15圖，其顯示該鮮線12 m的擠壓製程具有三種擠壓方向。在The first wire end 123 of the bonding wire 120 is bonded to a first pad 132' to form a first bond portion 121. In detail, the bonding between the bonding wire 120 and the first pad 132 includes the following steps: the first wire end 123 of the bonding wire 12 is formed into a spherical portion and connected to a linear portion. Hey. Then, a capillary U8 of the 2-wire machine 116 presses the spherical portion to form an arc-shaped joint portion 124. Then, the arc-shaped joint portion 124 is joined to the first pad 132 by a vibration process (such as an ultrasonic vibration process) to form the first pad portion 12: In the embodiment, the wire 120 The outer portion of the linear portion 122 may be coated with an anti-oxidation metal layer. The anti-oxidation metal layer can be:;: two. Can be replaced by a copper peach line. The percentage of the copper urn 3 reset is 〇.8〇/〇~2.7〇/. . In the multi-test 12th figure, the bonding wire 12 is joined to the second pad 134, such as the 13th spring: and 125 ancient, the force is not the mouth. The bonding process between the capillary 120 and the second pad 134 is the following steps: the soldering needle 118 is raised to - then the fresh needle 118 will have a _ line 12G = two 10 Π λα and a little fox shape. If necessary, the length of the spring 120 is automatically sent by the wire machine. The needle 118 presses the first wire and the salt of the wire 12 to 125. And a 'vibration process, the second line of the bonding wire 120 is coupled to the second pad 134. Referring to the second and subsequent drawings, after the bonding process of the bonding wire 120 and 125, the bonding surface between the bonding wire 120 and the 201030867 second pad 134 has a first bonding area. The soldering pin U8 forms a second wire end 125 of the bonding wire 120, such as a wire fishtail region 128, which is adjacent to the joint surface between the wire m and the second pad 134: and the wire The section of the fishtail section 128 does not contain any protrusions (Bu(1)), that is, the section of the wire tail region 128 contains a smooth arc. Moreover, the soldering pin 118 has a fresh line cutting area 12 7 in the second pad 134. % Referring to the second drawing, the surface of the second pad 134 is defined as a normal vector Ν, and the soldering pin (10) is used to be perpendicular to the normal direction... 4 turns, or the glow pin 118 is parallel to the bonding wire 2 In the direction 140 of the joint between the second and second pads 134, the second (four) 125 of the bonded wire 12G is pressed twice to form a second solder joint (like (10)^b〇nd). Referring to Fig. 15, it is shown that the extrusion process of the fresh wire 12 m has three extrusion directions. in

中，5亥銲線120之第二線端125的擠壓製程J 下列步驟：定義一樁麽古a ' 匕含 价銲二"I 該擠壓方向為通過 "弟一!爾” 126之該法向4 ⑽以及沿該擠壓方向將 ：，方向 第二線端125擠壓。 、干線120之 在一替代實施例中’該銲線12〇之第二線端 201030867 125的擠壓製程包含下列步驟：定義為一擠壓方 向，遠擠壓方向為一直線方向144，該直線方向 144通過5亥第二銲點部分i%上方，且讓直線方向 144垂直於該第一銲點部分l2i及第二銲點部分 126所形成之直線投影於該承載件112之上表面 113的直線；以及沿該擠壓方向將接合後之該銲線 120之第二線端125擠壓。In the extrusion process of the second line end 125 of the 5th welding line 120, the following steps are performed: define a piece of ancient a ' 匕 price welding 2 "I the direction of extrusion is through "弟一!尔" 126 The normal direction 4 (10) and along the extrusion direction:, the direction of the second line end 125 is pressed. The trunk line 120 is in an alternative embodiment, the extrusion of the second line end 201030867 125 of the wire 12 The process comprises the steps of: defining a direction of extrusion, the direction of the far extrusion is a straight line direction 144, the direction of the line 144 passing over the second solder joint portion i%, and letting the linear direction 144 be perpendicular to the first solder joint portion A line formed by the l2i and the second pad portion 126 is projected on a straight line of the upper surface 113 of the carrier member 112; and the second wire end 125 of the bonding wire 120 is pressed in the pressing direction.

在另一替代實施例中’該銲線12〇之第二線端 125的擠壓製輕包含下列步驟：定義為一擠壓方 向’该擠壓方向為一直線方肖146，該直線方向 146通過该第二銲點部分126上方，且該直線方向 146平行於該第一銲點部分121及第二鲜點部分 126所形成之直線投影於該承載件112之上表面 113的直線；以及沿該擠壓方向將接合後之該銲線 120之第二線端125擠壓。 參~考第16圖，將該銲線12〇之其他部分 自该弟二銲點部分126之銲線切斷區127分離 士此以形成本發明之銲線接合結構，並完成本發 =接合製程。參考第17a及m圖，在該銅 \ 之第二線端125的接合、擠壓及分離製程 =::、線m與第二㈣134之間的新接合， 八 第一接合面積A2(亦即該第二銲點部分u 接口面積），其大於該第一接合面積A丨。請〉、 201030867 I::8::銲線12°之第二線端㈣成 二接塾;::V28，’緊咖^ 分⑶包含該新 J，即该弟二銲點部 ⑵。該新銲線48及該銲線切斷區 凸起區128,之剖面包含至少-擠壓 區128,之:J:、、'二移所造成’亦即該新銲線魚尾 12 9胸新广么包含一平滑弧線。該擠壓凸起 匕、"亥新鲜線魚尾區128，— 亦即該擠壓凸起129爷_ ^玄'而衣以， 成，而非藉由至少兩次=程^ 凸起129形狀可為階梯狀而形成。該擠壓 中，當該銲線U0皮置^1在另—實施例 凸起⑶二 為銅把銲線時’繼 之29成伤為銅和飽混合物。 ^據本發明之第二鮮點（⑽咖5〇叫部分，由 喰之；後線之第二線端被擠壓，因此該鮮 f弟：1…分之新銲線魚尾區的剖面包含至 > -滅凸起⑽!），亦即該料與第二接塾之 具有較大接合面積（因為擠壓後之接合面積^ ^ 於擠壓前之接合面積A1)’進而增加該銲線 接墊之間的接合力及強度。 … — 參考第18目，在本實施射，該承载件112 為基板U2a。該銲線120之一線端電性連接於嗦曰 片1H)之接墊！32(亦即第—接墊），該銲線12〇 ^曰 201030867 -線端電性連接於該基板U2a之接墊134(亦即第二 - 接墊）。該第一接墊及第二接墊可為複數個。該晶片 m之接墊132電性連接於該晶片之線路（圖未示）。 該基板112a包含一對外電性連接點156，其位於 該下表面114。 ' 再參考第18圖，最後以一封膠138，包覆該晶 片110和該銲線120,並覆蓋該承載件112，使該封 • 膠138、該晶片no及該承載件112形成一球袼陣列 封裝體（BGApackage)，亦即本發明之半導體 ‘ 造1〇0。該封膠丨38組成成分包含氯離子和鈉離 , 子，如此可使該銅銲線12〇不易被氧化。該封膠138 之組成成分更包含溴離子。該封膠138之pH值可 介於4〜7之間。 . 參考第19圖，在另一實施例中，本發明之銲線 籲 接合結構可應用於凹槽向下（cavity down)型的封裴 構造，諸如w型球袼陣列封裴構造（wbga package)’亦即本發明之另一半導體封裝構造1〇〇，。 該半導體封裝構造100’大體上類似於該半導體封裝 構造100 ’其兩者主要差異係在於該晶片丨丨〇，的主 動表面115係設置於該承載件112(諸如基板112a,) 之上表面113上。該基板112b包括貫穿開口 117， 其由該上表面Π 3延伸至該下表面Η *。該銅銲線 120通過該貫穿開口 117,該铜銲線12〇之一線端電 11 201030867 性連接於該晶片11G，之接墊132(亦即第—接墊），該 銲線m之另-線端電性連接於該基板u2a,之接塾 134’（亦即第二接墊）’該接整134，配置於該下表面 114，。該第一接墊及第二接墊可為複數個。該晶片 no之接墊132電性連接於該晶片之線路(圖未 示)。該基板U2a’包括一對外電性連接點156，豆 位於該下表面114。 /、 參考第20圖’在又—實施例中，本發明之鲜線 口結構可應用於具有㈣的封裝構造，亦即本 IS:半導體封裝構造1〇0'該半導體封編 大體上類似於該半導體封裝構造i⑽，並 主要差異係在於該承載件112為釘举 112b(leadf_e)。該半導體封裝構造11G，另包含 :引:接墊134，，及一金屬層154，其中該引腳接 取代該第二接墊134。該引腳接墊134,, 故置於该釘架112b上。該金屬層154係覆蓋 腳接墊U4，，上，該金屬層154可為銀、金或鈀之 一。該引腳接墊134，，係與該銲線12〇電性連接。 明已以前述實施例揭示，然其並非用 =本發明’任何本發明所屬技術領域 :知識者，在不脫離本發明之精神和_内，當可 與修改。因此本發明之保護範圍；視 後附之申㉔專利範圍所界定者為準。 12 201030867 【圖式簡單說明】 第1圖為先前技術之銲線接合方法之剖面示意 圖。 第2至8圖為先前技術之銅銲線接合方法之剖 面示意圖。 第9圖為先前技術之銅銲線接合方法之剖面示 思圖，其顯不在接合製程之後，銅銲線之第二線端 形成有一薛線魚尾區。 第1 〇圖為本發明之一實施例之半導體封裝方 法之剖面示意圖，其顯示承载件及晶片。 第11圖為本發明之一實施例之半導體封裝方 j剖面示意圖，其顯示銲線與第—接墊 合製程。 文 法之:為本發明之一實施例之半導體封裝方 合^圖，其顯示銲線與第二接墊之間的接 第13圖為本發明 _ 法之剖面示意圖，Μ ::::之半導體封裝方 第二線❹2在接合製程之後，銲線之 /而形成有一銲線魚尾區。 弟14圖為本發明 法之剖面示专圖， —只知例之半導體封裝方 程。 '員不銲線之第二線端的擠壓製 第15圖為本發明夕—餘 法之立體示意圖，㈣ 例之半導體封裝方 . z、1、，員不擠壓製程具有三種擠壓方 13 201030867 向。 第】6圖為本發明之—實施合 法之立體示意圖，其顯示將二封裝方 二銲點部分分離。 ι線之其他部分與第 封壯!^们7'圖為本發明之—實施例之半導體 封衣方法之剖面及立體示意圖，苴 ，體 _製程之後，鮮線之第二線二， 線魚尾區。 战有新銲 第18圖為本發明之一實施例之 法之剖面示意圖。 干泠體封叙方 、弟19圖為本發明之另-實施例之半導 方法之剖面示意圖。 、、第20圖為本發明之又一實施例之半導： 方法之剖面示意圖。 ' ; 【主要元件符號說明】 10 晶片 打線機 銲線 銅線 銅球 線端 銲線魚尾區 接墊 半導體封裝構造 100”半導體封裝構造 晶片 封裝 封裝 16 20 22 24 25 28 32 100 12 18 205 23 24, 26 29 34100, 102 110’ 基板 銲針 其他部分 線端 弧狀接合部 鮮點部分 凸起 接墊 半導體封裴構造 打線機 晶片 14 201030867 112 承載件 112a 112a’基板 112b 113 上表面 114 115 主動表面 116 117 貫穿開口 118 120 銲線 120, 121 銲點部分 122 123 線端 124 125 線端 126 127 銲線切斷區 128 銲線魚尾區 128, 129 凸起 129, 132 接墊 134 134, 接墊 134，， 136 保護層 138 140 方向 142 144 直線方向 146 154 金屬層 156 A1 接合面積 A2 基板 釘架 下表面 背面 鲜針 其他部分 線狀部 弧狀接合部 銲點部分 新銲線魚尾區 凸起 接墊 接墊 封膠 旋轉方向 直線方向 電性連接點 接合面積 φ Ν 法向量 15In another alternative embodiment, the extrusion of the second wire end 125 of the wire 12 includes the following steps: defined as a direction of extrusion 'the direction of extrusion is a straight line 146, the direction of the line 146 is passed The second solder joint portion 126 is above, and the linear direction 146 is parallel to a line formed by the line formed by the first solder joint portion 121 and the second fresh spot portion 126 on the upper surface 113 of the carrier member 112; The direction of extrusion presses the second wire end 125 of the wire 120 after bonding. Referring to Figure 16, the other portion of the bonding wire 12 is separated from the wire cutting region 127 of the second solder joint portion 126 to form the wire bonding structure of the present invention, and the present invention is completed. Process. Referring to Figures 17a and m, the joining, squeezing and separating process at the second wire end 125 of the copper is::, the new joint between the line m and the second (four) 134, and the first joint area A2 (i.e., The second pad portion u interface area is greater than the first junction area A丨. Please, 201030867 I::8:: The second line end of the welding line 12° (four) is connected to the second line;::V28, 'tight coffee ^ points (3) contains the new J, that is, the second solder joint (2). The new bonding wire 48 and the wire bonding region raised portion 128 have a cross section including at least a pressing region 128, which is: J:, and 'two shifts caused', that is, the new wire tail fish tail 12 9 chest new Wide includes a smooth arc. The squeezing protrusion 匕, "Hai fresh line fishtail area 128, - that is, the squeezing protrusion 129 _ _ 玄 ” ” ” ” ” ” ” ” ” It can be formed in a stepped shape. In the extrusion, when the bonding wire U0 is placed in the other embodiment, the projection (3) is a copper bonding wire, and then 29 is wounded into a copper and a saturated mixture. According to the second fresh point of the present invention ((10) coffee 5 〇 part, by 喰; the second line end of the rear line is squeezed, so the fresh f: 1... the new weld line fishtail section profile contains To > - bulge (10)!), that is, the material has a larger joint area with the second joint (because the joint area after extrusion ^ ^ is the joint area A1 before extrusion) and thereby increase the weld The bonding force and strength between the wire pads. ... - Referring to item 18, in the present embodiment, the carrier 112 is a substrate U2a. One of the wire ends of the bonding wire 120 is electrically connected to the pad of the die 1H)! 32 (ie, the first pad), the bonding wire 12〇 ^曰 201030867 - the wire end is electrically connected to the pad 134 of the substrate U2a (that is, the second pad). The first pad and the second pad may be plural. The pad 132 of the chip m is electrically connected to the circuit of the chip (not shown). The substrate 112a includes an external electrical connection point 156 that is located on the lower surface 114. Referring again to Figure 18, the wafer 110 and the bonding wire 120 are coated with a glue 138, and the carrier 112 is covered, so that the sealing glue 138, the wafer no and the carrier 112 form a ball.袼 Array package (BGA package), that is, the semiconductor of the present invention. The composition of the sealant 38 contains chloride ions and sodium ions, so that the copper wire 12 can be easily oxidized. The composition of the sealant 138 further contains bromide ions. The sealant 138 may have a pH between 4 and 7. Referring to Fig. 19, in another embodiment, the wire bonding structure of the present invention can be applied to a cavity down type sealing structure such as a w-ball array sealing structure (wbga package) That is, another semiconductor package structure of the present invention. The semiconductor package construction 100' is substantially similar to the semiconductor package construction 100'. The main difference between the two is that the active surface 115 of the wafer is disposed on the surface 113 of the carrier 112 (such as the substrate 112a). on. The substrate 112b includes a through opening 117 that extends from the upper surface Π 3 to the lower surface Η*. The brazing wire 120 passes through the through opening 117, and the wire end of the brazing wire 12 is electrically connected to the wafer 11G, and the pad 132 (ie, the first pad), the wire m is further- The wire end is electrically connected to the substrate u2a, and the connection 134' (ie, the second pad) is disposed on the lower surface 114. The first pad and the second pad may be plural. The pad 132 of the wafer no is electrically connected to the wiring of the chip (not shown). The substrate U2a' includes an external electrical connection point 156 on which the beans are located. Referring to FIG. 20, in still another embodiment, the fresh wire port structure of the present invention can be applied to a package structure having (4), that is, the present IS: semiconductor package structure 1 〇 0'. The semiconductor package is substantially similar The semiconductor package construction i (10), and the main difference is that the carrier 112 is a pin 112b (leadf_e). The semiconductor package structure 11G further includes: a pad 134, and a metal layer 154, wherein the pin is substituted for the second pad 134. The pin pad 134 is placed on the stud 112b. The metal layer 154 covers the foot pad U4. The metal layer 154 may be one of silver, gold or palladium. The pin pad 134 is electrically connected to the bonding wire 12 . The present invention has been disclosed in the foregoing embodiments, and it is not intended to be in the nature of the invention, and the invention may be modified without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention is subject to the definition of the scope of the patent application. 12 201030867 [Simple description of the drawings] Fig. 1 is a schematic cross-sectional view showing a prior art wire bonding method. 2 to 8 are schematic cross-sectional views showing a prior art brazing wire bonding method. Fig. 9 is a cross-sectional view showing a prior art brazing wire bonding method in which a second line end of the brazing wire is formed with a squid line fish tail region after the joining process. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view showing a semiconductor package method according to an embodiment of the present invention, showing a carrier and a wafer. Figure 11 is a cross-sectional view showing a semiconductor package j according to an embodiment of the present invention, showing a bonding process of a bonding wire and a first bonding pad. The grammar method is a semiconductor package assembly diagram according to an embodiment of the present invention, which shows the connection between the bonding wire and the second pad. FIG. 13 is a schematic cross-sectional view of the method of the present invention, Μ :::: semiconductor The second wire ❹2 of the package side is formed with a wire tailing region after the bonding process. Figure 14 is a cross-sectional view of the method of the present invention, which is a semiconductor package of only a known example. The extrusion diagram of the second line end of the member non-welding line is a three-dimensional diagram of the eve method of the invention, (4) the semiconductor package of the example. z, 1, the non-extrusion process has three extrusion sides 13 201030867 to. Fig. 6 is a perspective view showing the implementation of the present invention, which shows the separation of the two solder joint portions. The other parts of the ι line and the first block of the sturdy! ^7's figure is a cross-section and a three-dimensional view of the semiconductor sealing method of the present invention - 苴, body _ process, the second line of the fresh line two, the line fishtail Area. There is a new welding in the war. Fig. 18 is a schematic cross-sectional view showing an embodiment of the present invention. A diagram of a semi-conductive method of another embodiment of the present invention is shown in the figure of the dry body. 20 is a semi-conductive view of another embodiment of the present invention: a schematic cross-sectional view of the method. ' ; [Main component symbol description] 10 wafer wire bonding machine copper wire copper ball wire end wire wire fishtail pad semiconductor package structure 100" semiconductor package structure chip package 16 20 22 24 25 28 32 100 12 18 205 23 24 , 26 29 34100, 102 110' Substrate soldering needle Other parts Wire end Arc joints Fresh spot part Raised pads Semiconductor package structure Wire machine wafer 14 201030867 112 Carrier 112a 112a' Substrate 112b 113 Upper surface 114 115 Active surface 116 117 through opening 118 120 welding wire 120, 121 solder joint portion 122 123 wire end 124 125 wire end 126 127 wire cut-off area 128 wire tail fishtail area 128, 129 protrusion 129, 132 pad 134 134, pad 134 , 136 Protective layer 138 140 Direction 142 144 Linear direction 146 154 Metal layer 156 A1 Joint area A2 Substrate nail holder Lower surface Back side Fresh needle Other parts Linear part Arc joints Solder joint part New weld line Fishtail area Raised joint Pad sealing rubber rotation direction linear direction electrical connection point joint area φ Ν normal vector 15

Claims (1)

201030867 七、申請專利範圍： 1 · 一種半導體封裝構造，包含： -晶片，具有-第-表面與相對之一第二表面，該 晶片包含一第一接墊，兮笛 * 忒弟一接墊位於該第一表 面； 二 叫穴相對之一第四表曲， 该承載件包含一第二接墊，兮 / 女至°亥弟二接墊位於該第二 表面，其中該晶片係設置於該承載件上； 至少-銅銲線1以電性連接於該晶片與該承載 件’該銅銲線包含： -第-線端’接合於該第—接墊，以形成一第 一銲點部分；以及 二第二線端’接合於該第二接墊，以形成一第 —錦點部分，JL中马·笛_》日 ”宁°亥弟—銲點部分包含一銲線 ❹ …、尾區和—銲線切斷區，該銲線魚尾區包含至 少-擠壓凸起，該擠壓凸起係與該銲線魚尾區 一體成型而製造；以及 —封膠，包覆该晶片及該銅銲線，並覆蓋該承 载件。 人 .依申請專利範圍第1項所述之半導體封裝構造， 其中該銅銲線含銅重量百分比為99.9%、99.99%或 99·999°/0之其中一者。 16 201030867 3 ·依申明專利範圍帛1項所述之半導體封裝構造， 其中該銅銲線具有一線狀部，其外圍係包覆一抗 氧化金屬層。 4.依申明專利範圍第3項所述之半導體封裝構造， 其中s亥抗氧化金屬層為I巴。 依申請專利範_ 4項所述之半導體封裝構造 其中該銅銲線含鈀重量百分比為0.8¾〜2.7%。 6·依申請專利範圍帛4項所述之半導體封裝構造， 其中該擠壓凸起成份包含銅和鈀。 7. 依申切專利範圍第i項所述之半導體封裝構造 其申該擠壓凸起為一銲針位移所造成。 8. :申請專利範圍帛！項所述之半導體封装構造 八中該擠壓凸起形狀為階梯狀。 °201030867 VII. Patent application scope: 1 . A semiconductor package structure comprising: - a wafer having a - first surface and a second surface opposite to each other, the wafer comprising a first pad, the 兮 * 忒 一 一 接 pad is located The first surface; the second surface is opposite to the fourth surface, the carrier includes a second pad, and the 兮/女至°海二二 pads are located on the second surface, wherein the wafer is disposed on the carrier At least - the brazing wire 1 is electrically connected to the wafer and the carrier 'the brazing wire comprises: - a - wire end 'bonded to the first pad to form a first pad portion; And the second second end of the second wire is joined to the second pad to form a first-spot portion, and the JL is in the middle of the horse, and the solder joint portion includes a wire bonding wire. And a wire cut-off area, the wire tail region comprising at least an extrusion protrusion, the extrusion protrusion being integrally formed with the wire tail region; and a sealant covering the wafer and the copper Welding wire and covering the carrier. People. According to the scope of claim 1 a semiconductor package structure, wherein the copper wire has a copper percentage by weight of 99.9%, 99.99%, or 99.999°/0. 16 201030867 3 · The semiconductor package structure of claim 1 The copper wire has a linear portion, and the periphery thereof is coated with an anti-oxidation metal layer. 4. The semiconductor package structure according to claim 3, wherein the anti-oxidation metal layer is I bar. The semiconductor package structure of the invention, wherein the copper wire has a palladium weight percentage of 0.83⁄4 to 2.7%. 6. The semiconductor package structure according to claim 4, wherein the extrusion protrusion component comprises Copper and palladium 7. The semiconductor package structure according to item ith of the patent application scope is claimed to be caused by a solder pin displacement. 8. : The semiconductor package structure described in the patent application scope In the eighth, the shape of the extrusion bulge is stepped. 半導體_造 1〇 士依：請專利範圍第1項之半導體封裝構、-， 中S亥第一接墊為鋁接墊或銅接墊之其中—者乂，其 ”申請專利範圍第,項所述之;:體:裝構 &，其中該承载件為基板。 13.依申請專利範圍第 項所述之半 導體封裝構 201030867 造’另包含： 一金屬層’覆蓋該第二接墊上。 14.造依範圍'13項所述之半導體封裝構 其中邊金屬層包含鎳、金或鈀之合金。 15造依圍第1項所述之半導體封裂構 引腳接Γ承載件為釘架，其中該第二接塾為- 16. 依申請專利銘R ^ ^ 圍弟15項所述之半導體封裝構 以，该釘架另包含： 再 金屬層，覆蓋該引腳接墊上。 I造依If::範圍^ 16項所述之半導體封裝構 ，、中以金屬層包含銀、金或鈀之一。 迕依1:專利範圍第1項所述之半導體封裝構 &其中該封膠經成成分包含氯離子 鈉離子。 成蠘子和 Ϊ9.依申請專利範圍第18項所述之 造’其中該封膠PH值介於4〜7之間。f衣構 2〇.—财導體封裝方法，包含τ列步驟： 5又置—晶片於—承載件上，其中該晶片具有—第— 表面與相對之—第二表面，該晶片包含—第 墊二該第—接墊位於該第一表面，且該承载件具有 乐二表面與相對之一第四表面，該承載件包含一第 18 201030867 二接墊，該第二接墊位於該第三表面； ' 提供至少一銅銲線，其包含第一線端及第二線 端； 將該銅銲線之第一線端接合於該第一接墊，以 形成一第一銲點部分； 將該銅銲線之第二線端接合於該第二接墊，此 時該銅銲線與第二接墊之間的接合面具有一第一 參 接合面積； 沿平行於該接合面之方向將接合後之該銅銲線 之第二線端擠壓，以形成一第二銲點部分，此時 該銅銲線與第二接墊之間的接合面具有一第二接 合面積，其中該第二接合面積大於該第一接合面 積； 將該銅銲線之其他部分與第二銲點分離，此時 φ 該第二銲點部分包含一銲線魚尾區和一銲線切斷 區，該銲線魚尾區包含至少一擠壓凸起；以及 以一封膠，包覆該晶片和該銅銲線，並覆蓋該承載 件，使該封膠、該晶片及該承載件形成一封裝體。 21. 依申請專利範圍第20項之半導體封裝方法，其 中沿平行於該接合面方向將接合後之該銅銲線之 第二線端擠壓，包含下列步驟： 定義一擠壓方向，該擠壓方向為通過該第二銲 19 201030867 點部分之旋轉方向；以及 沿該播壓方向將接合後之該銅鋒線之第 壓 端擠 22.依申請專利範圍第20項之半導體 中y单并於$ 4立人 丁午封爰方法，其 甲，口千仃於该接合面之方向將 之第二線端擠壓，包含下列步驟：後之该鋼鮮線 定義為-擠壓方向，該擠壓方向 Θ 向，該直線方向通過該第二鮮點部分上方，=及方 該直線方向垂直於該第一及第二鋒 以及 之直線投影於該承載件之面=所形成 及 乐—表面之直線；以 壓 沿該擠壓方向將接合後之該鋼鲜線之第二端擠 认依申請專利範圍第胃 〇 中沿平行於該接合面之方向將接人德\法，其 之第二線端擠麗，包含下列步驟：口之§亥鋼銲線 定義為-擠壓方向，該擠壓方 該直線方向通過該第二銲點部分i方八方向， 方向平行於該第一及第二銲雖^，且該直線 投影於該承載件之該第三表面二線:及之直線 壓沿該擠壓方向將接合後之該銅銲線之第二端擠 20 201030867 24.依申請專利範圍第20項之半導體封裝方法，其 中該第一接墊為鋁接墊或銅接墊之其t 一者。八 25·、依申請專利範圍第2〇項所述之半導體封裝方 法，其中該承载件為基板。 26.、依申請專利範圍第2〇項所述之半導體封裝方 法’另包含： 、 一金屬層’覆蓋該第二接墊上。 Ο 專利範圍第26項所述之半導體封裝方 '，/、中該金屬層包含鎳、金或鈀之合金。 认依申請專利範圍第2〇項之半導體封裝方法，並 忒弟二接墊為鋁接墊或銅接墊之其中一者。/、 29法依:Γ利範圍第20項所述之半導體封裝方 引 承载件為針架’其中該第二接塾為 引腳接墊。 设翌馮一 3〇:去依：請專利範圍第29項所述之半導體封f方 法，其中該H Μ封破方 —金屬層’覆蓋該弓|聊接墊上。Semiconductor _ _ 1 〇 依 : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : The body: the device & wherein the carrier is a substrate. 13. The semiconductor package 201030867 according to claim 1 further comprises: a metal layer covering the second pad. 14. The semiconductor package of claim 13 wherein the edge metal layer comprises an alloy of nickel, gold or palladium. 15 The semiconductor sealing structure of the pin-shaped carrier according to item 1 is a staple frame. , wherein the second interface is - 16. According to the semiconductor package structure described in claim 15 of the patent application R ^ ^, the nail frame further comprises: a metal layer covering the pin pad. If:: the semiconductor package of the range of the above, wherein the metal layer comprises one of silver, gold or palladium. The semiconductor package according to the first aspect of the invention, wherein the sealant is The composition contains sodium chloride ion. The scorpion and sputum 9. According to the 18th item of the patent application scope Said that 'the sealant PH value is between 4 and 7. The f coat structure 2 〇. - The financial conductor encapsulation method, comprising the τ column step: 5 again - the wafer on the carrier, wherein the wafer has a first surface and an opposite second surface, the wafer comprising - a second pad, the first pad is located on the first surface, and the carrier has a surface and a fourth surface opposite to each other, the carrier comprising a 18th 201030867 second pad, the second pad is located on the third surface; 'providing at least one brazing wire comprising a first wire end and a second wire end; bonding the first wire end of the brazing wire The first pad is formed to form a first pad portion; the second wire end of the brazing wire is bonded to the second pad, and the bonding surface between the brazing wire and the second pad is Having a first joint area; pressing the second line end of the bonded copper wire in a direction parallel to the joint surface to form a second joint portion, at this time, the copper wire and the second The joint mask between the pads has a second joint area, wherein the second joint area is greater than the first a bonding area; separating the other portion of the brazing wire from the second bonding point, wherein the second pad portion includes a wire tailing region and a wire cutting region, the wire tail region comprising at least one Extruding the protrusion; and coating the wafer and the brazing wire with a glue, and covering the carrier to form the encapsulant, the wafer and the carrier into a package. The semiconductor package method of claim 20, wherein the second line end of the bonded copper bonding wire is extruded in a direction parallel to the bonding surface, comprising the steps of: defining a pressing direction, the pressing direction is passing the second Welding 19 201030867 The direction of rotation of the point portion; and the pressing end of the copper front line after the bonding direction is squeezed. 22. According to the patent of the scope of claim 20, the y single is at $4 The crucible method, wherein the armor is pressed in the direction of the joint surface to press the second end of the joint, comprising the following steps: the steel fresh line is defined as - the extrusion direction, the extrusion direction is the direction, the straight line The direction passes above the second fresh spot portion , = and the direction of the straight line perpendicular to the first and second fronts and the line projected onto the surface of the carrier = the line formed and the music - surface; the steel is pressed after pressing the pressing direction The second end of the line is squeezed according to the scope of the patent application. The second side of the stomach is parallel to the joint surface, and the second line is squeezed, including the following steps: Defined as - extrusion direction, the direction of the straight line passes through the second solder joint portion i, the direction is parallel to the first and second solder, and the line is projected on the carrier The three-surface two-wire: and the linear pressure squeezes the second end of the bonded copper wire along the extrusion direction. 2010. The semiconductor package method according to claim 20, wherein the first pad is One of the aluminum pads or copper pads. The semiconductor packaging method of claim 2, wherein the carrier is a substrate. 26. The semiconductor packaging method of claim 2, further comprising: a metal layer covering the second pad.半导体 The semiconductor package described in item 26 of the patent scope, in which the metal layer comprises an alloy of nickel, gold or palladium. Recognize the semiconductor packaging method of the second application of the patent scope, and the two pads are one of aluminum pads or copper pads. /, 29 Fayi: The semiconductor package guiding device described in item 20 of the profit area is a needle holder 'where the second interface is a pin pad.翌 一 一 〇 〇 去 去 去 去 去 去 去 去 去 去 去 去 去 去 去 去 : : : : : : : : : : : : : : : : : : : : : : : : :
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