TWI447847B - Semiconductor device and fabrication method thereof - Google Patents

Description

Semiconductor device and method of fabricating the same

The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a deep trench contact structure and a method of fabricating the same.

In today's semiconductor technology, in order to achieve the operation of a single-chip system, the controller, the memory, the low-voltage operation circuit, and the high-voltage operation power components are highly integrated on a single wafer, in which the power components are developed. The types include vertical double-diffused MOS transistors (VDMOS), insulated gated dual-carrier transistors (IGBT), and lateral power transistors (LDMOS). The research and development aims to improve power conversion efficiency. Loss of energy. Since high voltage transistor components and low voltage CMOS circuit components are required to be provided on a single wafer, an isolation structure for isolating adjacent components is required in the process.

Please refer to FIG. 1, which shows a cross-sectional view of a conventional semiconductor device. The deep trench isolation structure 20 formed of a dielectric material can generally be used to isolate adjacent components, thereby enabling individual control of the power supply parameters of the isolated components. However, the deep trench isolation structure 20 is prone to parasitic capacitance. In addition, the buried oxide layer 30 between the active region of the device and the substrate 10 also generates parasitic capacitance. When the component is operated in a voltage environment, the coupling effect is caused by the charging of the parasitic capacitance described above, and this effect is particularly noticeable in the high voltage component. The capacitive coupling effect not only affects the performance of adjacent components, but also affects other electrically connected high and low voltage components by varying degrees of substrate.

With the continuous advancement of the semiconductor process, the size of the integrated circuit is getting smaller and smaller, the circuit is getting denser and denser, and the working clock is getting faster and faster, and the parasitic resistance effect and parasitic capacitance effect in the circuit inside the chip are getting more and more. Serious, and thus the frequency can no longer be increased, this is called RC delay, RC delay, RC Delay not only hinders the clock growth, but also increases the unnecessary power consumption of the circuit. These effects have different effects on the operation of the circuit, and also cause doubts about the stability of the circuit. Especially in the era of high-speed operation of the circuit today, the tolerance of the circuit to these interferences is getting lower and lower, and the severity of the problem is deepened. .

It is therefore desirable to provide a semiconductor device and method of forming the same that overcomes the deficiencies of the prior art.

The present invention provides a semiconductor device comprising: a substrate; a buried layer formed in the substrate, wherein the buried layer includes an insulating region and a conductor region; and a deep trench A contact structure is formed in the substrate, wherein the deep trench contact structure comprises a conductive material, and the conductive material is electrically connected to the conductor region.

The present invention also provides a method of fabricating a semiconductor device, comprising the steps of: providing a substrate having a buried layer therein, wherein the buried layer includes an insulating region and a conductor region; and forming a deep trench contact in the substrate The structure, wherein the deep trench contact structure comprises a conductive material, and the conductive material is electrically connected to the conductor region.

Embodiments of the present invention provide a semiconductor device and a method of fabricating the same. The manner of manufacture and the manner of use of the various embodiments are described in detail below with reference to the drawings. Wherein, the same component numbers as used in the drawings denote the same or similar components. In the drawings, the shapes and thicknesses of the embodiments may be impractical for clarity and convenience of description. While the following description is specifically directed to the various elements of the device of the present invention or the integration thereof, it is noted that the above-described elements are not particularly limited to those shown or described, but may be those skilled in the art. The various forms are known, and in addition, when a layer of material is placed over another layer or substrate of material, it may be directly on its surface or otherwise interposed with other intervening layers.

2 to 9 are cross-sectional views showing the fabrication of a semiconductor device in accordance with an embodiment of the present invention. Referring to FIG. 2, a substrate 100 is provided, which may have a conductor buried layer 120, an insulating buried layer 140, and an epitaxial layer 160 thereon. Substrate 100 can comprise a substrate of tantalum or other suitable semiconductor material. The insulating buried layer 140 may contain an oxide such as cerium oxide or the like. After forming a mask layer 180 over the epitaxial layer 160, the mask layer 180 can be patterned to expose the surface of the epitaxial layer 160 to be removed. The electrical resistance of the buried conductor layer 120 can be less than the electrical resistance of the substrate 100. In other embodiments, when the resistance of the substrate 100 is small enough, the conductor buried layer 120 may not be present (not shown).

Referring to FIG. 3, after the patterned mask layer 180 is formed over the epitaxial layer 160, an etching process may be performed to remove the epitaxial layer 160 exposed by the mask layer 180 to form a first deep trench. 200, wherein the first deep trench 200 formed exposes an upper surface of the insulating buried layer 140. In other embodiments, the etching process may be performed to remove the epitaxial layer 160 exposed by the mask layer 180 and the insulating buried layer 140 located under the epitaxial layer 160 to form the first deep trench 200. The formed first deep trench 200 exposes a portion below the upper surface of the insulating buried layer 140 (not shown). The mask layer 180 is then removed.

Referring to FIG. 4, after the first deep trench 200 is formed, a liner layer 210 may be formed on the sidewalls and the bottom surface of the first deep trench 200. The liner layer 210 may also extend onto the upper surface of the epitaxial layer 160. The backing layer 210 may comprise an oxide such as tetraethoxy silane (TEOS). Then, an etching process may be performed to remove the liner layer 210 exposed above the insulating buried layer 140 by the first deep trench 200, and the first deep trench 200 may be exposed after the liner layer 210 is removed. The insulating buried layer 140 is removed to form a second deep trench 220 below the first deep trench 200, as shown in FIG. 5, and retaining the liner layer 210 on the sidewall of the first deep trench 200. Referring to FIG. 5, the second deep trench 220 formed may expose the upper surface of the conductor buried layer 120. In another embodiment, the etching process performed may remove the portion of the buried conductor layer 120 exposed by the first deep trench 200 after the insulating buried layer 140 is removed, and the formed second deep trench 220 is exposed. The portion below the upper surface of the conductor buried layer 120 (not shown). In other embodiments, when the buried conductor layer 120 is absent, the formed second deep trench 220 may expose a portion below the surface or surface of the substrate 100 under the insulating buried layer 140.

Referring to FIG. 6, a doping process can be performed to form a doped region 230 in the buried conductor layer 120 exposed by the second deep trench 220. After the doping process, an annealing process may be further performed to diffuse the doping region 230 in the lateral and longitudinal directions, for example, laterally diffused into the buried layer 120 of the conductor below the insulating buried layer 140, and diffused longitudinally to the conductor. In the deeper area of the buried layer 120, as shown in Fig. 6. The doped region 230 may have the same conductivity type as the conductor buried layer 120. In one embodiment, the doped region 230 and the buried conductor layer 120 are all N-type conductive. The doping concentration of the doping region 230 may generally be greater than the doping concentration of the buried layer 120 of the conductor. The formation of doped regions 230 provides better doping uniformity to form a better interface resistance/capacitance, as well as a more stable (ohmic contact) conductive member. In other embodiments, when the resistance of the substrate 100 is small enough, the buried conductor layer 120 may be absent, and thus the doped region 230 may be formed in the substrate 100 exposed by the second deep trench 220 (not shown). In another embodiment, doped regions 230 may not be formed (not shown).

Referring to FIG. 7 , after the doping region 230 is formed, a conductive material 240 may be formed to fill the first deep trench 200 and the second deep trench 220 , and the conductive material 240 may extend onto the surface of the liner layer 210 . Conductive material 240 can comprise a conductive material such as doped polysilicon. In a preferred embodiment, the conductive material 240 is a doped polysilicon formed by in-situ chemical vapor deposition in an atmosphere of a gas doped with impurities. The conductive material 240, the doped region 230, and the conductor buried layer 120 may be of the same conductivity type. In one embodiment, the conductive material 240, the doped region 230, and the buried conductor layer 120 are all N-type conductive. In a preferred embodiment, the conductive material 240 is a polysilicon doped with an N-type impurity. In other embodiments, the electrically conductive material 240 can comprise a metal such as tungsten or aluminum.

Since the liner layer 210 and the epitaxial layer 160 generally containing oxides have a large lattice difference with each other, stress is easily generated at the joint interface thereof, especially in the high-temperature process performed in the subsequent manufacturing steps, and is more likely to increase. The difference in the large lattice causes structural defects. Selecting the doped polysilicon as the conductive material 240 can buffer the stress problem between the above materials, thereby improving the stability and efficiency of the device.

Referring to FIG. 8, an etching back process can then be performed to remove the conductive material 240 formed over the liner layer 210 and form a deep trench contact structure 260.

Due to the deep trench contact structure 260, the conductive material 240 containing the doped polysilicon can be formed by synchronous chemical vapor deposition in an environment with a gas doped with impurities, without an additional doping process to avoid The contamination problem that may result from the doping process, or the problem of reduced component performance due to impurity diffusion, can be designed such that the deep trench contact structure 260 can be designed closer to the main component. Since the sidewall of the deep trench contact structure 260 has a spacer layer 210 such as an insulating oxide, the deep trench contact structure 260 can also serve as an isolation structure for the isolation component. In one embodiment, the deep trench contact structure 260 can be used. Define the active area of the component. In another embodiment, the deep trench contact structure 260 and the insulating buried layer 140 may define active regions of the components.

Referring to FIG. 9, after the deep trench contact structure 260 is formed, the interlayer dielectric layer 300 may be further formed over the deep trench contact structure 260 and the liner layer 210, passing through the interlayer dielectric layer 300 and contacting the deep trench contact structure 260. Electrically connected contact plugs 320, such as tungsten plugs. In one embodiment, the sidewalls and bottom of the contact plugs 320 may have a barrier layer 310 such as titanium or titanium nitride and are formed over the contact plugs 320. Metal layer 330. The conductor buried layer 120, the doped region 230 and the deep trench contact structure 260 can be electrically connected to the outside through the contact plug 320 and the metal layer 330.

Due to the conductive material 240 in the deep trench contact structure 260, the conductive buried layer 120 (or the substrate 100) and the doped region 230 can be electrically connected to the outside through the contact plug 320 and the metal layer 330. When the parasitic charge formed in the insulating buried layer 140 and the liner layer 210 is formed, an external power source electrically connected to the conductive material 240, the conductor buried layer 120 (or the substrate 100), and the doping region 230 may be grounded to make a parasitic charge. The conductor buried layer 120 (or the substrate 100) adjacent to the insulating buried layer 140 and the pad layer 210, respectively, and the conductive material 240 can be conducted to the outside to avoid noise problems due to parasitic capacitance. The voltage of the conductor buried layer 120 (or the substrate 100) can also be externally controlled via the deep trench contact structure 250.

In the semiconductor device and the method for forming the same disclosed in the embodiments of the present invention, a deep trench contact structure is formed in the substrate having the insulating buried layer and the buried layer of the conductor therein, wherein the deep trench contact structure comprises a conductive material and is located at the conductive a liner layer on the sidewall of the material.

The conductive material of the deep trench contact structure may be formed by synchronous vapor deposition in a gas atmosphere with doping impurities, without performing an additional doping process to avoid possible contamination or degradation of component performance. Therefore, the deep trench contact structure can be designed to be located closer to the main component. The liner layer of the deep trench contact structure is an oxide layer having insulating properties, so that the deep trench contact structure can be used as an isolation structure of the isolation element, and can be used to define the active region of the component, and can reduce the active region required for a single component. area. For the above reasons, the deep trench contact structure formed according to the embodiment of the present invention can greatly increase the number of components that can be disposed in a single wafer and increase the density of components. When the doped polysilicon is selected as the conductive material in the deep trench contact structure, it can buffer the stress caused by the lattice difference between the liner layer and the epitaxial layer containing the oxide, thereby improving the stability of the element and efficacy.

The conductive material in the deep trench contact structure, and the buried layer (or substrate) of the conductor and the doped region can be electrically connected to the outside through the contact plug and the metal layer. Therefore, the parasitic charge formed in the insulating buried layer or the liner layer due to the operating element can be conducted to the outside via the conductive material, the buried layer (or substrate) of the conductor, and the doped region to avoid generation due to parasitic capacitance. Noise problem. The voltage of the buried layer (or substrate) of the conductor can also be externally controlled via the deep trench contact structure. The formation of the doped regions provides better doping uniformity and provides a better interface resistance/capacitance between the conductor buried layer (or substrate) and the conductive material of the deep trench contact structure, and is more stable. A conductive member (ohmically contacted).

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

10. . . Base

20. . . Deep trench insulation structure

30. . . Buried oxide layer

100. . . Base

120. . . Conductor buried layer

140. . . Insulating buried layer

160. . . Epitaxial layer

180. . . Mask layer

200. . . First deep trench

210. . . Liner layer

220. . . Second deep trench

230. . . Doped region

260. . . Deep trench contact structure

300. . . Interlayer dielectric layer

310. . . Barrier layer

320. . . Contact plug

330. . . Metal layer

Figure 1 shows a cross-sectional view of a conventional semiconductor device.

2 through 9 show cross-sectional views of forming a deep trench contact structure in accordance with an embodiment of the present invention.

100. . . Base

120. . . Conductor buried layer

140. . . Insulating buried layer

160. . . Epitaxial layer

210. . . Liner layer

230. . . Doped region

260. . . Deep trench contact structure

300. . . Interlayer dielectric layer

310. . . Barrier layer

320. . . Contact plug

330. . . Metal layer

Claims (12)

A semiconductor device comprising: a substrate; an insulating buried layer formed in the substrate; and a buried conductor layer formed in the substrate and under the insulating buried layer, wherein the conductor buried layer has a lower electrical resistance than the substrate a deep trench contact structure formed in the substrate, wherein the deep trench contact structure comprises a conductive material and a liner layer filled in a deep trench, wherein the liner layer is formed adjacent to the deep trench The sidewall of the insulating layer is not adjacent to the buried layer of the conductor, so that the conductor is buried to fill all portions of the bottom surface of the deep trench, and the conductive material is in direct contact with the buried layer of the conductor. The semiconductor device of claim 1, wherein the liner layer comprises an oxide. The semiconductor device of claim 1, wherein the conductive material comprises doped polysilicon. The semiconductor device of claim 1, further comprising a doped region formed between the deep trench contact structure and the substrate. The semiconductor device of claim 1, further comprising a doped region formed between the deep trench contact structure and the buried layer of the conductor. The semiconductor device of claim 5, wherein the doped region is formed between the conductive material and the buried layer of the conductor. A method of fabricating a semiconductor device, comprising the steps of: Providing a substrate having a buried conductor layer and an insulating buried layer therein, wherein the buried layer of the conductor is located under the insulating buried layer, wherein a resistance of the buried layer of the conductor is less than a resistance of the substrate; forming an epitaxial layer thereon On the insulating buried layer; patterning the epitaxial layer to form a first deep trench in the epitaxial layer; forming a liner layer on the epitaxial layer and filling the first deep trench; performing an etching a process of removing a liner layer at the bottom of the first deep trench and removing a portion of the buried buried layer exposed by the first deep trench to form a second deep trench; and forming a conductive material to fill the first deep trench and In the second deep trench, the deep trench contact structure is formed, wherein the liner layer is not formed in the second deep trench, so that the conductive material fills all portions of the bottom surface of the second deep trench. The method of fabricating a semiconductor device according to claim 7, further comprising forming a doped region between the deep trench contact structure and the substrate. The method of fabricating a semiconductor device according to claim 8, further comprising forming the doped region between the deep trench contact structure and the buried layer of the conductor. The method of fabricating a semiconductor device according to claim 7, wherein the second deep trench exposes the buried layer of the conductor. The method of fabricating a semiconductor device according to claim 7, wherein the second deep trench exposes the substrate, and the second deep The doped region is formed in the substrate exposed by the trench. The method for fabricating a semiconductor device according to claim 10, further comprising forming the doped region in the buried layer of the conductor exposed by the second deep trench.