TWI421604B - Pixel array - Google Patents

Description

Pixel array structure

This invention relates to a display array, and more particularly to a pixel array structure.

A general flat panel display is mainly composed of a display panel and a plurality of driver ICs. The display panel is mainly composed of a thin film transistor array substrate, a counter substrate, and a liquid crystal layer sandwiched between the two substrates. The thin film transistor array substrate mainly comprises a plurality of scan lines, a plurality of data lines, a thin film transistor arranged between the scan lines and the data lines, and a pixel electrode (Pixel Electrode) arranged corresponding to each of the thin film transistors. The above thin film transistor includes a gate, a source and a drain, which are used as switching elements of the liquid crystal display unit.

The fabrication process of a thin film transistor array substrate typically involves multiple development and etching steps. In general manufacturing techniques, the gate and scan lines are the first metal layer (Metal 1), and the source, drain and data lines are the second metal layer (Metal 2). Moreover, there is at least one dielectric layer between the first metal layer and the second metal layer. In the structure of the thin film transistor, the gate and the drain are at least partially overlapped, so that there is usually a so-called gate-drain parasitic capacitance (hereinafter referred to as Cgd) between the gate and the drain.

In recent years, in order to make the products of liquid crystal displays more popular, the industry is in full swing. For cost reduction operations, an architectural design of a half source driver is proposed, which primarily utilizes the layout on the thin film transistor array substrate to reduce the amount of data driven wafer usage. However, this design causes the orientation of the switching elements to be different, so that the difference in Cgd of the entire panel becomes large, causing uneven display of the screen.

Figure 1 is a schematic diagram of a conventional pixel array of a semi-data driven wafer. Referring to FIG. 1, in a conventional pixel array design, two scan lines 12 are located between two adjacent columns of pixels 13a, 13b, wherein the switching elements 14 and 15 of the two pixels 13a, 13b are The gates 41, 51 are respectively located on both sides of the scanning line 12a. In the fabrication flow of the switching elements 14, 15 having the above structure, when the precision of the machine is insufficient or the bit error on the process, the gates 41, 51 and the sources 42 and 52 of the switching elements 14, 15 The relative displacement between the drains 43 and 53 causes the characteristics of the switching elements 14, 15 to deviate from the original design values. At this time, since the gates 41 and 51 are respectively disposed on both sides of the corresponding scanning line 12, when the gates 41 and 51 of the switching elements 14 and 15 and the drains 43 and 53 are relatively displaced, the pixels 130a and 130b are The overlapping areas of the gates 41, 51 of the switching elements 14, 15 and the drains 43 and 53 are all different. If the direction of the pixel 13b is shifted, the Cgd of the pixel 13a on the side of the scanning line 12 is changed. Large, and the Cgd of the pixel 13b located on the other side of the scanning line 12 becomes smaller, resulting in a difference in Cgd in the pixels 13a, 13b. As a result, due to the error in the above process, the gate-drain parasitic capacitance Cgd of the entire display panel is somewhat small, so the array substrate is prone to display brightness unevenness during display. .

The invention provides a pixel array structure, which effectively improves the problem that the gate-drain parasitic capacitance changes due to the alignment error in the process.

The present invention provides a pixel array structure comprising a plurality of scan lines, a plurality of data lines extending in a direction perpendicular to the scan line, and a plurality of pixel units. Each of the data lines includes a first portion parallel to the scan line and a second portion perpendicular to the scan line, and the first portion is coupled to the second portion. Each two adjacent scan lines and each two adjacent data lines define a two pixel unit. Each pixel unit includes a switching element and a pixel electrode. The switching element has a gate, a source and a drain. The gate is electrically connected to the scan line, and the source and the data line are electrically connected. Sexually connected, the drain is electrically connected to the pixel electrode, and the drain of the switching element of the two pixel unit is facing the same side. Therefore, when the gate and the drain of the switching element are relatively displaced, the relative displacements of the gate and the drain of the entire panel switching element are all toward the same side, so that the entire display panel gate-drain parasitic capacitance Cgd At the same time, it is too large or too small, which improves the uneven brightness of the screen and improves the display quality of the screen.

In an embodiment of the invention, the first portion of the data line is located between the first scan line and the second scan line.

In an embodiment of the invention, the first portion of the data line overlaps the first scan line.

In an embodiment of the invention, the first portion of the data line overlaps the second scan line.

In an embodiment of the invention, the first portion and the second portion of the data line are staggered and connected to present a waveform and extend in a direction perpendicular to the scan line.

In an embodiment of the invention, the pixel unit includes a switching element and a picture a switching electrode comprising a gate electrically connected to the scan line, a source electrically connected to the first portion of the data line or the second portion of the data line, and a drain electrically connected to the pixel electrode .

In an embodiment of the invention, the source of the one or more switching elements is located on a corresponding side of the first portion of the data line.

In an embodiment of the invention, the source of the one or more switching elements is located on the same side of the second portion of the data line.

According to the above, the pixel array structure of the present invention has the switching elements facing the same side, so that the relative offset of the gate film layer (M1) and the gate film layer (M2) of the switching element is directed to the same side due to the process. Thus, the entire gate-drain parasitic capacitance of the panel is simultaneously increased or decreased at the same time, thereby reducing the difference in gate-drain parasitic capacitance of the display panel and improving the picture display quality.

The above described features and advantages of the present invention will be more apparent from the following description.

10‧‧‧ glass substrate

20‧‧‧Insulation

100, 110, 120, 130‧‧‧ pixel units

101, 111, 121, 131‧‧‧ switch components

Gates of 1011, 1111, 1211, 1311‧‧ ‧ switch components

Source of 1012, 1112, 1212, 1312‧‧ ‧ switch components

1013, 1113, 1213, 1313‧‧ ‧ bungee of switch components

102, 112, 122, 132‧‧‧ pixel electrodes

200, 210, 220, 230‧‧‧ scan lines

21, 201, 211, 221, 231‧‧‧ first scan line

22, 202, 212, 222, 232‧‧‧ second scan line

300, 310, 320, 330‧‧‧ data lines

31, 301, 311, 321, 331 ‧ ‧ the first part of the data line

302, 312, 322, 332‧‧‧ the second part of the data line

Figure 1 is a schematic view of a conventional array substrate.

2 is a schematic view of an array substrate according to Embodiment 1 of the present invention.

Fig. 3 is a partially enlarged view of the array substrate of Fig. 2.

Figure 4 is a schematic diagram of the distribution of data lines in Figure 2.

FIG. 5 is a schematic view of an array substrate according to Embodiment 2 of the present invention.

Fig. 6 is a partially enlarged view of the array substrate of Fig. 5.

Figure 7 is a schematic diagram of the distribution of data lines in Figure 5.

Figure 8 is a schematic view of an array substrate according to a third embodiment of the present invention.

Fig. 9 is a partially enlarged view of the array substrate of Fig. 8.

Figure 10 is a schematic diagram of the distribution of data lines in Figure 8.

Figure 11 is a schematic view of an array substrate according to a fourth embodiment of the present invention.

Fig. 12 is a partially enlarged view of the array substrate of Fig. 11.

Figure 13 is a schematic diagram of the distribution of data lines in Figure 11.

Figures 14a, 14b, and 14c are cross-sectional views of the data lines.

2 is a schematic view of an array substrate according to Embodiment 1 of the present invention, and FIG. 3 is a partially enlarged view of the array substrate of FIG. 2. Referring to FIG. 2 and FIG. 3 simultaneously, in the embodiment, the array substrate includes a plurality of scanning lines 200 extending in the row direction, and the plurality of data lines 300 are bent and extended in the column direction, and intersect with the scanning lines 200 but not An electrical connection, wherein the row direction and the column direction are perpendicular to each other; and a plurality of pixel units 100 disposed in an area formed by the scan line 200 and the data line 300, and electrically connected to the data line 300 And each data line 300 is electrically connected to two adjacent columns of pixel units. Further, the scan line 200 includes a first scan line 201 and a second scan line 202. Each data line 300 includes a first portion 301 and a second portion 302, and the first portion 301 of the data line 300 is The scan line 200 is parallel, and the second portion 302 of the data line 300 is perpendicular to the scan line 200, wherein the first portion 301 and the second portion 302 of the data line 300 are staggered and mutually connection. The pixel unit 100 is located in a region formed by the first scan line 201, the second scan line 200, and the second portion 302 of the data line, and has two pixel units 100 in the area.

The pixel unit 100 shown in FIGS. 2 and 3 includes a switching element 101 and a pixel electrode 102. The switching element 101 has a gate 1011, a source 1012, and a drain 1013. The gate 1011 of the switching element 101 is electrically connected to the scan line 200. More specifically, the gate 1011 of the switching element 101 and the scan line 200 belong to the same metal layer (M1), and The gate electrode 1011 and the scan line 200 are formed by the same process such as development etching; wherein the source 1012 of the switching element 101 of the pixel unit 100 is electrically connected to the data line 300, and the switch The drain 1013 of the element 101 is electrically connected to the pixel electrode 102 through a contact hole. More specifically, the source 1012 of the switching element 101 and the drain 1013 and the data line 300 belong to the same metal layer (M2), and the source 1012, the drain 1013 and the data line 300 are identical. A process such as a channel development etching is formed.

Fig. 4 is a schematic diagram showing the distribution of the data line traces of Fig. 2, in which only the data line 300 and the switching element 101 are shown. Referring to FIG. 4, the first portion 301 and the second portion 302 of the data line 300 are staggered and connected to each other, that is, the two ends of the first portion 301 of the data line 300 are connected as the data line. The two parts 302, and the two ends of the second part 302 of the data line 300 are connected as the first part 301 of the data line. It should be noted that the two ends are not only the data line 300 shown in the figure. The first portion 301 or the end of the second portion 302 of the data line 300 means that the system can be near the end point or end point. As shown in FIG. 4, the first portion 301 of the adjacent upper and lower two data lines 300 is connected at both ends of the second portion 302 of each data line 300. An end point of the second portion 302 of the middle data line 300 is connected to an end point of the first portion 301 of the upper data line adjacent thereto, and the next data adjacent thereto is connected to the other end of the second portion 302 of the data line 300. An end point of the first portion 301 of the line. Thus, the first portion 301 of the data line 300 is interleaved with the second portion 302 of the data line 300 and the data line 300 extends in a direction perpendicular to the scan line 200 as a whole, and the first portion 301 and the second portion 302 of the data line 300 are For electrical connection, more specifically, the first portion 301 and the second portion 302 of the data line 300 belong to the same metal layer (M2), which is formed by the same material development etching process. Macroscopically and as shown, the data line 300 extends in a square waveform.

Following the above, the source 1012 of the switching element 101 is connected to the data line 300, and is located on the second portion 302 of the data line 300, and each of the second portions 302 of each data line 300 is connected to two. The middle source 1012 of the switching element 101, and the source 1012 of the two switching elements 101 are located at two end points of the second portion 302 of the data line 300, and the source 1012 of the two switching elements 101 In the present embodiment, the drains 1013 of the source 1012 of the two switching elements 101 are all facing the right side, that is, the drain of the entire thin film transistor array substrate switching element 101 in this embodiment. 1013 is toward the right side, and the gate 1011 of the switching element 101 belongs to the first metal film layer (M1) and the drain 1013 of the switching element 101 belongs to the second metal film layer (M2). When the alignment error causes a change in Cgd, since the drain 1013 of the switching element 101 of the entire panel is directed to the right side, the Cgd of the entire panel is simultaneously large or small, thereby reducing the difference between the entire panel Cgd and avoiding The screen shows uneven brightness

5 is a schematic diagram of an array substrate according to Embodiment 2 of the present invention, and FIG. 6 is a diagram of FIG. A partial enlarged view of the array substrate. Referring to FIG. 5 and FIG. 6 simultaneously, in the embodiment, the array substrate includes a plurality of scanning lines 210 extending in the row direction, and the plurality of data lines 310 are meandered in the column direction and intersecting the scanning lines 210 but not An electrical connection, wherein the row direction and the column direction are perpendicular to each other; and a plurality of pixel units 110 disposed in an area formed by the scan line 210 and the data line 310, and electrically connected to the data line 310 And each data line 310 is electrically connected to two adjacent columns of pixel units. Further, the scan line 210 includes a first scan line 211 and a second scan line 212. Each data line 310 includes a first portion 311 and a second portion 312, and the first portion 311 of the data line 310 is The scan lines 210 are parallel, and the second portion 312 of the data lines 310 is perpendicular to the scan lines 210, wherein the first portion 311 and the second portion 312 of the data lines 310 are staggered and connected to each other. The pixel unit 110 is located in a region formed by the first scan line 211, the second scan line 210, and the second portion 312 of the data line, and has two pixel units 110 in the area.

The pixel unit 110 shown in FIGS. 5 and 6 includes a switching element 111 and a pixel electrode 102. The switching element 111 has a gate 1111, a source 1112, and a drain 1113. The gate 1111 of the switching element 111 is electrically connected to the scan line 210. More specifically, the gate 1111 of the switching element 111 and the scan line 210 belong to the same metal layer (M1), and The gate 1111 and the scan line 210 are formed by the same process of developing etching, etc., wherein the source 1112 of the switching element 111 of the pixel unit 110 is electrically connected to the data line 310, and the switch The drain electrode 1113 of the element 111 is electrically connected to the pixel electrode 102 through a contact hole, more specifically, the source electrode 1112 of the switching element 111, the drain electrode 1113, and the capital The material line 310 belongs to the same metal layer (M2), and the source electrode 1112, the drain electrode 1113 and the data line 310 are formed by the same development etching process.

Fig. 7 is a schematic diagram showing the distribution of the data line traces of Fig. 5, in which only the data line 310 and the switching element 111 are shown. Referring to FIG. 4, the first portion 311 and the second portion 312 of the data line 310 are staggered and connected to each other, that is, the two ends of the first portion 311 of the data line 310 are connected as the data line. The two portions 312, and the two ends of the second portion 312 of the data line 310 are connected as the first portion 311 of the data line. It should be noted that the two ends are not only the data lines 310 shown in the figure. The end of the first portion 311 or the second portion 312 of the data line 310 means that the system can be near the end point or end point. As shown in FIG. 7, the first portion 311 of the adjacent upper and lower data lines is connected at both ends of the second portion 312 of each data line, wherein an end point of the second portion 312 of the data line is connected to the upper portion adjacent thereto. An end point of the first portion 311 of the line connects an end point of the first portion 311 of the lower data line adjacent thereto at the other end adjacent to the second portion 312 of the data line. The first portion 311 of the data line is interleaved with the second portion 312 of the data line and the data line 310 extends in a direction perpendicular to the scan line 210 as a whole, and the first portion 311 and the second portion 312 of the data line 310 are Electrically connected, more specifically, the first portion 311 and the second portion 312 of the data line 310 belong to the same metal layer (M2), which is formed by the same material development etching process. Macroscopically and as shown, the data line 310 extends in a square waveform.

Following the above, the source 1112 of the switching element 111 is connected to the data line 310, and is located on the second portion 312 of the data line 310, and each of the second portions 312 of each data line 310 is connected to two. The middle source 1112 of the switching element 111, and both The source 1112 of the switching elements 111 is located at two end points of the second portion 312 of the data line 310, and the sources 1112 of the two switching elements 111 are oriented toward the same side; in this embodiment The drains 1113 of the source 1112 of the two switching elements 111 are all facing the left side, that is, the drains 1113 of the entire thin film transistor array substrate switching element 111 in the present embodiment are all facing the left side, and the switching elements 111 are The gate 1111 belongs to the first metal film layer (M1) and the drain electrode 1113 of the switching element 111 belongs to the second metal film layer (M2). When there is a registration error between the film layers, Cgd changes, due to the whole The drains 1113 of the switching elements 111 of the panel are all directed to the left side, so that the Cgd of the entire panel is too large or small at the same time, thereby reducing the difference between the entire panels Cgd, and avoiding the problem of uneven brightness of the screen display.

8 is a schematic view of an array substrate according to a third embodiment of the present invention, and FIG. 9 is a partially enlarged view of the array substrate of FIG. 8. Referring to FIG. 8 and FIG. 9 simultaneously, in the embodiment, the array substrate includes a plurality of scanning lines 220 extending in the row direction, and the plurality of data lines 320 are meandered in the column direction and intersecting the scanning line 220 but not An electrical connection, wherein the row direction and the column direction are perpendicular to each other; and a plurality of pixel units 120 disposed in the area formed by the scan line 220 and the data line 320, and electrically connected to the data line 320 And each data line 320 is electrically connected to two adjacent columns of pixel units. Further, the scan line 220 includes a first scan line 221 and a second scan line 222. Each data line 320 includes a first portion 321 and a second portion 322, and the first portion 321 of the data line 320 is The scan line 220 is parallel, and the second portion 322 of the data line 320 is perpendicular to the scan line 220, wherein the first portion 321 and the second portion 322 of the data line 320 are staggered and connected to each other. The pixel unit 120 is located on the first scan line 221 and the second scan line. 220 and a region formed by the second portion 322 of the data line, and having two pixel units 120 in the region.

The pixel unit 120 shown in FIGS. 8 and 9 includes a switching element 121 and a pixel electrode 122. The switching element 121 has a gate 1211, a source 1212 and a drain 1213. The gate 1211 of the switching element 121 is electrically connected to the scan line 220. More specifically, the gate 1211 of the switching element 121 and the scan line 220 belong to the same metal layer (M1), and The gate 1211 and the scan line 220 are formed by the same process of development etching; wherein the source 1212 of the switching element 121 of the pixel unit 120 is electrically connected to the data line 320, and the switch The drain electrode 1213 of the element 121 is electrically connected to the pixel electrode 122 through a contact hole, and more specifically, the source electrode 1212 of the switching element 121 and the drain electrode 1213 and the data line 320 belong to the same metal layer (M2), and The source electrode 1212, the drain electrode 1213 and the data line 320 are formed by the same process such as development etching.

Fig. 10 is a schematic diagram showing the distribution of the data line traces of Fig. 8, in which only the data line 320 and the switching element 121 are shown. Referring to FIG. 10, the first portion 321 and the second portion 322 of the data line 320 are staggered and connected to each other, that is, the first portion 321 of the data line 320 is connected to the data line. The two portions 322, and the two ends of the second portion 322 of the data line 320 are connected as the first portion 321 of the data line. It should be noted that the two ends of the data line are not only the data lines 320 shown in the figure. The first portion 321 or the end of the second portion 322 of the data line 320. Moreover, as shown in FIG. 10, adjacent first and second data line second portions 322 are connected at both ends of the first portion 321 of each data line, wherein one end of the first portion 321 of the data line is connected to the upper portion adjacent thereto. An end point of the second portion 322 of the data line Near the other end of the first portion 321 of the data line is connected to an end point of the second portion 322 of the lower data line adjacent thereto. The first portion 321 of the data line is interleaved with the second portion 322 of the data line and the data line 320 extends in a direction perpendicular to the scan line 220 as a whole, and the first portion 321 and the second portion 322 of the data line 320 are Electrically connected, more specifically, the first portion 321 and the second portion 322 of the data line 320 belong to the same metal layer (M2), which is formed by the same material development etching process. Macroscopically and as shown, data line 320 extends in a square waveform.

In the above, the source 1212 of the switching element 121 is connected to the data line 320, and is located on the second portion 322 of the data line 320. Two second portions 322 of each data line 320 are connected to each other. The middle source 1212 of the switching element 121, and the source 1212 of the two switching elements 121 are located at two end points of the second portion 322 of the data line 320, and the source 1212 of the two switching elements 121 The gates 1213 corresponding to the source 1212 of the two switching elements 121 are all facing the right side, that is, the bucker of the entire thin film transistor array substrate switching element 121 in this embodiment. 1213 is toward the right side, and the gate 1211 of the switching element 121 belongs to the first metal film layer (M1) and the drain electrode 1213 of the switching element 121 belongs to the second metal film layer (M2). When the alignment error causes a change in Cgd, since the drain 1213 of the switching element 121 of the entire panel is directed to the right side, the Cgd of the entire panel is simultaneously large or small, thereby reducing the difference between the entire panel Cgd and avoiding The screen shows uneven brightness

11 is a schematic view of an array substrate according to Embodiment 4 of the present invention, and FIG. 12 is a partially enlarged view of the array substrate of FIG. 11. Please also refer to Figure 11 and Figure 12 in this implementation. In the example, the array substrate includes a plurality of scanning lines 230 extending in the row direction, and the plurality of data lines 330 are bent and extended in the column direction, and intersect with the scanning lines 230 but are not electrically connected, wherein the row direction and the column direction are perpendicular to each other. And a plurality of pixel units 130 disposed in the area formed by the scan line 230 and the data line 330, electrically connected to the data line 330, and each data line 330 is electrically connected to the left and right adjacent Two columns of pixel units. Further, the scan line 230 includes a first scan line 231 and a second scan line 232. Each data line 330 includes a first portion 331 and a second portion 332, and the first portion 331 of the data line 330 is The scan lines 230 are parallel, and the second portion 332 of the data lines 330 is perpendicular to the scan lines 230, wherein the first portion 331 and the second portion 332 of the data lines 330 are staggered and connected to each other. The pixel unit 130 is located in a region formed by the first scan line 231, the second scan line 230, and the second portion 332 of the data line, and has two pixel units 130 in the area.

The pixel unit 130 shown in FIGS. 11 and 12 includes a switching element 131 and a pixel electrode 132. The switching element 131 has a gate 1311, a source 1312, and a drain 1313. The gate 1311 of the switching element 131 is electrically connected to the scan line 230. More specifically, the gate 1311 of the switching element 131 and the scan line 230 belong to the same metal layer (M1), and The gate 1311 and the scan line 230 are formed by the same process of developing etching, etc., wherein the source 1312 of the switching element 131 of the pixel unit 130 is electrically connected to the data line 330, and the switch The drain electrode 1313 of the element 131 is electrically connected to the pixel electrode 132 through a contact hole, and more specifically, the source electrode 1312 of the switching element 131 and the drain electrode 1313 and the data line 330 belong to the same metal layer (M2), and The source 1312, the bungee 1313 and the data line 330 are formed by the same process such as development etching.

Fig. 13 is a diagram showing the distribution of the data line traces of Fig. 12, in which only the data line 330 and the switching element 131 are shown. Referring to FIG. 4, the first portion 331 and the second portion 332 of the data line 330 are staggered and connected to each other, that is, the two ends of the first portion 331 of the data line 330 are connected as the data line. The two portions 332, and the two ends of the second portion 332 of the data line 330 are connected as the first portion 331 of the data line. It should be noted that the two ends of the data line are not only the data lines 330 shown in the figure. The first portion 331 or the end of the second portion 332 of the data line 330. As shown in FIG. 13, a second portion 332 of adjacent upper and lower data lines is connected at both ends of the first portion 331 of each data line, wherein one end of the first portion 331 of the data line is connected to the upper data line adjacent thereto. An endpoint of the second portion 332 is coupled to an endpoint of the second portion 332 of the lower data line adjacent thereto at the other end of the first portion 331 of the data line. The first portion 321 of the data line is interleaved with the second portion 322 of the data line and the data line 320 extends in a direction perpendicular to the scan line 220 as a whole, and the first portion 331 and the second portion 332 of the data line 330 are Electrically connected, more specifically, the first portion 331 and the second portion 332 of the data line 330 belong to the same metal layer (M2), which is formed by the same material development etching process. Macroscopically and as shown, data line 330 extends in a square waveform.

Following the above, the source 1312 of the switching element 131 is connected to the data line 330, and is located on the second portion 332 of the data line 330, and two second portions 332 of each data line 330 are connected to each other. The middle source 1312 of the switching element 131, and the source 1312 of the two switching elements 131 are located at the second portion 332 of the data line 330 At the two end points, the source 1312 of the two switching elements 131 are oriented toward the same side; in this embodiment, the drains 1313 of the source 1312 of the two switching elements 131 are all facing the left side, That is, in the present embodiment, the drain 1313 of the entire thin film transistor array substrate switching element 131 is directed to the left side, and the gate 1311 of the switching element 131 belongs to the first metal film layer (M1) and the drain of the switching element 131 1313 belongs to the second metal film layer (M2). When a Cgd change occurs when there is a registration error between the film layers, since the drain 1313 of the switching element 131 of the entire panel is directed to the left side, the Cgd of the entire panel is caused. At the same time, it is too large or too small to reduce the difference between the entire panel Cgd, and avoids the problem of uneven brightness of the screen display.

Figures 14a, 14b, and 14c are cross-sectional views of the data lines of the present invention and show only the first portion of the data lines. As shown in FIG. 14a, wherein 10 is a glass substrate and 20 is an insulating layer, in the embodiment, the first portion 31 of the data line is located above the first scanning line 21, that is, the first portion 31 of the data line and the first scanning line 21 overlapping. In the embodiment shown in Fig. 14b, the first portion 31 of the data line is located above the second scanning line 22, i.e., the first portion 31 of the data line overlaps the second scanning line 22. In the embodiment shown in Fig. 14c, the first portion 31 of the data line is located between the first scan line 21 and the second scan line 22.

It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and are not limited thereto; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that The technical solutions described in the foregoing embodiments are modified, or the equivalents of the technical features are replaced. The modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.

100‧‧‧ pixel unit

101‧‧‧Switching elements

102‧‧‧ pixel electrodes

200‧‧‧ scan line

201‧‧‧First scan line

202‧‧‧Second scan line

300‧‧‧Information line

The first part of the 301‧‧‧ data line

302‧‧‧Part II of the data line C

Claims (9)

A pixel array structure comprising: a plurality of scan lines, wherein the scan lines comprise a first scan line and a second scan line; a plurality of data lines, wherein each of the data lines includes a first portion parallel to the scan line and a second portion perpendicular to the scan line, and the first portion is interleaved with the second portion; a plurality of pixel units, wherein each two adjacent scan lines and each two adjacent data lines define two a pixel unit, each pixel unit includes a switching element and a pixel electrode, the switching element has a gate, a source, and a drain, the gate is electrically connected to the scan line, and the source is The data line is electrically connected, and the drain is electrically connected to the pixel electrode, and the drain of the switching element of the two pixel unit is facing the same side. The pixel array structure of claim 1, wherein the first portion of the data line is between the first scan line and the second scan line. The pixel array structure of claim 1, wherein the first portion of the data line overlaps the first scan line. The pixel array structure of claim 1, wherein the first portion of the data line overlaps the second scan line. The pixel array structure of claim 1, wherein the first portion and the second portion of the data line are staggered and connected to present a waveform and extend in a direction perpendicular to the scan line. The pixel array structure of claim 1, wherein the switching element The source is disposed on a corresponding side of the first portion of the data line. The pixel array structure of claim 1, wherein the source of the switching element is disposed on the same side of the second portion of the data line. The pixel array structure of claim 6, wherein the source of the switching element is located in the middle portion of the first portion of the data line and is electrically connected. The pixel array structure of claim 7, wherein the source of the switching element is located at a near end of the second portion of the data line and is electrically connected.