TWI406561B - Video processor and its automatic selection filter of the video filter driver - Google Patents
Video processor and its automatic selection filter of the video filter driver Download PDFInfo
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本發明是有關於一種驅動裝置,特別是指一種能自動偵測格式並依據格式自動切換濾波器的視訊濾波器驅動裝置。The invention relates to a driving device, in particular to a video filter driving device capable of automatically detecting a format and automatically switching a filter according to a format.
隨著時代追求高畫質的腳步,高品質的原影原音重現是人類對於視聽感官的終極需求,故視訊處理技術已由以往的類比(analog)技術發展到目前的數位(digital)技術。並且,在視訊信號格式方面,也由標準畫質(Standard-Definition,簡稱SD)發展到高畫質(High Definition,簡稱HD),其中標準畫質(SD)的視訊信號格式包含有複合(Composite)信號、S-Video(Y/C)信號等,而高畫質(HD)的視訊信號格式包含有DVI以及HDMI等。不過,目前大眾所使用的電視機(TV)與播放器(Player)不一定能支援高畫質的視訊信號格式,所以現有的電視機或是播放器(player)在設計上就必需考量到如何處理各式的視訊信號格式及向下兼容的彈性。With the pursuit of high image quality in the era, high-quality original sound reproduction is the ultimate demand for human visual sense. Therefore, video processing technology has evolved from the analog technology to the current digital technology. Moreover, in terms of video signal format, it is also developed from Standard-Definition (SD) to High Definition (HD), in which the standard image quality (SD) video signal format contains composite (Composite). ) Signals, S-Video (Y/C) signals, etc., and high-definition (HD) video signal formats include DVI and HDMI. However, the TV (TV) and player (Player) currently used by the public do not necessarily support high-definition video signal formats, so existing TVs or players must be designed. Handle various video signal formats and backward compatibility.
參閱圖1,針對電視與播放器的主要晶片(Main chip)1而言,為了滿足各式的視訊信號格式,就必需同時支援各種畫質解析度的格式才能確保實際應用於產品的彈性及相容性。目前普遍的視訊信號格式包括SD視訊信號的CVBS+S-Video(Y/C)以及HD視訊信號格式的R/G/B或Y/Pb/Pr,而在主要晶片(Main chip)1內部的視訊解碼器(video decoder)11是以數位資料的形態經過數位類比轉換器(DAC)12合成類比的視訊信號輸出,所以在視訊信號輸出方面,為了可以輸出目前普遍使用的視訊信號格式,主要晶片(Main chip)1的視訊解碼器11需同時搭配六組數位類比轉換器(DAC)12,並且外部的視訊濾波器驅動裝置(Video Filter Driver)2則必需具有六個分別連接各個數位類比轉換器12的視訊信號濾波單元,而且,由於SD視訊信號格式與HD視訊信號所需的視訊信號濾波單元不同,所以視訊信號濾波單元分為接受CVBS、Y、C輸入的SD視訊信號濾波單元21,以及接受R/G/B或Y/Pb/Pr輸入的HD視訊信號濾波單元22。Referring to FIG. 1, for the main chip 1 of the television and the player, in order to satisfy various video signal formats, it is necessary to simultaneously support various image resolution formats to ensure the elasticity and phase of the actual application. Capacitance. The current common video signal formats include CVBS+S-Video (Y/C) for SD video signals and R/G/B or Y/Pb/Pr for HD video signal formats, and are internal to Main chip 1. The video decoder 11 synthesizes an analog video signal output through a digital analog converter (DAC) 12 in the form of digital data. Therefore, in terms of video signal output, in order to output the currently widely used video signal format, the main chip The video decoder 11 of (Main chip) 1 needs to be equipped with six sets of digital analog converters (DACs) 12 at the same time, and the external video filter driver (Video Filter Driver) 2 must have six separate analog converters for each digital bit. 12 video signal filtering unit, and since the SD video signal format is different from the video signal filtering unit required for the HD video signal, the video signal filtering unit is divided into an SD video signal filtering unit 21 that accepts CVBS, Y, C inputs, and The HD video signal filtering unit 22 that accepts the R/G/B or Y/Pb/Pr input.
進一步說明,參閱圖2,SD視訊信號濾波單元21具有一直流箝位電路(DC Clamping)211、一類比頻寬(analog bandwidth)為9MHz的低通濾波器(LPF)212及一6dB的增益模組213。而參閱圖3,HD視訊信號濾波單元22具有一直流箝位電路(DC Clamping)221、一類比頻寬(analog bandwidth)為36MHz的低通濾波器(LPF)222及一6dB的增益模組223。相較之下,SD視訊信號濾波單元21與HD視訊信號濾波單元22的差異,僅在於兩者的低通濾波器的頻率截止點不同(即頻寬不同),但也因此差異造成電視與播放器的成本增加與空間上的浪費。舉例來說,若輸出的視訊信號為CVBS+S-Video(Y/C),實際上同一時間只利用到三個數位類比轉換器12與三個SD視訊信號濾波單元21。反之,若輸出的視訊信號為R/G/B,實際上同一時間也是只利用到三個數位類比轉換器12與三個HD視訊信號濾波單元22,這代表著不管輸出的視訊信號格式為SD或HD都會有三個數位類比轉換器12與三個視訊信號濾波單元未被使用到。Further, referring to FIG. 2, the SD video signal filtering unit 21 has a DC Clamping 211, a low-pass filter (LPF) 212 with an analog bandwidth of 9 MHz, and a 6 dB gain mode. Group 213. Referring to FIG. 3, the HD video signal filtering unit 22 has a DC Clamping 221, a low-pass filter (LPF) 222 having an analog bandwidth of 36 MHz, and a 6 dB gain module 223. . In contrast, the difference between the SD video signal filtering unit 21 and the HD video signal filtering unit 22 is only that the frequency cutoff points of the low pass filters of the two are different (that is, the bandwidth is different), but the difference is caused by the television and the playback. The cost of the device increases and the space is wasted. For example, if the output video signal is CVBS+S-Video(Y/C), only three digital analog converters 12 and three SD video signal filtering units 21 are actually used at the same time. On the other hand, if the output video signal is R/G/B, only three digital analog converters 12 and three HD video signal filtering units 22 are actually used at the same time, which means that the video signal format of the output is SD. Or HD will have three digital analog converters 12 and three video signal filtering units not used.
有鑑於此,若能將SD視訊信號濾波單元21與HD視訊信號濾波單元22加以整合,將可有效地降地電視與播放器之主要晶片與視訊濾波器驅動裝置的成本與空間,故為本案欲解決的方向。In view of this, if the SD video signal filtering unit 21 and the HD video signal filtering unit 22 can be integrated, the cost and space of the main chip and the video filter driving device of the TV and the player can be effectively reduced. The direction to be solved.
因此,本發明之目的,即在提供一種自動選擇濾波器的視訊濾波器驅動裝置。Accordingly, it is an object of the present invention to provide a video filter driving apparatus that automatically selects a filter.
於是,本發明視訊濾波器驅動裝置,可接收一第一視訊信號,並包含一信號格式判斷單元及一第一視訊信號濾波單元。信號格式判斷單元接收該第一視訊信號,並包括一同步信號分離模組及一頻率偵測模組。同步信號分離模組由該第一視訊信號中分離出一同步信號成分;頻率偵測模組耦接該同步信號分離模組並接收該同步信號成分,該頻率偵測模組用以偵測出該同步信號成分的頻率為一第一頻率或是一第二頻率,並發出一控制信號。第一視訊信號濾波單元包括一濾波器組及一切換開關。濾波器組具有一第一濾波器及一第二濾波器;切換開關耦接該頻率偵測模組與該濾波器組,並且接收該第一視訊信號與該控制信號,該切換開關依據該控制信號控制該第一視訊信號輸入該第一濾波器或該第二濾波器其中之一,使對該第一視訊信號進行濾波。Therefore, the video filter driving device of the present invention can receive a first video signal, and includes a signal format determining unit and a first video signal filtering unit. The signal format determining unit receives the first video signal, and includes a synchronization signal separation module and a frequency detection module. The synchronization signal separation module separates a synchronization signal component from the first video signal; the frequency detection module is coupled to the synchronization signal separation module and receives the synchronization signal component, and the frequency detection module is configured to detect The frequency of the synchronization signal component is a first frequency or a second frequency, and a control signal is issued. The first video signal filtering unit includes a filter bank and a switch. The filter bank has a first filter and a second filter; the switch is coupled to the frequency detection module and the filter bank, and receives the first video signal and the control signal, and the switch is controlled according to the control The signal controls the first video signal to be input to one of the first filter or the second filter to filter the first video signal.
較佳地,該同步信號成分為水平同步信號。Preferably, the synchronization signal component is a horizontal synchronization signal.
較佳地,該信號格式判斷單元還包括一用以分離出該視訊信號中之亮度信號且耦接該同步信號分離模組的亮度色度分離模組,並且該第一視訊信號通過該同步信號分離模組前,會先通過該亮度色度分離模組。Preferably, the signal format determining unit further includes a luminance chrominance separation module configured to separate the luminance signal in the video signal and coupled to the synchronization signal separation module, and the first video signal passes the synchronization signal Before the module is separated, the brightness chroma separation module is first passed.
較佳地,當該頻率偵測模組偵測出該同步信號成分的頻率為該第一頻率時,該控制信號為低電位的信號,並且該切換開關控制該第一視訊信號輸入該第一濾波器進行濾波;當該頻率偵測模組偵測出該同步信號成分的頻率為該第二頻率時,該控制信號為高電位的信號,並且該切換開關控制該第一視訊信號輸入該第二濾波器進行濾波。Preferably, when the frequency detecting module detects that the frequency of the synchronization signal component is the first frequency, the control signal is a low potential signal, and the switching switch controls the first video signal input to the first The filter performs filtering; when the frequency detecting module detects that the frequency of the synchronization signal component is the second frequency, the control signal is a high potential signal, and the switching switch controls the first video signal input to the first The second filter performs filtering.
較佳地,該視訊濾波器驅動裝置還包含一用以處理一第二視訊信號的第二視訊信號濾波單元,該第二視訊信號濾波單元包括該濾波器組及該切換開關,該切換開關耦接該頻率偵測模組與該濾波器組,並且接收該第二視訊信號與該控制信號,該切換開關依據該控制信號控制該第二視訊信號輸入該第一濾波器或該第二濾波器其中之一,使對該第二視訊信號進行濾波。另外,該視訊濾波器驅動裝置還包含一用以處理一第三視訊信號的第三視訊信號濾波單元,該第三視訊信號濾波單元包括該濾波器組及該切換開關,該切換開關耦接該頻率偵測模組與該濾波器組,並且接收該第三視訊信號與該控制信號,該切換開關依據該控制信號控制該第三視訊信號輸入該第一濾波器與該第二濾波器其中之一,使對該第三視訊信號進行濾波。Preferably, the video filter driving device further includes a second video signal filtering unit for processing a second video signal, the second video signal filtering unit includes the filter group and the switching switch, and the switching switch is coupled. Connecting the frequency detecting module and the filter bank, and receiving the second video signal and the control signal, the switching switch controls the second video signal to input the first filter or the second filter according to the control signal One of them filters the second video signal. In addition, the video filter driving device further includes a third video signal filtering unit for processing a third video signal, the third video signal filtering unit includes the filter group and the switching switch, and the switching switch is coupled to the a frequency detecting module and the filter group, and receiving the third video signal and the control signal, wherein the switching switch controls the third video signal to input the first filter and the second filter according to the control signal First, filtering the third video signal.
再者,該第一視訊信號濾波單元、該第二視訊信號濾波單元與該第三視訊信號信號濾波單元分別還包括一耦接該濾波器組且用以提高濾波後的視訊信號之強度的增益模組。並且,該第一視訊信號濾波單元、該第二視訊信號濾波單元與該第三視訊信號信號濾波單元分別還包括一直流箝位電路,以將信號箝位在一直流位準作為後端線路的信號截取參考電壓。Furthermore, the first video signal filtering unit, the second video signal filtering unit and the third video signal filtering unit respectively comprise a gain coupled to the filter group for increasing the intensity of the filtered video signal. Module. And the first video signal filtering unit, the second video signal filtering unit and the third video signal filtering unit respectively comprise a DC clamp circuit for clamping the signal to a DC level as a back-end line. The signal intercepts the reference voltage.
較佳地,該第一頻率為標準畫質視訊信號中的水平同步信號的頻率,該第二頻率為高畫質視訊信號中的水平同步信號的頻率。Preferably, the first frequency is a frequency of a horizontal synchronization signal in a standard image quality video signal, and the second frequency is a frequency of a horizontal synchronization signal in the high quality video signal.
另外,本發明之另一目的,在於提供一種具有上述視訊濾波器驅動裝置且節省成本與空間的視訊處理器。Further, another object of the present invention is to provide a video processor having the above-described video filter driving device and which is cost-effective and space-saving.
本發明之功效在於,藉由信號格式判斷單元判斷出第一視訊信號的視訊信號格式,並且,第一視訊信號濾波單元、第二視訊信號濾波單與第三視訊信號濾波單元依據頻率偵測模組所發出的控制信號切換使用不同的濾波器,藉此將不同頻寬的第一濾波器與第二濾波器整合於同一個視訊信號濾波單元內,再者,主要晶片相對應地僅需設置三個數位類比轉換器,相較於習知確實節省了視訊處理器的成本與空間。The method of the present invention is to determine the video signal format of the first video signal by the signal format determining unit, and the first video signal filtering unit, the second video signal filtering unit and the third video signal filtering unit are based on the frequency detecting mode. The control signal sent by the group switches using different filters, thereby integrating the first filter and the second filter of different bandwidths into the same video signal filtering unit. Furthermore, the main chip only needs to be set correspondingly. The three digital analog converters save the cost and space of the video processor compared to conventional ones.
有關本發明之前述及其他技術內容、特點與功效,在以下配合參考圖式之一個較佳實施例的詳細說明中,將可清楚的呈現。The above and other technical contents, features and advantages of the present invention will be apparent from the following detailed description of the preferred embodiments.
參閱圖4,為本發明視訊處理器的較佳實施例。視訊處理器(Video Processor)適合用於電視機(TV)或播放器(Player),並具有一主要晶片(Main chip)4及一視訊濾波器驅動裝置(Video Filter Driver)5,視訊濾波器驅動裝置5用以與主要晶片4搭配作用。主要晶片4具有一視訊解碼器(video decoder)41以及連接視訊解碼器41的一第一數位類比轉換器(DAC)421、一第二數位類比轉換器(DAC)422及一第三數位類比轉換器(DAC)423。視訊解碼器41是以數位資料的形態處理視訊信號,而所述的數位類比轉換器421、422、423用以將視訊解碼器41輸出的數位資料轉換成類比視訊信號(analog video signal)。並且,由圖4可得知所述的數位類比轉換器421、422、423輸出的視訊信號格式可為一組標準畫質(簡稱SD)視訊信號的CVBS、Y及C,或是一組高畫質(簡稱HD)視訊信號的Y、Pb、Pr,或是一組SD/HD視訊信號的G、B、R。為了以下說明,定義第一數位類比轉換器421所輸出的信號為第一視訊信號S1,如CVBS或Y或G;定義第二數位類比轉換器422所輸出的信號為第二視訊信號S2,如Y或Pb或B;定義第三數位類比轉換器423所輸出的信號為第三視訊信號S3,如C或Pr或R。Referring to FIG. 4, a preferred embodiment of the video processor of the present invention is shown. The video processor is suitable for a television (TV) or a player (Player), and has a main chip 4 and a video filter driver 5, and a video filter driver. The device 5 serves to cooperate with the main wafer 4. The main chip 4 has a video decoder 41 and a first digital analog converter (DAC) 421 connected to the video decoder 41, a second digital analog converter (DAC) 422 and a third digital analog conversion. (DAC) 423. The video decoder 41 processes the video signal in the form of digital data, and the digital analog converters 421, 422, and 423 are used to convert the digital data output by the video decoder 41 into an analog video signal. Moreover, it can be seen from FIG. 4 that the video signal format output by the digital analog converters 421, 422, and 423 can be a set of standard picture quality (SD) video signals CVBS, Y, and C, or a group of high. Image quality (referred to as HD) video signal Y, Pb, Pr, or a set of SD / HD video signal G, B, R. For the following description, the signal output by the first digital analog converter 421 is defined as the first video signal S1, such as CVBS or Y or G; and the signal output by the second digital analog converter 422 is defined as the second video signal S2, such as Y or Pb or B; the signal output by the third digital analog converter 423 is defined as a third video signal S3, such as C or Pr or R.
繼續參閱圖4,視訊濾波器驅動裝置5包含一信號格式判斷單元50、一連接第一數位類比轉換器421的第一視訊信號濾波單元51、一連接第二數位類比轉換器422的第二視訊信號濾波單元52,以及一連接第三數位類比轉換器423的第三視訊信號濾波單元53,其中,第一視訊信號濾波單元51接收第一視訊信號S1,第二視訊信號濾波單元52接收第二視訊信號S2,第三視訊信號濾波單元53接收第三視訊信號S3,並且上述的視訊信號濾波單元51~53的構造相同,僅在於接收的視訊信號不同。再者,每一視訊信號濾波單元51~53外部連接一電阻9以供與後端線路做阻抗匹配。Referring to FIG. 4, the video filter driving device 5 includes a signal format determining unit 50, a first video signal filtering unit 51 connected to the first digital analog converter 421, and a second video connected to the second digital analog converter 422. a signal filtering unit 52, and a third video signal filtering unit 53 connected to the third digital analog converter 423, wherein the first video signal filtering unit 51 receives the first video signal S1, and the second video signal filtering unit 52 receives the second The video signal S2, the third video signal filtering unit 53 receives the third video signal S3, and the above-described video signal filtering units 51-53 have the same configuration except that the received video signals are different. Furthermore, each of the video signal filtering units 51-53 is externally connected with a resistor 9 for impedance matching with the back-end line.
在此先行說明本實施例的特點在於,利用SD視訊信號與HD視訊信號中的同步信號之水平同步信號(Horizontal sync signal)的頻率不同來選擇視訊信號的濾波器頻寬。進一步說明,SD視訊信號中的同步信號之水平同步信號的頻率為15KHz,而HD視訊信號中的同步信號之水平同步信號的頻率為45KHz,因此,本實施例利用SD視訊信號與HD視訊信號兩者的水平同步信號的頻率不同來判斷視訊信號格式為SD或HD,並藉此選擇適合的濾波器,詳細說明如下。First, the present embodiment is characterized in that the filter bandwidth of the video signal is selected by using the SD video signal and the frequency of the horizontal sync signal of the synchronization signal in the HD video signal. Further, the frequency of the horizontal synchronization signal of the synchronization signal in the SD video signal is 15 kHz, and the frequency of the horizontal synchronization signal of the synchronization signal in the HD video signal is 45 kHz. Therefore, the present embodiment uses the SD video signal and the HD video signal. The frequency of the horizontal synchronizing signal is different to judge whether the video signal format is SD or HD, and thereby select a suitable filter, which is described in detail below.
參閱圖5,視訊濾波器驅動裝置5的信號格式判斷單元50包括依序設置的一接收第一視訊信號S1的亮度色度分離(Y/C separation)模組501、一耦接亮度色度分離模組501的同步信號分離(Sync signal separation)模組502、一耦接同步信號分離模組502的頻率偵測(Frequency detection)模組503及一耦接頻率偵測模組503的位準移位(Level shift)模組504,並且上述的各模組係以電路(circuit)來實現。另外,需說明的是,由於第一視訊信號S1(CVBS或Y或G)中包含有同步信號,故藉一緩衝器(圖未示)將第一數位類比轉換器421所輸出的第一視訊信號S1分為兩路分別輸入信號格式判斷單元50與第一視訊信號濾波單元51。Referring to FIG. 5, the signal format determining unit 50 of the video filter driving device 5 includes a chrominance chroma separation (Y/C separation) module 501 for receiving the first video signal S1, and a coupling luminance chromaticity separation. The Sync signal separation module 502 of the module 501, the frequency detection module 503 coupled to the synchronization signal separation module 502, and the level shift of the coupled frequency detection module 503 A level shift module 504, and each of the above modules is implemented by a circuit. In addition, it should be noted that, since the first video signal S1 (CVBS or Y or G) includes a synchronization signal, the first video output by the first digital analog converter 421 is buffered by a buffer (not shown). The signal S1 is divided into two separate input signal format determining units 50 and a first video signal filtering unit 51.
亮度色度分離模組501接收第一視訊信號S1且用以分離出第一視訊信號S1(如CVBS)中之亮度信號(Y),但也會因視訊信號的不同而不作用,舉例來說,若輸入的第一視訊信號S1為Y或G,則亮度色度分離模組501不作用。接著,同步信號分離模組502用以將第一視訊信號S1中的同步信號分離出一同步信號成分(若第一視訊信號S1為CVBS,則輸入同步信號分離模組502的信號為亮度信號),在本實施例中,該同步信號成分為水平同步信號。此外,亦可在同步信號分離模組502內增設一電容,以使輸出的水平同步信號變形,以便頻率偵測模組503更易於辨識出水平同步信號的頻率。The luminance chroma separation module 501 receives the first video signal S1 and separates the luminance signal (Y) in the first video signal S1 (such as CVBS), but also does not function due to the difference of the video signal. For example, If the input first video signal S1 is Y or G, the luminance chrominance separation module 501 does not function. Then, the synchronization signal separation module 502 is configured to separate the synchronization signal in the first video signal S1 into a synchronization signal component (if the first video signal S1 is CVBS, the signal input to the synchronization signal separation module 502 is a luminance signal) In this embodiment, the synchronization signal component is a horizontal synchronization signal. In addition, a capacitor may be added in the synchronization signal separation module 502 to deform the output horizontal synchronization signal, so that the frequency detection module 503 can more easily recognize the frequency of the horizontal synchronization signal.
頻率偵測模組503接收水平同步信號,並且偵測出該水平同步信號的頻率為一SD視訊信號格式的第一頻率(15KHz),或是一HD視訊信號格式的第二頻率(45KHz),並發出一控制所述視訊信號濾波單元51~53的控制信號CS。在本實施例中,頻率偵測模組503在偵測出該水平同步信號的頻率為第一頻率時,使所發出的控制訊號為低電位;頻率偵測模組503在偵測出該水平同步信號的頻率為第二頻率時,使所發出的控制訊號為高電位,藉此,控制信號CS為高電位時,表示輸入的視訊信號格式為SD;控制信號CS為低電位時,表示輸入的視訊信號格式為HD。而位準移位模組504的功用容後再述。The frequency detecting module 503 receives the horizontal synchronization signal, and detects that the frequency of the horizontal synchronization signal is a first frequency (15 kHz) of an SD video signal format, or a second frequency (45 kHz) of an HD video signal format. And a control signal CS for controlling the video signal filtering units 51-53 is issued. In this embodiment, the frequency detecting module 503 detects that the horizontal control signal is at the first frequency, and causes the generated control signal to be low; the frequency detecting module 503 detects the level. When the frequency of the synchronization signal is the second frequency, the issued control signal is at a high potential, whereby when the control signal CS is at a high potential, the input video signal format is SD; when the control signal CS is at a low potential, the input is indicated. The video signal format is HD. The function of the level shift module 504 will be described later.
接著先以視訊濾波器驅動裝置5的第一視訊信號濾波單元51做說明,並繼續參閱圖5,第一視訊信號濾波單元51包括一耦接第一數位類比轉換器421的直流箝位電路(DC Clamping)601、一耦接直流箝位電路601的切換開關(Switch)602、一耦接切換開關602的濾波器組603及一耦接濾波器組603的增益(Gain up)模組604,並且上述的模組係以電路(circuit)來實現。直流箝位電路601用以將信號箝位在一直流位準作為後端線路的信號截取參考電壓。濾波器組603具有一適於過濾SD視訊信號的第一濾波器61及一適於過濾HD視訊信號的第二濾波器62,所述的濾波器用以將通過的視訊信號(第一視訊信號S1)的雜訊去除,並且,在本實施例中,第一濾波器為頻寬9MHz的低通濾波器(LPF),第二濾波器為頻寬36MHz的低通濾波器(LPF)。切換開關602接收來自信號格式判斷單元50的控制信號CS以選擇切換至濾波器組603內適用的濾波器。在本實施例中,切換開關602為一數位開關,於是,當控制信號CS為低電位(即表示第一視訊信號S1為SD格式)時,切換開關602切換至適於SD視訊信號的第一濾波器61;當控制信號CS為高電位(即表示第一視訊信號S1為HD格式)時,切換開關602切換至適於HD視訊信號的第二濾波器62。進一步說明的是,該位準位移模組504用以調整控制信號CS的電位,以使控制信號CS的高電位與低電位合乎切換開關602的切換標準。而且,經過濾波的第一視訊信號S1會通過增益模組604以增加其信號強度約6db,以做為阻抗匹配使用(如電視機輸入阻抗為75 ohm),但並不以此為限。The first video signal filtering unit 51 of the video filter driving device 5 is first described. Referring to FIG. 5, the first video signal filtering unit 51 includes a DC clamping circuit coupled to the first digital analog converter 421. DC Clamping 601, a switch 602 coupled to the DC clamp circuit 601, a filter bank 603 coupled to the switch 602, and a Gain up module 604 coupled to the filter bank 603, And the above modules are implemented by circuits. The DC clamp circuit 601 is used to clamp the signal to a DC level as a signal for the back-end line to intercept the reference voltage. The filter bank 603 has a first filter 61 adapted to filter the SD video signal and a second filter 62 adapted to filter the HD video signal, the filter for passing the video signal (the first video signal S1) The noise is removed, and, in the present embodiment, the first filter is a low pass filter (LPF) having a bandwidth of 9 MHz, and the second filter is a low pass filter (LPF) having a bandwidth of 36 MHz. The changeover switch 602 receives the control signal CS from the signal format determination unit 50 to selectively switch to a suitable filter within the filter bank 603. In this embodiment, the switch 602 is a digital switch. When the control signal CS is low (that is, the first video signal S1 is in the SD format), the switch 602 is switched to the first suitable for the SD video signal. The filter 61; when the control signal CS is high (that is, the first video signal S1 is in the HD format), the switch 602 is switched to the second filter 62 suitable for the HD video signal. It is further noted that the level displacement module 504 is configured to adjust the potential of the control signal CS such that the high potential and the low potential of the control signal CS meet the switching criteria of the switch 602. Moreover, the filtered first video signal S1 is passed through the gain module 604 to increase its signal strength by about 6 db for impedance matching (eg, the TV input impedance is 75 ohm), but is not limited thereto.
參閱圖6,第二視訊信號濾波單元52與第一視訊信號濾波單元51的差異在於,第二視訊信號濾波單元52的直流箝位電路601是接收第二視訊信號S2,其餘構造與功用相同,故不多加贅述。參閱圖7,第三視訊信號濾波單元53與第一視訊信號濾波單元52的差異在於,第三視訊信號濾波單元53的直流箝位電路601是接收第三視訊信號S3,其餘構造與功用相同,故不多加贅述。Referring to FIG. 6, the difference between the second video signal filtering unit 52 and the first video signal filtering unit 51 is that the DC clamp circuit 601 of the second video signal filtering unit 52 receives the second video signal S2, and the rest of the configuration is the same as the function. Therefore, do not add more details. Referring to FIG. 7, the difference between the third video signal filtering unit 53 and the first video signal filtering unit 52 is that the DC clamp circuit 601 of the third video signal filtering unit 53 receives the third video signal S3, and the rest of the configuration is the same as the function. Therefore, do not add more details.
整體來說,若主要晶片4輸出的第一視訊信號S1、第二視訊信號S2、第三視訊信號S3的視訊信號格式為SD,則信號格式判斷單元50的頻率偵測模組503偵測出第一視訊信號S1中水平同步信號的頻率為第一頻率(15KHz),並且使發出的控制信號CS為低電位,於是,第一視訊信號濾波單元51、第二視訊信號濾波單元52與第三視訊信號濾波單元53的切換開關602會依控制信號CS切換使用第一濾波器61,以供SD視訊信號進行濾波。另一方面,若主要晶片4輸出的第一視訊信號S1、第二視訊信號S2、第三視訊信號S3的視訊信號格式為HD,則信號格式判斷單元50的頻率偵測模組503偵測出第一視訊信號S1中水平同步信號的頻率為第二頻率(45KHz),並且使發出的控制信號CS為高電位,於是,第一視訊信號濾波單元51、第二視訊信號濾波單元52與第三視訊信號濾波單元53的切換開關602會依控制信號CS切換使用第二濾波器62,以供SD視訊信號進行濾波。如此一來,本實施例的主要晶片4僅需要三組數位類比轉換器,以及視訊濾波器驅動裝置5僅需要三組視訊信號濾波單元,相較於習知確實節省了視訊處理器的成本與空間。In general, if the video signal format of the first video signal S1, the second video signal S2, and the third video signal S3 outputted by the main chip 4 is SD, the frequency detecting module 503 of the signal format determining unit 50 detects The frequency of the horizontal synchronizing signal in the first video signal S1 is the first frequency (15 KHz), and the issued control signal CS is low, so that the first video signal filtering unit 51, the second video signal filtering unit 52 and the third The switch 602 of the video signal filtering unit 53 switches the first filter 61 according to the control signal CS for filtering the SD video signal. On the other hand, if the video signal format of the first video signal S1, the second video signal S2, and the third video signal S3 outputted by the main chip 4 is HD, the frequency detecting module 503 of the signal format determining unit 50 detects The frequency of the horizontal synchronizing signal in the first video signal S1 is the second frequency (45 KHz), and the issued control signal CS is at a high potential, so that the first video signal filtering unit 51, the second video signal filtering unit 52 and the third The switch 602 of the video signal filtering unit 53 switches the second filter 62 according to the control signal CS for filtering the SD video signal. Therefore, the main chip 4 of the embodiment only needs three sets of digital analog converters, and the video filter driving device 5 only needs three sets of video signal filtering units, which saves the cost of the video processor compared with the conventional one. space.
附帶說明的是,參閱圖8,為顯示於電視或播放器之顯示螢幕的一使用介面900。使用者可藉由使用介面900選擇主要晶片4所輸出的視訊信號,以滿足所需的視覺感受。舉例來說,若使用者欲觀看HD視訊信號格式的影像,則透過一遙控器在使用介面900上進行點選,使主要晶片4的各數位類比轉換器421、422、423輸出Y、Pb、Pr或G、B、R至視訊濾波器驅動裝置5的第一視訊信號濾波單元51、第二視訊信號濾波單元52與第三視訊信號濾波單元53,再藉由第一視訊信號濾波單元51、第二視訊信號濾波單元52與第三視訊信號濾波單元53輸出Y、Pb、Pr或G、B、R至顯示螢幕,如此一來,使用者便可觀看到所需的畫面品質。Incidentally, referring to FIG. 8, a usage interface 900 is displayed on a display screen of a television or a player. The user can select the video signal output by the main wafer 4 by using the interface 900 to meet the desired visual experience. For example, if the user wants to view the image in the HD video signal format, the user can select the Y, Pb, and the digital analog converters 421, 422, and 423 of the main chip 4 by using a remote controller. Pr or G, B, R to the first video signal filtering unit 51, the second video signal filtering unit 52 and the third video signal filtering unit 53 of the video filter driving device 5, and then by the first video signal filtering unit 51, The second video signal filtering unit 52 and the third video signal filtering unit 53 output Y, Pb, Pr or G, B, R to the display screen, so that the user can view the desired picture quality.
綜上所述,本實施例的視訊濾波器驅動裝置5藉由信號格式判斷單元50判斷出第一視訊信號S1的視訊信號格式,並且,第一視訊信號濾波單元51、第二視訊信號濾波單元52與第三視訊信號濾波單元53依據頻率偵測模組503所發出的控制信號CS切換使用不同的濾波器,藉此將不同頻寬的第一濾波器61與第二濾波器62整合於同一個視訊信號濾波單元內,再者,主要晶片4相對應地僅需設置三個數位類比轉換器421、422、423,相較於習知確實節省了視訊處理器的成本與空間,故確實能達成本發明之目的。In summary, the video filter driving device 5 of the present embodiment determines the video signal format of the first video signal S1 by the signal format determining unit 50, and the first video signal filtering unit 51 and the second video signal filtering unit. 52 and the third video signal filtering unit 53 switch different control filters according to the control signal CS sent by the frequency detecting module 503, thereby integrating the first filter 61 and the second filter 62 of different bandwidths. In a video signal filtering unit, in addition, the main chip 4 only needs to set three digital analog converters 421, 422, and 423 correspondingly, which saves the cost and space of the video processor compared with the conventional one. The object of the invention is achieved.
惟以上所述者,僅為本發明之較佳實施例而已,泛指針對應用不同視訊格式之水平同步信號偵測而達到相對應的濾波器自動調整,當不能以此限定本發明實施之範圍,即大凡依本發明申請專利範圍及發明說明內容所作之簡單的等效變化與修飾,皆仍屬本發明專利涵蓋之範圍內。However, the above description is only a preferred embodiment of the present invention. The universal pointer automatically detects the corresponding horizontal synchronization signal detection using different video formats, and cannot limit the scope of implementation of the present invention. The simple equivalent changes and modifications made by the present invention in the scope of the invention and the scope of the invention are still within the scope of the invention.
4...主要晶片4. . . Main wafer
41...視訊解碼器41. . . Video decoder
421...第一數位類比轉換器421. . . First digital analog converter
422...第二數位類比轉換器422. . . Second digital analog converter
423...第三數位類比轉換器423. . . Third digit analog converter
5...視訊濾波器驅動裝置5. . . Video filter driver
50...信號格式判斷單元50. . . Signal format judgment unit
501...亮度色度分離模組501. . . Luminance chroma separation module
502...同步信號分離模組502. . . Synchronization signal separation module
503...頻率偵測模組503. . . Frequency detection module
504...位準移位模組504. . . Level shift module
51...第一視訊信號濾波單元51. . . First video signal filtering unit
52...第二視訊信號濾波單元52. . . Second video signal filtering unit
53...第三視訊信號濾波單元53. . . Third video signal filtering unit
601...直流箝位電路601. . . DC clamp circuit
602...切換開關602. . . Toggle switch
603...濾波器組603. . . Filter bank
604...增益模組604. . . Gain module
61...第一濾波器61. . . First filter
62...第二濾波器62. . . Second filter
900...使用介面900. . . Use interface
9...電阻9. . . resistance
S1...第一視訊信號S1. . . First video signal
S2...第二視訊信號S2. . . Second video signal
S3...第三視訊信號S3. . . Third video signal
CS...控制信號CS. . . control signal
圖1是一方塊圖,說明習知的主要晶片與視訊濾波器驅動裝置;Figure 1 is a block diagram showing a conventional main chip and video filter driving device;
圖2是一方塊圖,說明該視訊濾波器驅動裝置的SD視訊信號濾波單元;2 is a block diagram showing an SD video signal filtering unit of the video filter driving device;
圖3是一方塊圖,說明該視訊濾波器驅動裝置的HD視訊信號濾波單元;3 is a block diagram showing the HD video signal filtering unit of the video filter driving device;
圖4是一方塊圖,說明本發明視訊處理器的主要晶片與視訊濾波器驅動裝置;4 is a block diagram showing the main chip and video filter driving device of the video processor of the present invention;
圖5是一方塊圖,說明該視訊濾波器驅動裝置的信號格式判斷單元與第一視訊信號濾波單元;Figure 5 is a block diagram showing the signal format determining unit and the first video signal filtering unit of the video filter driving device;
圖6是一方塊圖,說明該視訊濾波器驅動裝置的第二視訊信號濾波單元;Figure 6 is a block diagram showing the second video signal filtering unit of the video filter driving device;
圖7一方塊圖,是說明該視訊濾波器驅動裝置的第三視訊信號濾波單元;及Figure 7 is a block diagram showing a third video signal filtering unit of the video filter driving device; and
圖8是一示意圖,說明電視或播放器的使用介面。Figure 8 is a schematic diagram showing the use interface of a television or player.
4...主要晶片4. . . Main wafer
41...視訊解碼器41. . . Video decoder
421...第一數位類比轉換器421. . . First digital analog converter
422...第二數位類比轉換器422. . . Second digital analog converter
423...第三數位類比轉換器423. . . Third digit analog converter
5...視訊濾波器驅動裝置5. . . Video filter driver
50...信號格式判斷單元50. . . Signal format judgment unit
51...第一視訊信號濾波單元51. . . First video signal filtering unit
52...第二視訊信號濾波單元52. . . Second video signal filtering unit
53...第三視訊信號濾波單元53. . . Third video signal filtering unit
9...電阻9. . . resistance
S1...第一視訊信號S1. . . First video signal
S2...第二視訊信號S2. . . Second video signal
S3...第三視訊信號S3. . . Third video signal
CS...控制信號CS. . . control signal
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TW099124720A TWI406561B (en) | 2010-07-27 | 2010-07-27 | Video processor and its automatic selection filter of the video filter driver |
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TW099124720A TWI406561B (en) | 2010-07-27 | 2010-07-27 | Video processor and its automatic selection filter of the video filter driver |
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TW201206174A TW201206174A (en) | 2012-02-01 |
TWI406561B true TWI406561B (en) | 2013-08-21 |
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TWI581640B (en) * | 2014-09-09 | 2017-05-01 | 鴻海精密工業股份有限公司 | Signal synthesis circuit |
Citations (6)
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CN1220800A (en) * | 1997-03-12 | 1999-06-23 | 松下电器产业株式会社 | MPEG decoder providing multiple standard output signals |
EP0707426B1 (en) * | 1994-10-11 | 2003-01-08 | Hitachi, Ltd. | Digital video decoder for decoding digital high definition and/or digital standard definition television signals |
US20050028220A1 (en) * | 2003-03-04 | 2005-02-03 | Broadcom Corporation | Television functionality on a chip |
TWI248314B (en) * | 2003-03-04 | 2006-01-21 | Sony Corp | Image signal processing circuit and image signal processing method |
TW200835334A (en) * | 2006-10-27 | 2008-08-16 | Broadcom Corp | Automatic format identification of analog video input signals |
TW201002020A (en) * | 2008-06-25 | 2010-01-01 | Realtek Semiconductor Corp | Timing control for multi-channel full-duplex transceiver and thereof method |
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2010
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Patent Citations (6)
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EP0707426B1 (en) * | 1994-10-11 | 2003-01-08 | Hitachi, Ltd. | Digital video decoder for decoding digital high definition and/or digital standard definition television signals |
CN1220800A (en) * | 1997-03-12 | 1999-06-23 | 松下电器产业株式会社 | MPEG decoder providing multiple standard output signals |
US20050028220A1 (en) * | 2003-03-04 | 2005-02-03 | Broadcom Corporation | Television functionality on a chip |
TWI248314B (en) * | 2003-03-04 | 2006-01-21 | Sony Corp | Image signal processing circuit and image signal processing method |
TW200835334A (en) * | 2006-10-27 | 2008-08-16 | Broadcom Corp | Automatic format identification of analog video input signals |
TW201002020A (en) * | 2008-06-25 | 2010-01-01 | Realtek Semiconductor Corp | Timing control for multi-channel full-duplex transceiver and thereof method |
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