TWI401688B - Memory device and method of operating memory - Google Patents

Description

Memory device and method of operating memory

The present invention relates to a memory, and more particularly to a memory device and a method of operating a memory.

A memory is a semiconductor component used to store information or data. As computer microprocessors become more powerful, the programs and operations that are executed by software increase. Therefore, the demand for memory having a high storage capacity is also gradually increasing.

Among various memory products, non-volatile memory allows multiple program programming, reading, and erasing operations, and even in memory. After the power is interrupted, the data stored in it can also be saved. Because of these advantages, non-volatile memory has become a widely used memory in personal computers and electronic devices.

Well-known electrically programmable and erasable non-volatile memory technology such as electrically erasable programmable read-only memory for charge storage structure Memory, EEPROM) and flash memory have been used in a variety of modern applications. The flash memory is designed to have an array of memory cells that can be programmed and read independently. A typical flash memory cell stores charge on a floating gate. The stored charge changes the threshold voltage (Vt) of the memory cell. In a read operation, a read voltage is applied to the gate of the memory cell, regardless of whether the memory cell is turned on (eg, conducting current). Memory cell turn-on indicates the stylized state of the memory cell. For example, a memory cell that conducts current during a read operation can be designated as "1", while a memory cell that does not conduct current during a read operation can be designated as "0". Applying charge to or removing charge from the floating gate to program and erase the memory cell, that is, changing the stored value from "1" to "0" or from "0" to "1" .

Another type of memory is the use of a charge-trapping structure (eg, a layer of non-conducting SiN material) rather than a conductor gate material used in floating gate elements. When the charge trapping memory cells are programmed, the charge is captured and does not move through the non-conductor layer. The charge is retained by the charge trapping layer until the memory cell is erased, maintaining the data state without continuously applying electrical power. The charge trapping memory cell can be manipulated as a two-sided cell. That is, since the charge does not move through the non-conductor charge trapping layer, the charge can be located at a different charge trap.

As the number of memory cells increases, the threshold voltage distribution range of the memory cells becomes larger. Figure 1 and Figure 2 show the critical voltage distribution of a typical 1-megabite memory and a 1-gigabite memory, respectively. These memories have multiple memory cells, and each memory cell can store two bits of data. The horizontal axis represents the threshold voltage of the memory cell, and the vertical axis represents the number of memory cells. The critical voltage distribution of the 1-megabiyte memory includes distribution regions 21 to 24. SW1 is a sensing window located between the high boundary of the distribution area 21 and the low boundary of the distribution area 22. Likewise, SW2 is a sensing window located between distribution areas 22 and 23. SW3 is a sensing window located between the distribution areas 23 and 24. The distribution regions 25 to 28 are the critical voltage distribution regions of the 1-gigabiyte memory. The sensing windows SW4 to SW6 are sensing windows of 1-gigabyte memory. As shown in FIGS. 1 and 2, the range of the distribution regions 25 to 28 is larger than the range of the distribution regions 21 to 24, which causes the sensing windows SW4 to SW6 of the 1-gigabiyte memory to be narrower than the sensing window of the 1-megabiyte memory. SW1 to SW3. Therefore, when the capacity of the memory becomes larger, the difference in the threshold voltage of the memory cell of the memory also becomes larger, and the sensing window of the memory is also narrowed, resulting in the memory cell of the memory when the memory is read. The sensing process of individual states becomes difficult.

Accordingly, the present invention provides a method of operating a memory. After ending the plurality of memory cells of the stylized memory to different levels, the bits of the memory cells can be identified by comparing the threshold voltages of the memory cells having different levels.

The invention further provides a memory device. This memory device has a memory and a controller. The controller programs the plurality of memory cells of the memory to different levels and identifies the bits of the memory cell by comparing the threshold voltages of the memory cells having different levels.

The present invention proposes a method of operating a memory. The memory includes a plurality of memory cells. Each memory cell has a first end and a second end. The method includes: when the first end of the first group of memory cells is at a low threshold voltage level, staging the first end of the first group of memory cells to be higher than the first level; and when the second group is The first end and the second end of the memory cell should be at a high threshold voltage level to program the first end and the second end of the second group of memory cells to be higher than the second level. The first one is below the second level.

The invention further provides a method of operating a memory. The memory includes at least one memory cell. The memory cell has a first end and a second end. The method includes determining whether a threshold voltage of the first end of the memory cell is higher than a first level; determining whether a threshold voltage of the first end of the memory cell is lower than a second level, wherein the first level is lower than the second level And comparing the threshold voltage of the first terminal to the threshold voltage of the second terminal when the threshold voltage of the first terminal is between the first level and the second level.

The invention further provides a memory device comprising a memory and a controller. The memory has a plurality of memory cells. Each memory cell has a first end and a second end. The controller is configured to at least implement the following steps to program the memory cell: when the second end of the memory cell of the first group should be at a low threshold voltage level, the first end of the memory cell of the first group is programmed to be higher than the first a level; and when the first and second ends of the memory cells of the second group are at a high threshold voltage level, the first and second ends of the memory cells of the second group are programmed to be higher than the second level quasi. The first one is below the second level.

The invention further provides a memory device comprising a memory and a controller. The memory has at least one memory cell. The memory cell has a first end and a second end. The controller is configured to: at least perform the following steps to read the memory cell: determine whether the threshold voltage of the first end of the memory cell is higher than the first level; and determine whether the threshold voltage of the first end of the memory cell is lower than the second level, wherein The first bit is lower than the second level; and when the threshold voltage of the first end is between the first level and the second level, the threshold voltage of the first end is compared with the threshold voltage of the second end.

In the embodiment of the present invention, the controller further performs the following steps to program the memory cell: when the threshold voltage of the second end of the memory cell of the first group is higher than the first level, the programming of the first group is stopped. The first end of the memory cell.

In the embodiment of the present invention, the controller further performs the following steps to program the memory cell: when the first end of the memory cell of the third group should be at a low threshold voltage level, the memory of the third group of memory cells is programmed. The second end is above the first level.

In the embodiment of the present invention, before the first end and the second end of the memory cell of the second group are programmed to be higher than the second level, the controller simultaneously programs the first end of the memory cell of the second group. The first end of the memory cell with the second end and the first group is higher than the first level.

In the embodiment of the present invention, the controller further performs the following steps to program the memory cell: finding an upper limit of the first threshold voltage distribution of the memory; and defining the first level to be higher than the upper limit of the first threshold voltage distribution.

In the embodiment of the present invention, the controller further performs the following steps to program the memory cell: finding an upper limit of the second threshold voltage distribution of the memory; and defining the second level to be higher than the upper limit of the second threshold voltage distribution. The upper limit of the second threshold voltage distribution is higher than the upper limit of the first threshold voltage distribution.

In the embodiment of the present invention, the controller further performs the following steps to read the memory cell: if the threshold voltage of the first end of the memory cell is lower than the first level, determining that the first end is in the first logic state.

In the embodiment of the present invention, the controller further performs the following steps to read the memory cell: if the threshold voltage of the first end of the memory cell is higher than the second level, determining that the first end is in the second logic state.

In the embodiment of the present invention, the controller further performs the following steps to read the memory cell: if the threshold voltage of the first end is between the first level and the second level, and if the threshold voltage of the first end Below the threshold voltage of the second terminal, it is determined that the first end is in the first logic state and the second end is in the second logic state.

In the embodiment of the present invention, the controller further performs the following steps to read the memory cell: if the threshold voltage of the first end is between the first level and the second level, and if the threshold voltage of the first end The threshold voltage is higher than the second end, and the first end is determined to be the second logic state and the second end is the first logic state.

The above described features and advantages of the present invention will be more apparent from the following description.

Please refer to FIG. 3 , which is a schematic cross-sectional view of a memory cell 30 of the prior art. The memory cell 30 has a substrate 32 having two buried PN junctions. One PN junction is between source 34 and substrate 32, and the other PN junction is between drain 36 and substrate 32. A bottom isolation layer 38 of the memory cell 30 is formed on the channel between the source 34 and the drain 36. On top of the isolation layer 38 is a charge trapping layer 40 that is electrically isolated from the substrate 32 by a bottom isolation layer 38. When hot electrons (hot electrons) are injected into the charge trap layer 40, the hot electrons are captured, so that the threshold voltage of the memory cell 30 is adjusted under control. A top isolation layer 42 is formed over the charge trapping layer 40 to electrically isolate the conductor gate 44 from the charge trapping layer 40. A gate 44 is formed on the isolation layer 42 (cerium oxide layer). The memory cell 30 has a first end 41 near the source 34 and a second end 43 near the drain 36. Each of the first end 41 and the second end 43 is programmable to store one bit of data. Therefore, the two-bit data can be stored in the memory cell 30.

When the first end 41 is programmed, a voltage is applied to the gate 44 and the source 34 such that vertical and lateral electric fields are generated to accelerate electrons from the drain 36 along the channel of the memory cell 30. As the electrons move along the channel, some of the electrons get enough energy to leap over the potential barrier of the isolation layer 38 and are captured in the charge trapping layer 40 near the first end 41. Therefore, the threshold voltage of the first terminal 41 increases, and the bit of the first terminal 41 changes from "1" to "0", that is, from the first logic state to the second logic state. Similarly, when the second terminal 43 is programmed, a voltage is applied to the gate 44 and the drain 36 to force electrons to be trapped in the charge trapping layer 40 adjacent the second end 43. Therefore, the threshold voltage of the second terminal 43 is increased, and the bit of the second terminal 43 is changed from "1" to "0".

Please refer to FIG. 4 and FIG. 5. FIG. 4 is a functional block diagram of a memory device 50 according to an embodiment of the invention. FIG. 5 is a circuit diagram of the memory 52 of the memory device 50. The memory device 50 has a memory 52, a controller 54, a column decoder 56, a row decoder 58, and a sensing circuit 60. The memory 52 has a plurality of memory cells 30 in FIG. The memory cell 30 of the memory 52 is disposed in an array having n columns and m rows, where n and m are integers greater than one. Controller 54 is coupled to column decoder 56 and row decoder 58 to control the operation of memory cell 30 of memory 52. Column decoder 56 applies a word line voltage to gate 44 of memory cell 30 via a plurality of word lines W ₀ -W _{n of} memory device 50. Row decoder 58 applies a bit line voltage to memory cell 30 via a plurality of bit lines B ₀ -B _{m+1 of} memory device 50. Referring to FIG. 3 and FIG. 5, the gate 44 of each memory cell 30 is coupled to one of the corresponding word lines W ₀ -W _n . The source 34 and the drain 36 of each of the memory cells 30 are coupled to adjacent two bit lines in the bit lines B ₀ -B _m+1 . For example, the gate of the upper left memory cell 30 is coupled to the word line W ₀ , and the source and drain of the leftmost memory cell 30 are coupled to the bit lines B ₀ and B _{1 , respectively} . In the present embodiment, when one end of a memory cell 30 is programmed, a first word line voltage (eg, 10V) is applied to the memory cell 30 via a corresponding one of the word lines W ₀ -W _n . a gate, applying a first bit line voltage (eg, 4V) to a source/drain close to one end of the stylized operation via a corresponding _one of the bit lines B ₀ -B _m+1 ; The source/drain of the other end of the memory cell 30 is grounded. Referring to FIG. 3, when the first terminal 41 is programmed, a first word line voltage is applied to the gate 44, a first bit line voltage is applied to the source 34, and the drain 36 is grounded. In addition, when the second terminal 43 is programmed, the first word line voltage is applied to the gate 44, the source 34 is grounded, and the first bit line voltage is applied to the drain 36. The stylized operation of memory cell 30 will continue until the threshold voltage at one end of the stylized operation is above or equal to a predetermined level.

In addition, when data is read from one end of the memory cell 30, a second word line voltage (eg, 5V) is applied to the gate of the memory cell 30 via a corresponding one of the word lines W ₀ -W _n . Grounding the source/drain close to one end under the read operation and applying a second bit line voltage (eg, 1.6V) via a corresponding _one of the bit lines B ₀ -B _m+1 to Source/drain near the other end. Referring to FIG. 3, when the bit of the first end 41 of the memory cell 30 is read, the second word line voltage is applied to the gate 44, the source 34 is grounded, and the second bit line voltage is applied to the drain. 36. If the second word line voltage is higher than the threshold voltage of the first terminal 41, the channel between the source 34 and the drain 36 is turned on, and the current flows from the drain 36 through the source 34 and the bit line B ₀ -B. _One of the corresponding bit lines of _m+1 flows to the sensing circuit 60. However, if the second word line voltage is lower than the threshold voltage of the first terminal 41, the channel between the source 34 and the drain 36 is turned off, and the sensing circuit 60 does not sense the memory. The current of cell 30. Accordingly, the sensing circuit 60 can determine the logic state of the bit of the first terminal 41 by detecting the current from the memory cell 30. Similarly, when the bit of the second end 43 of the memory cell 30 is read, the second word line voltage is applied to the gate 44, the second bit line voltage is applied to the source 34, and the drain 36 is grounded. If the second word line voltage is higher than the threshold voltage of the second terminal 43, the channel between the source 34 and the drain 36 is turned on, and the current flows from the source 34 through the drain 36 and the bit line B ₀ -B. _One of the corresponding bit lines of _m+1 flows to the sensing circuit 60. However, if the second word line voltage is lower than the threshold voltage of the second terminal 43, the channel between the source 34 and the drain 36 is turned off, and the sensing circuit 60 does not sense the memory. The current of cell 30.

Please refer to FIG. 6, which is a threshold voltage distribution diagram of the memory cell 30 when the memory cell 30 of the memory 52 is programmed in accordance with an embodiment of the present invention. Unlike the threshold voltage distributions shown in FIGS. 1 and 2, the horizontal axis in FIG. 6 represents the threshold voltage of each of the first end 41 and the second end 43 of the memory cell 30, and the vertical axis represents the memory cell 30. The number of bits stored by the first end 41 and the second end 43. FIG. 6 shows a first threshold voltage distribution 61, a second threshold voltage distribution 62, a third threshold voltage distribution 63, and a fourth threshold voltage distribution 64. The first threshold voltage distribution 61 represents the distribution of the threshold voltage of the bit "1" of the memory cell 30 having the "11" pattern. The second threshold voltage distribution 62 represents the distribution of the threshold voltage of the bit "1" of the memory cell 30 having the "01" and "10" modes. The third threshold voltage distribution 63 represents the distribution of the threshold voltage of the bit "0" of the memory cell 30 having the "01" and "10" modes. The fourth threshold voltage distribution 64 represents the distribution of the threshold voltage of the bit "0" of the memory cell 30 having the "00" pattern. The patterns "11", "01", "10", and "00" are used to indicate the data stored in the memory cell 30. For example, the memory cell 30 having the "11" mode indicates that the memory cell 30 stores the "11" of the two bits, and the memory cell 30 having the "01" mode indicates that the memory cell 30 stores the "01" of the two bits. In detail, the most significant bit (MSB) of each mode represents the data stored by the first end 41 of the corresponding memory cell 30, and the least significant bit of each mode (the least significant bit) , LSB) represents the data stored by the second end 43 of the corresponding memory cell 30. For example, the first end 41 of the memory cell 30 having the mode "01" stores the material of the one-bit "0", and the second end 43 of the memory cell 30 having the mode "01" stores the one-bit "1". data of.

As shown in FIG. 6, the first threshold voltage distribution 61 has an upper limit B2 and the second threshold voltage distribution 62 has B4. The upper limit B2 is the initial upper limit of the memory cell 30 when all memory cells are stylized. The upper limit B4 is a word line voltage that can be used to correctly identify all the bits of the logic "1". The upper limit B4 is higher than the upper limit B2. The upper limits B2 and B4 can be accurately obtained by measuring the threshold voltage of the memory cell 30. Further, the lower limit of the third threshold voltage distribution 63 is equal to or higher than the first level PV1, and the lower limit of the fourth threshold voltage distribution 64 is equal to or higher than the second level PV2. The first quasi-PV1 is defined as being above the upper limit B2, and the second quasi-PV2 is defined as being above the upper limit B4. Please refer to FIG. 4 to FIG. 7 at the same time. FIG. 7 is a flow chart when the controller 54 programs the memory cells 30 of the memory 52. For simplicity, FIG. 6 is used to illustrate the threshold voltage distribution of the memory cell 30 that is programmed after the memory cell 30 is programmed by the controller 54. When the memory cell 30 is programmed, if the second end 43 of the memory cell 30 of the group A should be at a low threshold voltage level, the first end 41 of the memory cell 30 of the group A is stylized and high. At the first level PV1 (step S701). The memory cell 30 of the group A referred to herein represents the memory cell 30 to be programmed into "01". In addition, when the memory cell 30 is programmed, if the first end 41 of the memory cell 30 of the group B should be at a low threshold voltage level, the second end 43 of the memory cell 30 of the group B is programmed to be higher than The first bit is quasi-PV1 (step S702). The memory cell 30 of the group B referred to herein represents the memory cell 30 to be programmatically "10". In addition, when the memory cell 30 is programmed, if the first end 41 and the second end 43 of the memory cell 30 of the group C should be at a high threshold voltage level, the first end 41 of the memory cell 30 of the group C is The second end 43 is programmed to be higher than the second level PV2 (step S703). The memory cell 30 of the group C referred to herein represents the memory cell 30 to be programmed into "00". The first end 41 or the second end 43 should be at a low threshold voltage level indicating that the bit of the first end 41 or the second end 43 should be "1" after the stylized operation of the memory 52, and the first end 41 or The second end 43 should be at a high threshold voltage level indicating that the threshold voltage indicates that the bit of the first end 41 or the second end 43 should be "0" after the stylized operation of the memory 52. Due to the second bit effect of the memory cell 30, when the stylized first end 41 is "0" and the second terminal 43 is not programmed, the threshold voltage of the unprogrammed second terminal 43 will increase. . Similarly, when the stylized second end 43 is "0" and the first end 41 is not programmed, the threshold voltage of the unprogrammed first end 41 will increase. As shown in FIG. 6, the second threshold voltage distribution 62 moves from the first threshold voltage distribution 61 to the right. In other words, the average threshold voltage of the bit "1" of the second threshold voltage distribution 63 is greater than the average threshold voltage of the bit "1" of the first threshold voltage distribution 61. In this case, group A may also be referred to as a first group, group C may also be referred to as a second group, and group B may also be referred to as a third group.

Please refer to Figure 7 again. The order of steps S701, S702, and S703 can be changed. For example, before proceeding to step S701, step S702 or S703 may be performed. Moreover, in accordance with an embodiment of the present invention, the first end of the memory cell 30 of the group C before the first end 41 and the second end 43 of the memory cell 30 of the group C are programmed to be higher than the second level PV2 41 is simultaneously programmed with the second end 43 and the first end 41 of the memory cell 30 of the group A to be higher than the first level PV1. In other words, the controller 54 controls the column decoder 56 and the row decoder 58 to program the first end 41 of the memory cells 30 of groups A and C to be higher than the first level PV1, and then to program the group A When the operation of one end 41 is stopped, the second end 43 of the memory cell 30 of the group C is programmed to be higher than the second level PV2. Therefore, the total programming time of the memory cell 30 will be shortened. In addition, in accordance with an embodiment of the present invention, the first end of the memory cell 30 of the group C is before the first end 41 and the second end 43 of the memory cell 30 of the group C are programmed to be higher than the second level PV2. 41 is simultaneously programmed with the second end 43 and the second end 43 of the memory cell 30 of the group A to be higher than the first level PV1. In other words, the controller 54 controls the column decoder 56 and the row decoder 58 to program the second end 43 of the memory cells 30 of groups A and C to be higher than the first level PV1, and then to program the group A When the operation of the two terminals 43 is stopped, the first end 41 of the memory cell 30 of the group C is programmed to be higher than the second level PV2.

In another embodiment of the present invention, when the first end 41 of the memory cell 30 of the group A is programmed to be higher than the first level PV1 in step S701, the second of the memory cells 30 of the group A will be determined. Whether the threshold voltage of terminal 43 is higher than the first level PV1. Since the threshold voltage of the second end 43 of the group A should be lower than the threshold voltage of the first end 41 of the group A, if the second bit affects, the threshold voltage of the second end 43 of the memory cell of the group A is high. At the first level PV1, it can be confirmed that the first end 41 of the memory cell 30 of the group A has been programmed to be higher than the first level PV1. Therefore, when the threshold voltage of the second end 43 of the memory cell 30 of the group A is higher than the first level PV1, the step S701 is terminated to stop the first end 41 of the memory cell 30 of the stylized group A. Similarly, when the second end 43 of the memory cell 30 of the group B is programmed to be higher than the first level PV1 in step S702, it will be determined whether the threshold voltage of the first end 41 of the memory cell 30 of the group B is Higher than the first level PV1. Since the threshold voltage of the first end 41 of the group B should be lower than the threshold voltage of the second end 43 of the group B, if the second bit affects, the threshold voltage of the first end 41 of the memory cell of the group B is high. At the first level PV1, it can be verified that the second end 43 of the memory cell 30 of group B has been programmed to be higher than the first level PV1. Therefore, when the threshold voltage of the first end 41 of the memory cell 30 of the group B is higher than the first level PV1, the step S702 is terminated to stop the second end 43 of the memory cell 30 of the stylized group B.

Please refer to FIG. 3 to FIG. 6 and FIG. 8 at the same time. FIG. 8 is a flow chart when the controller 54 reads data from the memory cells 30 of the memory 52. When selling access to the information from the memory cell 30, a column decoder 56 is applied to the word line via the word line voltage PV1 W ₀ -W _n memory cells to gate electrode 30. Since the word line voltage of PV1 is higher than the upper limit B2, the channel of the memory cell having the mode "11" will be turned off, so that the bit of each end of the memory cell 30 having the mode "11" can be read. In other words, all of the bits of the first threshold voltage distribution 61 can be correctly identified as a logic "1." Further, since the lower limit of the third threshold voltage distribution 63 is equal to or higher than the first level PV1, the bit having no logic "0" is erroneously determined to be logic "1". Therefore, when the data of the memory cell 30 is read by applying the word line voltage of PV1, the bits of the logical "1" read out are all correct. As previously described, the controller 54 determines whether the threshold voltage (Vt) at one end under the read operation is lower than the first level PV1 (step S801). If the threshold voltage Vt at one end under the reading operation is lower than the first level PV1, the bit at one end under the reading operation is determined to be the logic state "1" (step S805).

Furthermore, when reading data from memory cell 30, column decoder 56 applies another PV2 word line voltage to target memory cell 30. Since the word line voltage of PV2 is higher than the upper limit B4, all the bits of the memory cell having the pattern "00" can be read. In other words, all of the bits of the fourth threshold voltage distribution 64 can be correctly identified as a logical "0". Further, the second level PV2 is higher than the upper limit B4 of the second threshold voltage distribution 62, so a bit having no logic "1" is erroneously determined to be logic "0". Therefore, when the data of the memory cell 30 is read by applying the word line voltage of PV2, the bits of the logical "0" read out are all correct. The controller 54 determines whether the threshold voltage Vt at one end under the reading operation is lower than the first level PV2 (step S802). If the threshold voltage Vt at one end under the reading operation is higher than the second level PV2, the bit at one end under the reading operation is determined to be in the logic state "0" (step S804).

When the threshold voltage Vt at one end under the reading operation is between the first level PV1 and the second level PV2, it indicates that the data pattern of the memory cell 30 should be "01" or "10". In this case, the controller 54 compares the threshold voltage Vt at one end under the read operation with the threshold voltage Vtb at the adjacent end in the same memory cell 30 (step S803). If the threshold voltage Vt is higher than the threshold voltage Vtb, the bit at one end under the read operation can be identified as "0" (step S804), and the other end in the same memory cell 30 can be identified as "1" ". However, if the threshold voltage Vt is lower than the threshold voltage Vtb, the bit at one end under the read operation can be identified as "1" (step S805), and the other end in the same memory cell 30 can be identified as "0". It is to be noted that the order of steps S801 and S802 can be changed. In an embodiment of the invention, step S802 can be performed before step S801.

In summary, the controller of the present invention programs the first end and the second end of the memory cell to different levels. The plurality of threshold voltage distributions of the programmed memory cells can overlap each other such that the threshold voltage range can be reduced to increase the speed of the stylized memory cells. When reading data from a memory cell, the controller identifies the bit of the memory cell by comparing the threshold voltage of the memory cell having a different level and comparing the threshold voltage of the adjacent programmable end.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

21, 22, 23, 24. . . distribution area

30. . . Memory cell

32. . . Base

34. . . Source

36. . . Bungee

38, 42. . . Isolation layer

40. . . Charge trapping layer

41. . . First end

43. . . Second end

44. . . Gate

50. . . Memory device

52. . . Memory

54. . . Controller

56. . . Column decoder

58. . . Row decoder

60. . . Sense circuit

61. . . First threshold voltage distribution

62. . . Second threshold voltage distribution

63. . . Third critical voltage distribution

64. . . Fourth threshold voltage distribution

A, B, C. . . Group

B ₀ -B _m+1 . . . Bit line

B2, B4. . . Upper limit

PV1. . . First standard

PV2. . . Second level

S701-S703, S801-S805. . . step

SW1, SW2, SW3, SW4, SW5, SW6. . . Sense window

W ₀ -W _n . . . Word line

Figure 1 shows the critical voltage distribution of a typical 1-megabite memory.

Figure 2 is a diagram showing the threshold voltage distribution of a general 1-gigabite memory.

3 is a schematic cross-sectional view of a memory cell of the prior art.

4 is a functional block diagram of a memory device according to an embodiment of the invention.

Fig. 5 is a circuit diagram of a memory of the memory device of Fig. 4.

6 is a diagram showing a threshold voltage distribution of a memory cell when a memory cell of a memory is programmed in accordance with an embodiment of the present invention.

Figure 7 is a flow chart when the controller of Figure 4 stylizes the memory cells of the memory.

Figure 8 is a flow chart when the controller of Figure 4 reads data from the memory cells of the memory.

S701-S703. . . step

Claims (22)

A method of operating a memory, the memory comprising a plurality of memory cells, each memory cell having a first end and a second end, each of the first end and the second end storing one bit The method of operating the memory includes: staging the memory cells of the first group when the second ends of the memory cells of a first group are at a low threshold voltage level The first ends are higher than a first level; and when the first ends of the memory cells of the second group and the second ends are at a high threshold voltage level, the first The first ends of the memory cells of the two groups and the second ends are higher than a second level, wherein the first level is lower than the second level. The method of operating a memory according to the first aspect of the invention, wherein when the threshold voltages of the second ends of the memory cells of the first group are higher than the first level, the method further includes stopping the stylization. The first ends of the memory cells of the first group. The method of operating a memory according to claim 1, wherein when the first ends of the memory cells of a third group are at the low threshold voltage level, further comprising stylizing the third The second ends of the memory cells of the group are higher than the first level. The method of operating a memory according to claim 1, wherein before the first end of the memory cells of the second group and the second ends are higher than the second level The memory of the second group The first ends of the cells and the second ends and the first ends of the memory cells of the first group are simultaneously programmed to be higher than the first level. The method for operating a memory according to claim 1, further comprising: finding an upper limit of a first threshold voltage distribution of the memory, the first threshold voltage distribution indicating that the stored data has an "11" mode a distribution of a threshold voltage of a bit "1" of the memory cell; and defining the first level to be above an upper limit of the first threshold voltage distribution. The method for operating a memory according to claim 5, further comprising: finding an upper limit of a second threshold voltage distribution of the memory, the second threshold voltage distribution indicating that the stored data has "01" and " a distribution of a threshold voltage of a bit "1" of the memory cell of the 10" mode; and defining the second level to be higher than an upper limit of the second threshold voltage distribution, wherein an upper limit of the second threshold voltage distribution is higher than the first The upper limit of a critical voltage distribution. A method of operating a memory, the memory comprising at least one memory cell having a first end and a second end, each of the first end and the second end storing one bit The method for operating the memory includes: determining whether a threshold voltage of the first end of the memory cell is higher than a first level; determining whether a threshold voltage of the first end of the memory cell is lower than a second bit Prevailing, wherein the first level is lower than the second level; When the threshold voltage of the first end is between the first level and the second level, comparing the threshold voltage of the first end with the threshold voltage of the second end. The method of operating a memory according to claim 7, wherein if the threshold voltage of the first end of the memory cell is lower than the first level, the method further comprises determining that the first end is a first logic state. . The method of operating a memory according to claim 7, wherein if the threshold voltage of the first end of the memory cell is higher than the second level, the method further comprises determining that the first end is a second logic state. . The method of operating a memory according to claim 7, wherein if the threshold voltage of the first end is between the first level and the second level, and if the threshold voltage of the first end The threshold voltage lower than the second end further includes determining that the first end is a first logic state and the second end is a second logic state. The method of operating a memory according to claim 7, wherein if the threshold voltage of the first end is between the first level and the second level, and if the threshold voltage of the first end The threshold voltage is higher than the second end, and further includes determining that the first end is a second logic state and the second end is a first logic state. A memory device includes: a memory having a plurality of memory cells, each memory cell having a first end and a second end, each of the first end and the second end storing one bit Metadata; and a controller for at least performing the following steps to program the memory cells: when the second ends of the memory cells of a first group are at a low threshold voltage level, the first group is programmed The first ends of the memory cells of the group are higher than a first level; and when the first ends of the memory cells of the second group and the second terminals are at a high threshold voltage At the time of registration, the first ends of the memory cells of the second group and the second terminals are programmed to be higher than a second level, wherein the first level is lower than the second level. The memory device of claim 12, wherein the controller further performs the following steps to program the memory cells: when the threshold voltages of the second ends of the memory cells of the first group are high At the first level, the first ends of the memory cells of the first group are stopped. The memory device of claim 12, wherein the controller further performs the following steps to program the memory cells: when the first ends of the memory cells of a third group are When the threshold voltage level is low, the second ends of the memory cells of the third group are programmed to be higher than the first level. The memory device of claim 12, wherein before the first end of the memory cells of the second group and the second ends are higher than the second level, The controller simultaneously programs the first end of the memory cells of the second group and the second ends and the first ends of the memory cells of the first group to be higher than the first bit quasi. The memory device of claim 12, wherein the controller further performs the following steps to program the memory cells: finding an upper limit of a first threshold voltage distribution of the memory, the first threshold voltage distribution A distribution of threshold voltages indicating that the stored data has a bit "1" of the memory cell of the "11" mode; and defining the first level to be higher than the upper limit of the first threshold voltage distribution. The memory device of claim 16, wherein the controller further performs the following steps to program the memory cells: finding an upper limit of a second threshold voltage distribution of the memory, the second threshold voltage distribution a distribution of threshold voltages indicating that the stored data has a bit "1" of the memory cells of the "01" and "10" modes; and defining the second level to be higher than an upper limit of the second threshold voltage distribution, wherein The upper limit of the second threshold voltage distribution is higher than the upper limit of the first threshold voltage distribution. A memory device includes: a memory having at least one memory cell, the memory cell having a first end and a second end, each of the first end and the second end storing a bit And a controller for performing at least the following steps to read the memory cells: determining whether a threshold voltage of the first end of the memory cell is higher than a first level; determining the first of the memory cells Whether the threshold voltage at one end is lower than a second level, wherein the first level is lower than the second level; When the threshold voltage of the first end is between the first level and the second level, comparing the threshold voltage of the first end with the threshold voltage of the second end. The memory device of claim 18, wherein the controller further performs the following steps of reading the memory cell: if the threshold voltage of the first end of the memory cell is lower than the first level, determining The first end is in a first logic state. The memory device of claim 18, wherein the controller further performs the following steps of reading the memory cell: if the threshold voltage of the first end of the memory cell is higher than the second level, determining The first end is in a second logic state. The memory device of claim 18, wherein the controller further performs the following steps to read the memory cell: if the threshold voltage of the first terminal is between the first level and the second level And if the threshold voltage of the first end is lower than the threshold voltage of the second end, determining that the first end is a first logic state and the second end is a second logic state. The memory device of claim 18, wherein the controller further performs the following steps to read the memory cell: if the threshold voltage of the first terminal is between the first level and the second level And if the threshold voltage of the first end is higher than the threshold voltage of the second end, determining that the first end is a second logic state and the second end is a first logic state.