CN101887749B - Memory device and method of operating the same - Google Patents

Abstract

The invention discloses a memory device and an operation method thereof. The method includes applying a first bit line voltage to the memory cell to sense a first current of the memory cell. When the first current is greater than a first reference current related to the first bit line voltage, the first data storage area is determined to be in an un-programmed state. Otherwise, a second bit line voltage is applied to the memory cell to sense a second current of the memory cell. When the difference between the first current and the second current is greater than the difference between the first reference current and the second reference current, the first data storage area is determined to be in an un-programmed state. Otherwise, the first data storage area is judged to be in a programming state.

Description

Memory device and method of operating the same

technical field

The present invention relates to a method of operating a memory and a memory device, and more particularly to a method and a memory device for reducing second bit effects in a memory device.

Background technique

Memory is a semiconductor component used to store information or data. As computer microprocessors have become more powerful, the number of programs and operations performed by software has also increased. Therefore, the demand for memories with high storage capacity is gradually increasing.

Among various memory products, non-volatile memory (non-volatile memory) allows multiple data programming (programming), reading (reading) and erasing (erasing) operations, and even after the power supply of the memory is interrupted Ability to save data stored in it. Due to these advantages, nonvolatile memory has become a widely used memory in personal computers and electronic equipment.

Well-known electrically programmable and erasable (electrically programmable and erasable) non-volatile memory technologies for charge storage structures such as electrically erasable programmable read-only memory (EEPROM) ) and flash memory (flash memory) have been used in various modern applications. Flash memory is designed with an array of memory cells that can be programmed and read independently. A general flash memory cell stores charge in a floating gate. Another type of flash memory uses a charge-trapping structure, such as a layer of nonconducting silicon nitride (SiN) material, rather than the conductive gate material used in floating gate devices. When a charge trapping memory cell is programmed, charge is trapped and does not move through the nonconductive layer. The charge is held by the charge trapping layer until the memory cell is erased, maintaining the data state when power is not continuously supplied. The charge trapping memory cell can be operated as a two-sided cell. That is, since the charges do not move through the nonconductive charge trapping layer, the charges can be located at different charge traps. In other words, more than one bit of information is stored in each memory cell in a flash memory device using a charge trapping structure.

A single memory cell can be programmed to store two completely separate bits in the charge-trapping structure (in such a way that charges are concentrated near the source and drain regions, respectively). Programming of memory cells can be performed by channel hot electron (CHE) injection, which generates hot electrons in the channel region. Some hot electrons gain energy and are trapped in the charge trapping structure. By reversing the biases applied to the source and drain terminals, charge is trapped to either part of the charge trapping structure (near the source region, near the drain region, or both).

Therefore, if no charge is stored in the memory cell, the threshold voltage of the memory cell has a minimum value corresponding to the combination of bits 1 and 1. If the charge is stored in the charge trapping structure near the source region but not near the drain region, the threshold voltage has a different value corresponding to the combination of bits 1 and 0. If charge is stored near the drain region but not near the source region, the threshold voltage has another value. In this case, the threshold voltage corresponds to a combination of bits 0 and 1. Finally, if the charge is stored near the source and drain regions, the threshold voltage is highest and corresponds to the combination of bits 0 and 0. Therefore, four different combinations (bits 00, 01, 10, and 11) can be stored, and each combination has a corresponding threshold voltage. During a read operation, the current flowing through a memory cell will vary depending on the threshold voltage of the memory cell. Typically, this current will have four different values, each corresponding to a different threshold voltage. Therefore, by detecting this current, it is possible to determine the byte status stored in the memory cell.

The entire effective charge range or threshold voltage range can be classified as a memory operation window. In other words, the memory operation margin is defined by the difference between the programming level and the erasing level. Since memory cell operations require good level separation between various states, a large memory operation margin is required. However, the performance of 2-bit memory cells generally degrades with the so-called "second bit effect". Under the second-site effect, the localized charges in the charge-trapping structure influence each other. For example, during a reverse reading operation, a read bias is applied to the drain terminal and the charge stored near the source region (ie, the "first bit") is detected. However, then the bit near the drain region (ie, the "second bit") creates a potential barrier to reading the first bit near the source region. This barrier can be overcome by applying an appropriate bias, using the drain-induced barrier lowering (DIBL) effect to suppress the effect of the second bit close to the drain region and allow detection of the storage of the first bit. state. However, when the second bit near the drain region is programmed to a high threshold voltage state and the first bit near the source region is in an unprogrammed state, the second bit substantially raises the barrier. Thus, as the threshold voltage with respect to the second bit increases, the read bias of the first bit is no longer sufficient to overcome the potential barrier created by the second bit. Therefore, since the threshold voltage with respect to the second bit increases, the threshold voltage with respect to the first bit also increases, thereby reducing the memory operation margin. The second bit effect reduces the memory operation margin for 2-bit/cell operation. Accordingly, there is a need for methods and devices for suppressing second bit effects in memory devices.

Contents of the invention

The invention provides a method for reading a memory cell, which can alleviate the second bit effect.

The invention also provides a method for operating a storage unit, which can reduce the operating margin.

The present invention proposes a method of operating a storage unit having a first data storage area and a second data storage area. The method includes applying a first bit line voltage to the memory cell to detect a first current of the memory cell. When the first current is greater than the first reference current about the first bit line voltage, it is determined that the first data storage area is in an unprogrammed state. When the first current is less than the first reference current, a second bit line voltage is applied to the memory cell to detect a second current of the memory cell. Then, when the first difference between the first current and the second current is greater than the second difference between the first reference current and the second reference current, it is determined that the first data storage area is in an unprogrammed state. However, when the first difference is less than or equal to the second difference, it is determined that the first data storage region is in a programmed state.

According to an embodiment of the present invention, the second bit line voltage is different from the first bit line voltage.

According to an embodiment of the present invention, the second bit line voltage is greater than the first bit line voltage.

According to an embodiment of the present invention, the first word line voltage for detecting the first current is equal to the second word line voltage for detecting the second current.

According to an embodiment of the present invention, the method further includes defining a program verify voltage of the memory cell and defining an upper limit of the low threshold voltage distribution of the memory cell. In addition, the difference between the program confirm voltage and the upper limit of the low threshold voltage distribution is about 600mV.

The invention further provides a memory device. The memory device includes a memory and a controller. The memory has a plurality of memory cells. Each storage unit has a first data storage area and a second data storage area. The controller is used to perform a reading process on each storage unit. For each memory cell, the step of reading includes applying a first bit line voltage to the memory cell to detect a first current of the memory cell. When the first current is greater than the first reference current about the first bit line voltage, it is determined that the first data storage area is in an unprogrammed state. When the first current is less than the first reference current, a second bit line voltage is applied to the memory cell to detect a second current of the memory cell. Then, when the first difference between the first current and the second current is greater than the second difference between the first reference current and the second reference current, it is determined that the first data storage area is in an unprogrammed state. However, when the first difference is less than or equal to the second difference, it is determined that the first data storage region is in a programmed state.

The invention also provides a memory device. The memory device includes a memory, a detection circuit and a controller. The memory has a plurality of memory cells. Each storage unit has a first data storage area and a second data storage area. The detection circuit is used to apply a first bit line voltage to the memory cell during the reading step to detect a first current of the memory cell, wherein when the first current is less than a first reference current with respect to the first bit line voltage, the detection circuit applies the first current. The second bit line voltage is applied to the storage unit to detect the second current of the storage unit. The controller is used to read each memory cell with reference to the program verify voltage. For each memory cell, the reading step includes detecting a first threshold voltage of the first data storage area, and then judging that the first data storage area is in an unprogrammed state when the first threshold voltage is lower than the program verification voltage.

In the present invention, when reading data from each data storage area in the memory cell, the performance of the threshold voltage distribution of the target data storage area (target data storage) under different bit line voltages is used to determine the target data storage area programming status. Therefore, even if the operating margin is small, even if the operating margin is closed, when the detection current is smaller than the reference current, the data storage area with a bit "1" and the data storage area with a bit "0" under the second bit effect Datastores can be correctly distinguished. Therefore, when the size of memory cells shrinks, operating margin will no longer be an obstacle. Additionally, second bit effects on memory cell operations are mitigated. In addition, since the second bit effect is mitigated and has a small operating margin, the programming speed is increased and the time to program memory cells is reduced.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail together with the accompanying drawings.

Description of drawings

FIG. 1 is a schematic cross-sectional view of a memory cell according to an embodiment of the invention.

FIG. 2 is a functional block diagram of a memory device according to an embodiment of the invention.

FIG. 3 is a circuit diagram of a memory of the memory device in FIG. 2 .

FIG. 4A is a graph showing threshold voltage distributions of memory cells when a first current is sensed when the memory cells are programmed according to an embodiment of the present invention.

FIG. 4B is a graph showing threshold voltage distributions of memory cells when a second current is sensed when the memory cells are programmed according to an embodiment of the present invention.

FIG. 5 is a flow chart of steps of a method for reading a storage unit of a memory according to an embodiment of the present invention.

FIG. 6A is a graph showing threshold voltage distributions of data storage regions in memory cells in an unprogrammed state “11” with various bit line voltages according to an embodiment of the present invention.

FIG. 6B is a graph showing threshold voltage distributions of data storage in memory cells under programming state "00" with various bit line voltages according to an embodiment of the present invention.

FIG. 6C is a graph showing threshold voltage distributions of data storage regions in memory cells under programming states “01”/“10” with various bit line voltages according to an embodiment of the present invention.

FIG. 7 is a flow chart illustrating the steps of defining a process margin according to an embodiment of the present invention.

FIG. 8 is a flow chart of steps of a method for reading a storage unit of a memory according to an embodiment of the present invention.

[Description of main component symbols]

100: storage unit

110a: first data storage area

110b: Second data storage area

102: Substrate

104: source/drain region

108, 112: insulating layer

110: charge trapping layer

114: conductor grid

200: memory device

202: memory

204: Controller

206: column decoder

208: row decoder

210: detection circuit

212: Analog to Digital Converter

402: First threshold voltage distribution

404: Second Threshold Voltage Distribution

406: Third Threshold Voltage Distribution

602, 604: threshold voltage distribution groups

B0-Bm+1: bit line

D1, D2: voltage difference

Dr: Reference voltage difference

S501-S511, S701-S703, S801-S815: steps

W0-Wn: word line

Detailed ways

FIG. 1 is a schematic cross-sectional view of a memory cell according to an embodiment of the invention. As shown in FIG. 1 , memory cell 100 has substrate 102 . Two source/drain regions 104 are formed in the substrate 102 . The bottom insulating layer 108 of the memory cell 100 is formed on the channel between the source/drain regions 104 . Charge trapping layer 110 is located on top of insulating layer 108 , which is electrically isolated from substrate 102 by insulating layer 108 . When hot electrons are injected into the charge trapping layer 110, the hot electrons are trapped so that the threshold voltage of the memory cell 100 will be adjusted under control. The top insulating layer 112 is formed on the charge trapping layer 110 to electrically isolate the conductor gate 114 from the charge trapping layer 110 . The memory unit 100 has a first data storage region 110 a close to one of the source/drain regions 104 and a second data storage region 110 b close to the other of the source/drain regions 104 . The first data storage area 110a and the second data storage area 110b are programmable to store one bit of data. Therefore, two bits of data will be stored in the memory unit 100 .

When programming the first data storage region 110a, a voltage is applied to the conductor gate 114 and the source/drain region 104 close to the first data storage region 110a, thereby generating vertical and lateral electric fields to allow electrons to flow from the other source The /drain region 104 accelerates away from the first data storage region 110 a along the channel of the memory cell 100 . When electrons move along the channel, some electrons gain enough energy to jump over the potential barrier of the bottom insulating layer 108 and are trapped in the charge trapping layer 110 around the first data storage region 110a. Therefore, when the bit in the unprogrammed state is defined as logic "1", the threshold voltage of the first data storage area 110a increases, and the bit of the first data storage area 110a changes from "1" to "0", that is, from The first logic state transitions to the second logic state. Likewise, when programming the second data storage region 110b, a voltage is applied to the conductor gate 114 and the source/drain region 104 near the second data storage region 110b, so that electrons are trapped around the second data storage region 110b in the charge trapping layer 110. Therefore, the threshold voltage of the second data storage region 110b will increase, and the bit of the second data storage region 110b will change from "1" to "0".

FIG. 2 is a functional block diagram of a memory device according to an embodiment of the invention. FIG. 3 is a circuit diagram of a memory of the memory device in FIG. 2 . As shown in FIG. 2 and FIG. 3 , the memory device 200 has a memory 202, a controller 204, a row decoder (row decoder) 206, a row decoder (column decoder) 208, a detection circuit 210, and an analog-to-digital converter ( analog-to-digital converter) 212. The memory 202 has a plurality of storage units 100 (as shown in FIG. 1 ). The storage units 100 of the memory 202 are arranged in an array with n columns and m rows, wherein n and m are integers greater than 1. The controller 204 is coupled to the column decoder 206 and the row decoder 208 to control the operation of the storage unit 100 of the memory 202 . The analog-to-digital converter 212 is coupled to the controller 204 to convert the detected current and the reference current into digital values respectively. The column decoder 206 applies a word line voltage to the conductor gate 114 of the memory cell 100 via a plurality of word lines W ₀ -W _n of the memory device 200 . The row decoder 208 applies the bit line voltage to the memory cell 100 via a plurality of bit lines B ₀ -B _m+1 of the memory device 200 . As shown in FIGS. 1 and 3 , the conductor gate 114 of each memory cell 100 is coupled to a corresponding one of the word lines W ₀ -W _n . The source/drain region 104 of each memory cell 100 is coupled to two adjacent bit lines among the bit lines B ₀ -B _m+1 . For example, the conductor gate of the upper left memory cell 100 is coupled to word line W ₀ , and the source/drain regions of the upper left memory cell 100 are respectively coupled to bit lines B ₀ and B ₁ .

When reading data information from a data storage area of the memory cell 100, a word line voltage (for example, 5V) is applied to the conductor gate 114 of the memory cell 100 via a corresponding word line in the word lines W ₀ -W _n . In the fetch operation, the source/drain area close to the data storage area is grounded, and the other source/drain area close to another data storage area is connected to a corresponding bit line pair in the bit line B ₀ -B _m+1 . A bit line voltage (eg, 1.6V) is applied to the drain region. As shown in FIG. 1, when reading the bit of the first data storage region 110a of the memory cell 100, a word line voltage is applied to the conductor gate 114, and the source/drain region 104 close to the first data storage region 110a is grounded. , and a second bit line voltage is applied to the other source/drain region 104 . If the word line voltage is higher than the threshold voltage of the first data storage region 110a, the channel between the source/drain region 104 is turned on, and the current flows from the source/drain region 104 (away from the first data storage region 110a). The storage region 110 a ) flows to the detection circuit 210 through the source/drain region 104 (near the first data storage region 110 a ) and a corresponding one of the bit lines B ₀ -B _m+1 . However, if the word line voltage is lower than the threshold voltage of the first data storage region 110a, the channel between the source/drain region 104 is turned off, and the detection circuit 210 will not detect the voltage from the memory cell 100a. current. Therefore, the detection circuit 210 will determine the logic state of the bit in the first data storage area 110 a by detecting the current from the memory unit 100 . Similarly, when reading the bit of the second data storage region 110b of the memory cell 100, the word line voltage is applied to the conductor gate 114, and the bit line voltage is applied to the source/drain region 104 (away from the second data storage region 110b). voltage, and ground the source/drain region 104 (near the second data storage region 110b). If the word line voltage is higher than the threshold voltage of the second data storage region 110b, the channel between the source/drain region 104 is turned on, and the current flows from the source/drain region 104 (away from the second data storage region 110b) It flows to the detection circuit 210 through the source/drain region 104 (near the second data storage region 110 b ) and a corresponding one of the bit lines B ₀ -B _m+1 . However, if the word line voltage is lower than the threshold voltage of the second data storage region 110 b , the channel between the source/drain regions 104 is closed, and the detection circuit 210 will not detect the current from the memory cell 100 .

For a memory cell with 2-bit storage (such as the memory cell 100), there are at least four programming states (including 11, 01, 10 and 00). In this embodiment, the unprogrammed state of the memory cell is defined as logic "11". Therefore, when both the first data storage area and the second data storage area are programmed, the programming state of the memory cell is defined as logic "00". In addition, the programmed state of each memory cell can be represented by a corresponding threshold voltage distribution. FIG. 4A is a graph showing threshold voltage distributions of memory cells when a first current is sensed when the memory cells are programmed according to an embodiment of the present invention. FIG. 4B is a graph showing threshold voltage distributions of memory cells when a second current is sensed when the memory cells are programmed according to an embodiment of the present invention. As shown in FIG. 4A, the horizontal axis in FIG. 4A represents the word line voltages of the first data storage region 110a and the second data storage region 110b of the memory cell 100, while the vertical axis represents the voltage generated by the first data storage region 110a of the memory cell 100. and the number of bits stored in the second data storage area 110b. As shown in FIG. 4A , a first threshold voltage distribution 402 represents a distribution of threshold voltages for bit "1" of memory cells 100 having a programmed state of "11". In other words, when both the first data storage region and the second data storage region of the memory cell are in an unprogrammed state, the first threshold voltage distribution 402 is a low threshold voltage distribution of unprogrammed bits of the memory cell.

In addition, the second threshold voltage distribution 404 represents the distribution of the threshold voltages of the bit "1" of the memory cells 100 having the programmed states of "01" and "10". That is, the second threshold voltage distribution 404 represents the threshold voltage distribution of unprogrammed cells of the memory cells when the first data storage region or the second data storage region is programmed. In other words, the second threshold voltage distribution 404 is the threshold voltage distribution of unprogrammed cells of the memory cells under the second bit effect. The third threshold voltage distribution 406 represents the distribution of the threshold voltages of the bit “0” of the memory cells 100 . In other words, the third threshold voltage distribution 406 represents the threshold voltage distribution of the programmed bits of the memory cells.

As shown in FIG. 4A , the second threshold voltage distribution 404 partially overlaps the third threshold voltage distribution 406 in addition to partially overlapping the first threshold voltage distribution 402 . It is obvious that the operating margin for reading the data information of the storage unit is very small, or even non-existent. The present invention provides an operation method for reading data information stored in one of the first data storage area 110a and the second data storage area 110b. By applying the operation method of the present invention, it can be easily distinguished from the programmed state of the data storage area under the second bit effect, even if the second threshold voltage distribution 404 overlaps with the third threshold voltage distribution and the operating margin of the read operation is not exist. FIG. 5 is a flow chart of steps of a method for reading a storage unit of a memory according to an embodiment of the present invention. When reading the data information of the first data storage area 110a in the memory cell 100, the controller ₂₀₄ applies the word line voltage to the conductor gate 114 of the memory cell 100 and the source of the memory cell 100 through the word lines _W0 -Wn. A bias voltage is applied between the electrode/drain regions 104 to perform the reading step. That is, the application is accomplished by applying the first bit line voltage to the source/drain region 104 (away from the first data storage region 110a) and grounding the source/drain region 104 near the first data storage region 110b. The bias voltage between the source/drain regions 104 . As shown in FIG. 5 , a first current induced by a first bit line voltage is detected in the source/drain region 104 (step S501 ).

In step S503 , the first current is compared with a first reference current related to the first bit line voltage, and the word line voltage is applied to the memory cell 100 . Typically, for reading data information in a memory cell, a predetermined and fixed word line voltage is applied to the conductor gate 114, and a predetermined and fixed bit line voltage is applied to the source/drain of the data storage area to be read. polar region 104. The generated current is mapped to the programmed state by comparing the generated current with a reference current with respect to the word line voltage and applying the bit line voltage to the memory cell. If the read current is higher than the reference current, the memory cell is judged to be in a logic state (ie, unprogrammed state). In other words, if the current is lower than the reference current, the memory cell is determined to be in another logic state (ie, programmed state).

Therefore, in step S505, when the first current is greater than the first reference current with respect to the first bit line voltage, it is determined that the first data storage region is in an unprogrammed state. Regarding the threshold voltage of the first data storage region 110a, the higher the current, the lower the threshold voltage. Therefore, when the first current is greater than the first reference current with respect to the first bit line voltage, the threshold voltage of the first data storage region 110a is less than the reference voltage with respect to the reference current. As shown in FIG. 4A, the reference voltage with respect to the reference current is higher than the upper limit of the first threshold voltage distribution 402 and part of the second threshold voltage distribution 404, so that all bits with a threshold voltage less than the reference voltage can be correctly distinguished as logic " 1", and bits without logic "0" are incorrectly judged as logic "1". Therefore, when data information is read from the first data storage area 110a of the memory unit 100 by detecting the first current higher than the reference current, the data information in the first data storage area 110a is determined to be logic "1", and the second A data storage area 110a is determined to be in an unprogrammed state.

In addition, since the second bit effect increases the potential barrier for reading data information from the target data storage area (adjacent to the data storage area of another programmed state), it is not easy to simply convert the selected current when the detected current is smaller than the reference current. The detected current is mapped to the programming state to determine the data information of the target data storage area in the memory cell. In terms of threshold voltage, the smaller the current, the higher the threshold voltage. As shown in FIG. 4A , for reading data information from the target data storage area, when the detected current is lower than the reference current, the threshold voltage of the target data storage area is higher than the reference voltage with respect to the reference current. However, as shown in FIG. 4A, in addition to the data storage area of bit "0" having a threshold voltage higher than the reference voltage, the data storage area of bit "1" also has a threshold voltage higher than the reference voltage under the second bit effect. . Therefore, when the threshold voltage is higher than the reference voltage, under the second bit effect or the programmed state where the bit in the target data storage area is only logic "0", it is not easy to simply refer to the detected current of the target data storage area. Determine whether the bit in the target data storage area is a logic "1" of the storage unit.

FIG. 6A is a graph showing threshold voltage distributions of data storage regions in memory cells in an unprogrammed state “11” with various bit line voltages according to an embodiment of the present invention. FIG. 6B is a graph showing threshold voltage distributions of data storage in memory cells under programming state "00" with various bit line voltages according to an embodiment of the present invention. It should be noted that the voltage variation of the bit line in FIG. 6A , FIG. 6B and FIG. 6C can be represented by probing different voltages of the bit line through an external power supply device. As shown in FIG. 6A , no matter how the bit line voltage is changed from 1V to 1.6V and 2.3V, the threshold voltage distribution pattern of the bit “1” of the memory cell 100 in the “11” programming state is almost the same. Furthermore, the threshold voltage distributions for different bit line voltages do not deviate from each other after excluding a voltage deviation factor due to current variation with different bit line voltages. Likewise, as shown in FIG. 6B , it is apparent that the threshold voltage distribution patterns of the bit “0” of the memory cells 100 in the “00” programmed state are almost the same. Furthermore, the threshold voltage distributions do not shift away from each other after excluding the voltage deviation coefficient. It should be noted that the threshold voltage distribution of the bit "0" of the memory cell 100 in the "00" programming state and the threshold voltage distribution of the bit "1" of the memory cell 100 in the "11" programming state will not be applied with different bit line voltages. And affect.

FIG. 6C is a graph showing threshold voltage distributions of data storage regions in memory cells under programming states “01”/“10” with various bit line voltages according to an embodiment of the present invention. As shown in FIG. 6C, the threshold voltage distribution group 602 represents the threshold voltage of the bit "0" of the memory cell 100 in the "10" or "01" programming state when the bit line voltage is changed from 1V to 1.6V, 2.3V, and 3V. distributed. In addition, the threshold voltage distribution group 604 represents the threshold voltage distribution of the bit "1" of the memory cell 100 in the "01" or "10" programming state when the bit line voltage is changed from 1V to 1.6V, 2.3V, and 3V. As shown in FIG. 6C , it is evident that in the threshold voltage distribution group 602 of the bit "0" of the memory cell 100 in the "10" or "01" programming state, the threshold voltage distribution patterns are almost the same. Furthermore, the threshold voltage distributions do not shift away from each other after excluding the voltage deviation coefficient.

However, as shown by threshold voltage distribution group 604, the pattern of threshold voltage distributions for bit "1" of memory cell 100 of the "10" or "01" programmed state is slightly distorted. Most importantly, the threshold voltage distribution shifts toward lower threshold voltages as the bit line voltage changes from 1V to 1.6V, 2.3V, and 3V after excluding the voltage deviation coefficient. Apparently, as shown in FIGS. 6A, 6B and 6C, only the data storage area with bit "1" under the second bit effect is strongly affected by the change of the bit line voltage. That is, only the bit "1" threshold voltage distribution under the second bit effect will shift significantly. Therefore, when the threshold voltage is greater than the reference voltage (the detected current is less than the reference current), the data information in the data storage area can be accurately determined by further applying different bit line voltages to detect changes in the current of the memory cell.

In particular, as shown in FIG. 4B, when a second bit line voltage greater than the first bit line voltage is applied to the source/drain region 104 (away from the data storage area to be read) and the word line voltage remains the same, the detection to the second current. If the data storage area to be read is in the programmed state, the change of the detected current under different bit line voltages is less than or equal to the voltage deviation coefficient (represented by the change of the reference current due to the application of different bit line voltages). That is to say, as shown in FIG. 4A and FIG. 4B, in terms of threshold voltage, compared with the threshold voltage distribution 406 in FIG. 4A, the threshold voltage distribution 406' of the data storage region in the programmed state in FIG. 4B is shifted to the right. The voltage difference D1 (less than or equal to the reference voltage difference Dr, which varies with respect to the reference current when different bit line voltages are applied).

If the data storage area to be read is in the unprogrammed state with the second bit effect, the detected current variation under different bit line voltages is larger than the voltage deviation coefficient caused by applying different bit line voltages. In other words, as shown in FIG. 4A and FIG. 4B , in terms of threshold voltages, compared to the threshold voltage distribution 404 in FIG. 4A , the threshold voltage distribution 404' of the data storage region in the unprogrammed state with the second bit effect in FIG. 4B The voltage difference D2 is offset to the right (greater than the reference voltage difference Dr, which varies with respect to the reference current when different bit line voltages are applied).

Therefore, as shown in FIG. 5, when the first current is smaller than the reference current, a second bit line voltage (different from the first bit line voltage) is applied to the source/drain region 104 (away from the first data storage region 110a), And the word line voltage remains the same to detect the second current (step S507). It should be noted that the second bit line voltage is greater than the first bit line voltage. Then, in step S509 , the difference between the second current and the first current is compared with the reference current change caused by different bit line voltages applied to the memory cell 100 . That is, by excluding the voltage deviation coefficient due to the application of different bit line voltages, the true behavior of the threshold voltage distribution after application of different bit line voltages can be detected. Therefore, when the difference between the second current and the first current is less than or equal to the difference between the first reference current with respect to the first bit line voltage and the second reference current with respect to the second bit line voltage, the first data storage The threshold voltage distribution of the regions is not affected by different applied bit line voltages. Therefore, the data information of the first data storage area 110a is determined to be logic "0", and the first data storage area 110a is determined to be in a programming state (step S511).

On the other hand, when the difference between the second current and the first current is greater than the difference between the first reference current with respect to the first bit line voltage and the second reference current with respect to the second bit line voltage, the first data storage The threshold voltage distribution of a region can be heavily influenced by different applied bit line voltages. Therefore, the data information of the first data storage area 110a is determined as logic "1" with the second bit effect, and the first data storage area 110a is determined to be in an unprogrammed state (step S505).

FIG. 7 is a flow chart illustrating the steps of defining a process margin according to an embodiment of the present invention. As shown in FIG. 7, before the first data storage area 110a or the second data storage area 110b is read or programmed, the present invention further includes the step of defining the upper limit of the low threshold voltage distribution of the memory cell (step S701) and defining the storage The step of program verification voltage of the cell (step S703). Significantly, the difference between the program verify voltage and the upper limit of the low threshold voltage distribution of memory cells can be as small as 600mV. In addition, the sequence of step S701 and step S703 cannot be changed.

FIG. 8 is a flow chart of steps of a method for reading a storage unit of a memory according to an embodiment of the present invention. In another embodiment of the present invention, as shown in FIG. 8 , the first current ( Step S801). Then, in step S803, the first current and the first reference current about the first bit line voltage and the word line voltage applied to the memory cell 100 are respectively analog-to-digital converted into a first current digital value and a first reference digital value , to record. In step S805, the first current digital value and the first reference digital value are compared to determine the programming state of the data storage area to be read. When the first current digital value is greater than the first reference digital value, the data storage area to be read is determined to be in an unprogrammed state (step S807 ). On the other hand, when the first current digital value is smaller than the first reference digital value, it cannot be determined whether the data storage area is in a programmed state or an unprogrammed state with the second bit effect.

In addition, as shown in FIG. 8, in step S809, when the first current digital value is smaller than the first reference digital value, a second bit line voltage (different from the first bit line voltage) is applied to the source/drain region 104 (away from the data storage area to be read), and the word line voltage remains the same to detect the second current. Then, in step S811, analog-to-digital conversion of the second current and the second reference current about the second bit line voltage and the word line voltage applied to the memory cell 100 into a second current digital value and a second reference digital value, respectively , to record. In addition, in step S813, the programming state of the data storage area to be read is determined. That is, the difference between the second current digital value and the first current digital value is compared with the reference digital value variation generated by different bit line voltages applied to the memory cell 100 . If the difference between the second current digital value and the first current digital value is less than or equal to the difference between the first reference digital value and the second reference digital value, then it is determined that the data storage area to be read is in a programming state (step S815 ). If the difference between the second current digital value and the first current digital value is greater than the difference between the first reference digital value and the second reference digital value, then it is determined that the data storage area to be read is an unreadable data storage area with a second bit effect. programming state (step S807).

In the present invention, when data is read from each data storage area of the memory cell, the performance of the threshold voltage distribution of the target data storage area under different bit line voltages is used to determine the programming state of the target data storage area. Therefore, even if the operating margin is small or even non-existent, when the detection current is smaller than the reference current, the data storage area with the bit "1" and the data storage area with the bit "0" under the second bit effect can be corrected. District distinction. Therefore, operating margin will no longer be an obstacle to shrinking the size of memory cells. In addition, second bit effects on memory cell operations are also mitigated. In addition, since the second bit effect is reduced and the operation margin is small, the programming speed is increased, and the time for programming memory cells is shortened.

Although the present invention has been disclosed as above with the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be determined by the scope defined in the claims.

Claims (16)

1. the method for an operation store unit, this storage unit has two region of data storages, it is characterized in that, and the method for this operation store unit comprises:

Apply one first electric current that one first bit-line voltage to this storage unit detects this storage unit; And

If this first electric current is less than one first reference current, apply one second electric current that one second bit-line voltage to this storage unit detects this storage unit, and one second difference between one first difference between this first electric current and this second electric current and this first reference current and one second reference current relatively is to judge the state of this region of data storage.

2. the method for operation store according to claim 1 unit, it is characterized in that, when this first difference during greater than this second difference, this region of data storage is judged as a programming state not, and when this first difference was less than or equal to this second difference, this region of data storage was judged as a programming state.

3. the method for operation store according to claim 1 unit is characterized in that this second bit-line voltage is greater than this first bit-line voltage.

4. the method for operation store according to claim 1 unit is characterized in that, equals one second word line voltage for detection of this second electric current for detection of one first word line voltage of this first electric current.

5. the method for operation store according to claim 1 unit is characterized in that an operation window of this storage unit is 600mV.

6. the method for operation store according to claim 1 unit is characterized in that, more comprises:

Define a upper limit of the low threshold voltage distribution of this storage unit; And

Voltage is confirmed in a programming that defines this storage unit.

7. the method for operation store according to claim 6 unit is characterized in that, this programming confirms that the difference between this upper limit of voltage and the distribution of this low threshold voltage is 600mV.

8. the method for operation store according to claim 1 unit is characterized in that, when this first electric current during greater than this first reference current, this region of data storage is judged as a programming state not.

9. the method for operation store according to claim 1 unit is characterized in that, more comprises:

After detecting this first electric current, it is the form of digital value that this first electric current and this first reference current are simulated respectively to digital conversion; And

After detecting this second electric current, it is the form of digital value that this second electric current and this second reference current are simulated respectively to digital conversion.

10. a storage arrangement is characterized in that, comprising:

One storer has a plurality of storage unit, and each storage unit has two region of data storages;

One testing circuit, be used for during a read step, applying one first electric current that one first bit-line voltage to these a plurality of storage unit detect these a plurality of storage unit, if and this first electric current applies one second electric current that one second bit-line voltage to these a plurality of storage unit detect these a plurality of storage unit during less than first reference current; And

One controller, be used for each storage unit is carried out this read step, and be used for relatively one first difference between this first electric current and this second electric current and one second difference between this first reference current and one second reference current, to judge the state of this region of data storage.

11. storage arrangement according to claim 10 is characterized in that, this second bit-line voltage is different from this first bit-line voltage.

12. storage arrangement according to claim 10 is characterized in that, this second bit-line voltage is greater than this first bit-line voltage.

13. storage arrangement according to claim 10 is characterized in that, equals one second word line voltage for detection of this second electric current for detection of one first word line voltage of this first electric current.

14. storage arrangement according to claim 10 is characterized in that, an operation window of these a plurality of storage unit is 600mV.

15. storage arrangement according to claim 10 is characterized in that, when this first electric current during greater than this first reference current, this region of data storage is judged as a programming state not.

16. storage arrangement according to claim 10, it is characterized in that, more comprise an analog-to-digital converter, be used for after detecting this first electric current this first electric current and this first reference current are converted to respectively the form of digital value, and the form that after this second electric current of detection, this second electric current and this second reference current is converted to respectively digital value.

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