TWI385513B - Testing device for simulating storage devices and testing method thereof - Google Patents

Description

Test device simulating multiple storage devices and test method thereof

The present invention relates to a test device, and more particularly to a test device for simulating a plurality of storage devices and a test method therefor.

In the production process of the motherboard of the computer device, in order to test whether the serial interface of the motherboard (Serial Advanced Technology Attachment, SATA) hard disk connector function is normal, many devices and consumables are used for the SATA hard disk connector of the motherboard. carry out testing.

As shown in FIG. 1, the motherboard 101 is provided with four SATA hard disk connectors 102a to 102d. When testing the SATA hard disk connectors 102a to 102d, it is necessary to connect the four SATA hard disks 103a to 103d to the SATA hard disk connectors 102a to 102d of the motherboard 101.

Of course, the motherboard 101 is also connected with components necessary for testing, such as CPU, memory, hard disk, etc., which are necessary for running the test program.

However, current testing methods have a number of disadvantages. For example: (1) During the test, the connector of the SATA hard disk is easily damaged due to frequent insertion and removal, and the new SATA hard disk must be replaced, which will greatly increase the testing cost. (2) During the process of moving and inserting and removing, the SATA hard disk may easily cause damage to the hard disk due to collision. (3) SATA physical hard disk is a magnetic medium. If it is suddenly powered off or in a strong magnetic field, it is easy to cause track damage and it is not easy to repair. (4) When testing, how many SATA connectors are on the motherboard, how many physical hard disks are needed, and each physical hard disk takes up a certain amount of space, so if the motherboard has multiple SATA connectors, then This requires a lot of space for testing and the need to purchase multiple SATA hard drives to increase test costs.

The invention provides a test device for simulating a plurality of storage devices and a test method thereof, which can solve the above problems.

The present invention provides a test device for simulating a plurality of storage devices for testing a plurality of first storage device connectors of a computer device, the computer device transmitting a plurality of first access commands to the test device through the first storage device connectors To simulate performing an access operation on a plurality of access segments of the storage devices. The test device includes a plurality of second storage device connectors, a control unit, and a test access segment. The plurality of second storage device connectors are configured to couple the first storage device connectors and receive the first access commands. The control unit is coupled to the second storage device connectors. The test access segment is coupled to the control unit, and is configured to simulate the access segments, such that the control unit responds to the first access commands and performs the storing of the first access commands on the test access segments. Take the operation.

The present invention also provides a test method for testing a plurality of first storage device connectors of a computer device, the computer device transmitting a plurality of first access commands through the first storage device connectors to simulate the storage devices Multiple access segments perform an access operation. The testing method includes: receiving the first access instructions; and responding to the first access instructions to execute the first access instructions on a test access segment for simulating the access segments Access operation.

The invention has the beneficial effects that the memory is used to provide an access section, and the memory has the characteristics of fast reading and writing speed with respect to the hard disk, so the testing speed of the invention is fast. In addition, compared with hard disks, the memory is small in size, good in vibration resistance, and not easily damaged, so the production test cost can be reduced.

The above and other objects, features and advantages of the present invention will become more <RTIgt;

2 is a schematic view of a test apparatus in accordance with a preferred embodiment of the present invention.

The testing device 200 provided in this embodiment is used to test a plurality of first storage device connectors 302a, 302b of the motherboard 301 of the computer device 300. In theory, a plurality of first storage device connectors 302a, 302b should be coupled to a plurality of corresponding storage devices during testing. In this embodiment, the storage device is a hard disk. Preferably, the storage device is a SATA hard disk. However, the present invention is not limited thereto. In this embodiment, the first storage device connectors 302a, 302b are SATA hard disk connectors, and are adapted to be connected to a SATA hard disk. The SATA signal sent by the motherboard 301 can be transmitted to the SATA hard disk connected to the SATA hard disk connector via the SATA hard disk connector.

In this embodiment, the motherboard 301 to be tested is provided with a central processing unit (CPU), a memory, a display card, etc., in addition to the first storage device connectors 302a, 302b. In addition, the motherboard 301 is also connected to a power supply, a display, and a hard disk. The hard disk stores a test program for controlling the computer device 300 to issue an access command and the matching test device 200 to determine the first storage device. Whether the connectors 302a, 302b are good. In other embodiments, the test program may also be stored in the memory on the motherboard 301, which is not limited by the present invention.

In this embodiment, the plurality of first storage device connectors 302a, 302b are connected to the testing device 200 provided in the embodiment, and the testing device 200 is used to simulate a plurality of storage devices, so that the computer device 300 still considers A plurality of first access commands can be sent to the plurality of storage devices through the first storage device connectors 302a, 302b to access the plurality of access segments of the plurality of storage devices, but in fact, The plurality of first access commands issued by the computer device 300 are sent to the test device 200 through the first storage device connectors 302a, 302b to simulate performing access operations on the plurality of access segments of the storage devices.

In this embodiment, the first access instruction includes a plurality of write instructions or a plurality of read instructions, that is, the first access instruction may be a write instruction or a read instruction. In this embodiment, the above access operation may be a write operation or a read operation.

In addition, each access instruction may be an access operation to an access sector or a plurality of access segments of a particular physical storage device (eg, a hard disk), and each access segment has a corresponding access address, and each access instruction also has an access address (including a start address and an end address), so that the controller of the storage device (hard disk) can follow the access command The access address is used to access a particular access segment. In this embodiment, for convenience of description, the access address of the first access instruction and the address of the access section of the specific physical storage device are referred to as a first access address.

The testing device 200 provided in this embodiment includes a plurality of second storage device connectors 201a, 201b, an interface conversion unit 202, a control unit 203, and a memory 204. In this embodiment, the control unit 203 and the memory 204 are integrated in a programmable logic gate array (FPGA) 205. In other embodiments, the control unit 203 and the memory 204 may also be separate components. In addition, the second storage device connectors 201a, 201b, the interface conversion unit 202, and the programmable logic gate array wafer 205 are disposed on the same circuit board 206.

The plurality of second storage device connectors 201a, 201b are configured to couple the first storage device connectors 302a, 302b and receive one or more first access commands issued by the computer device 300. The second storage device connectors 201a, 201b and the first storage device connectors 302a, 302b can be coupled by a connecting wire (for example, a SATA cable).

In the present embodiment, the second storage device connectors 201a, 201b can respectively and simultaneously connect the first storage device connectors 302a, 302b to simultaneously detect whether the first storage device connectors 302a, 302b are good. In this embodiment, the second storage device connectors 201a, 201b are SATA connectors. In other embodiments, the second storage device connectors 201a, 201b may also be connectors of SAS connectors or other storage devices.

The interface conversion unit 202 is coupled to the second storage device connector 201a, 201b and the control unit 203, respectively, and the control unit 203 is coupled to the interface conversion unit 202 and the memory 204, respectively. In this embodiment, the memory 204 is a static random access memory (SRAM). In other embodiments, the memory 204 may also be a non-volatile memory, but the invention is not limited thereto. The memory 204 has a test access section 2041, and the test access section 2041 can be used to simulate one or more access sections in at least one storage device, wherein the test access section 2041 has a second Access address.

The interface conversion unit 202 is configured to receive a plurality of first access instructions from the second storage device connectors 201a, 201b, and to convert the plurality of first access commands into a plurality of second access commands, where An access instruction is a serial interface instruction (for example, a SATA interface instruction), and the second access instruction is a parallel interface instruction (for example, an ATA interface instruction). In other embodiments, the interface conversion unit 202 can be included in the control unit 203, which is not limited by the present invention.

The control unit 203 is configured to respond to the first access instruction issued by the computer device 300 to simulate an access operation for executing the first access instruction to the test access segment.

As described above, the first access command issued by the computer device 300 is an access operation to a specific physical storage device (eg, a hard disk). Although the interface conversion unit 202 converts the first access instruction into the second access instruction, the first access address in the first access instruction is retained.

The control unit 203 receives the second access instruction provided by the interface conversion unit 202, and the control unit 203 maps the first access address in the second access instruction to the second access address of the test access segment 2041. The computer device 300 is caused to perform an access operation on the access segment of the storage device, and is configured to perform an access operation on the test access segment 2041 according to the second access address.

Figure 3 is a flow chart showing the test method of the preferred embodiment. For the description of FIG. 3, please refer to FIG. 2 together.

In step S305, the computer device 300 executes a test program stored in a primary hard disk and sends a first access command to the test device 200 through the first storage device connector 302a.

In step S310, the interface conversion unit 202 is configured to receive the first access instruction from the second storage device connector 201a, and convert the first access instruction into a plurality of second access commands of different formats but the same content. .

In step S315, the control unit 203 executes the second access instruction and maps the first access address in the second access instruction to the second access address to access the test access segment 2041. Operation, for example: writing a test data.

In step S320, the computer device 300 sends a first access command, such as reading data, to the test device 200 through the first storage device connector 302a to read the previously written test access segment 2041. data. After the computer device 300 reads the data, the computer device 300 compares whether the read data is consistent with the previously written data. If they match, the first storage device connector 302a is good. If not, the representative device A storage device connector 302a may be problematic.

The testing of the other first storage device connector 302b is similar to that described above.

In summary, the test apparatus provided by the preferred embodiment of the present invention simulates all storage space of a real hard disk by using a storage space of an access section of the memory according to the working principle of the hard disk, that is, all the different contents in the hard disk. The access segment of the address maps to a specific access segment of the above memory. In this way, the storage device connector of the computer device tests the read and write alignment of the access segments of different addresses, and actually operates on the same specific access segment. Thereby, the test speed of the present invention is fast, and the space required for testing is small, and the production test cost can be reduced without purchasing too many hard disks.

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

101. . . motherboard

102a, 102b, 102c, 102d. . . SATA hard drive connector

103a, 103b, 103c, 103d. . . SATA hard drive

200. . . Test device

300. . . Computer device

301. . . motherboard

302a, 302b. . . First storage device connector

201a, 201b. . . Second storage device connector

202. . . Interface conversion unit

203. . . control unit

204. . . Memory

205. . . Programmable logic gate array chip

206. . . Circuit board

2041. . . Test access section

S305, S310, S315, S320. . . step

Figure 1 shows a schematic diagram of a prior art test apparatus.

2 is a schematic view of a test apparatus in accordance with a preferred embodiment of the present invention.

3 is a flow chart showing a test method of a preferred embodiment of the present invention.

200. . . Test device

300. . . Computer device

301. . . motherboard

302a, 302b. . . First storage device connector

201a, 201b. . . Second storage device connector

202. . . Interface conversion unit

203. . . control unit

204. . . Memory

205. . . Programmable logic gate array chip

206. . . Circuit board

2041. . . Test access section

Claims (12)

A test device for simulating a plurality of storage devices for testing a plurality of first storage device connectors of a computer device, the computer device transmitting a plurality of first access commands to the test device through the first storage device connectors Performing an access operation for simulating a plurality of access segments of the storage devices, the testing device includes: a plurality of second storage device connectors for coupling the first storage device connectors, and receiving The first access command; a control unit coupled to the second storage device connectors; and a test access segment coupled to the control unit and configured to simulate the access segments such that The control unit is responsive to the first access instructions and performs an access operation of the first access instructions to the test access segment. The test device of claim 1, wherein the access segments each have a first access address, the test access segment has a second access address, and the control unit maps the The first access address of the first access instruction to the second access address, so that the test access segment performs the access operation of the first access instruction. The test device of claim 1, further comprising an interface conversion unit, respectively coupled to the second storage device connector and the control unit, and configured to convert the first access commands into multiple Second access instruction. The test device of claim 3, wherein the first access instructions are serial interface instructions, and the second access instructions are parallel interface instructions. The test device of claim 1, wherein the first accesses The instructions include a plurality of write instructions or a plurality of read instructions. The test apparatus of claim 1, wherein the test access section and the control unit are integrated in a programmable logic gate array wafer. A test method for testing a plurality of first storage device connectors of a computer device, the computer device transmitting a plurality of first access commands through the first storage device connectors to simulate a plurality of storage devices The access segments perform an access operation, the test method includes: receiving the first access instructions; and responding to the first access instructions to store a test for simulating the access segments The fetch section performs an access operation of the first access instructions. The test method of claim 7, wherein the access segments each have a first access address, and the test access segment has a second access address. The test method of claim 8, wherein the step of responding to the first access instructions further comprises: mapping the first access address of the first access instruction to the second Accessing an address for performing an access operation of the first access instructions in the test access section. The test method of claim 7, further comprising: converting the first access instructions into a plurality of second access instructions, wherein the first access instructions are serial interface instructions, and the The second access instruction is a parallel interface instruction. The test method of claim 7, wherein the first access The instructions include a plurality of write instructions or a plurality of read instructions. The test method of claim 7, wherein the step of performing an access operation on the test access segments comprises writing data to the test access segments, and reading writes to the tests Accessing the data of the segment, the testing method further includes: determining whether the written data is consistent with the read data to determine whether the first storage device connectors are normal.