TWI381513B - Wafer stack package structure and its preparation method - Google Patents

Description

Wafer stack package structure and its preparation method

The invention relates to a wafer stacking package structure and a manufacturing method, in particular to a wafer stacking package structure and a manufacturing method thereof which can reduce the cost and simplify the process.

There are roughly two ways to install a three-dimensional package, namely, package on package (PoP) and package in package (PiP). The PoP package is a typical three-dimensional package, which is formed by attaching and testing two independent packages to be surface-bonded.

However, the current PoP package structure must be completed after the individual packages are completed, and then the ball placement and stacking are combined, which is time-consuming and labor-intensive. Moreover, the thickness of the package structure after lamination is large, which cannot meet the current demand for light and thin electronic products.

In order to solve the above problems, one of the objects of the present invention is to provide a wafer stack package structure and a method for fabricating the same, which utilizes a recess structure on the bottom surface of the upper wafer to cover the underlying flip chip, so that the stacked structure can effectively reduce the package. Thickness and cost of use of the substrate and conductive balls.

In order to achieve the above object, an embodiment of the present invention provides a wafer stack package structure including: a substrate; a flip chip is disposed on the substrate and electrically connected to the substrate; and a bottom surface of the wafer has a recess for the cover Providing a flip chip, wherein a spacer member is disposed between the wafer and the flip chip to cover the flip chip and a portion of the substrate and to fix the wafer on the flip chip; and an electrical component is electrically connected to the wafer The active surface and the substrate.

In order to achieve the above object, an embodiment of the present invention provides a method for fabricating a wafer stack package structure, comprising: providing a substrate. A flip chip is disposed on the substrate and electrically connected to the substrate. A wafer is provided in which the bottom surface of the wafer has a recess. A spacer member is disposed on the upper surface of the flip chip. The stacked wafers are stacked on a flip chip, wherein the recesses are disposed outside the flip chip. The wafer is pressed to fill the spacer member in the recess to cover the flip chip and a portion of the substrate. And electrically connecting the wafer and the substrate by using an electrical component.

The detailed description is as follows, and the preferred embodiment is not intended to limit the invention.

Please refer to FIG. 1A to FIG. 1D. FIG. 1A to FIG. 1D are schematic cross-sectional views showing a manufacturing method of a wafer stack package structure according to an embodiment of the present invention. First, referring to FIG. 1A, a substrate 10 is provided. A flip chip 20 is disposed on the substrate 10, and the substrate 10 is electrically connected to the flip chip 20. Next, referring to FIG. 1B, a spacer member 30 is disposed on the upper surface of the flip chip 20 by a dispensing or coating technique, wherein the spacer member 30 may be an epoxy resin, a B-stage cured adhesive or other suitable coating material. Further, a wafer 40 is provided. As shown in FIG. 1C, the bottom surface of the wafer 40 has a recess 42. Next, the wafer 40 is stacked on the flip chip 20 such that the recess 42 is overlaid on the flip chip 20. Applying a pressure to the wafer 40 fills the spacer member 30 in the recess 42 to cover the flip chip 20 and a portion of the substrate 10, and adhere the wafer 40 to the substrate 10, and electrically insulating the wafer 40 and flip chip. Wafer 20. Next, as shown in FIG. 1D, the wafer 40 is wire-bonded, and the wafer 40 and the substrate 10 are electrically connected by an electrical component 50. Finally, the wafer 40, the electrical component 50, and a portion of the substrate 10 are coated with an encapsulant 60 (eg, comprised of epoxy) to form a wafer stack package structure as shown in FIG. 1E.

Following the above, as shown in FIG. 1E, a plurality of conductive balls 70 are disposed under the substrate 10 to electrically connect the wafer stack package structure to the external device.

Continuing to refer to FIG. 1E , the completed wafer stack package structure includes: a substrate 10; a flip chip 20 is disposed on the substrate 10 and electrically connected to the substrate 10; and a wafer 40 has a groove 42 on a bottom surface thereof. The flip chip 20 is covered, and a spacer member 30 is disposed between the wafer 40 and the flip chip 20 to cover the flip chip 20 and a portion of the substrate 10, and the wafer 40 is fixed on the flip chip 20; And an electrical connection component 50 electrically connects the wafer 40 and the substrate 10. Furthermore, an encapsulant 60 covers the wafer 40, the electrical component 50 and a portion of the substrate 10. And a plurality of conductive balls 70 are disposed under the substrate 10 to facilitate electrical connection between the wafer stack package structure and the external device.

In another embodiment, as shown in FIG. 2A, the size of the groove 42 of the upper wafer 40 is premised on covering the size of the underlying flip chip 20, and the shape is not limited to the closed groove, and the groove 42 is more There is at least one opening 43, as shown in FIGS. 2B, 2C, 2D, 2E, and 2F.

In one embodiment of the present invention, a recess is formed on the bottom surface of the upper wafer, and the space under the recess can accommodate other wafers required for the package (in this embodiment, a flip chip, but not limited), which is effective. Use space to solve the problem that the total height of the PoP package structure is too thick. In addition, the use of the substrate and the conductive ball when a plurality of packages are stacked can be reduced, which greatly reduces the production cost. Furthermore, after simplifying the process, the problem of the alignment of the upper package and the lower package conductive ball in the PoP package structure can be improved.

In summary, a wafer stack package structure and a method for fabricating the same according to an embodiment of the present invention utilize a recess structure formed on a bottom surface of an upper wafer to cover a lower layer flip chip. The stacked structure can effectively reduce the thickness of the package and the substrate and the substrate. The cost of using conductive balls.

The embodiments described above are merely illustrative of the technical spirit and the features of the present invention, and the objects of the present invention can be understood by those skilled in the art, and the scope of the present invention cannot be limited thereto. That is, the equivalent variations or modifications made by the spirit of the present invention should still be included in the scope of the present invention.

10. . . Substrate

20. . . Flip chip

30. . . Spacer member

40. . . Wafer

42. . . Groove

43. . . Opening

50. . . Electrical component

60. . . Encapsulant

70. . . Conductive ball

1A, 1B, 1C, 1D, and 1E are schematic cross-sectional views showing a method of fabricating a wafer stack package structure according to an embodiment of the present invention.

2A, 2B, 2C, 2D, 2E and 2F are schematic structural views of a groove according to an embodiment of the present invention.

10. . . Substrate

20. . . Flip chip

30. . . Spacer member

40. . . Wafer

42. . . Groove

50. . . Electrical component

60. . . Encapsulant

70. . . Conductive ball

Claims (10)

A wafer stack package structure comprising: a substrate; a flip chip, disposed on the substrate and electrically connected to the substrate; a wafer having a bottom surface having a recess for covering the flip chip a spacer member is disposed between the wafer and the flip chip for covering the flip chip and a portion of the substrate and fixing the wafer on the flip chip; and an electrical component, electrically connected The active surface of the wafer and the substrate. The wafer stack package structure of claim 1, wherein the flip chip and the wafer are electrically insulated from each other by the spacer member. The wafer stack package structure of claim 1, further comprising an encapsulant covering the wafer, the electrical component and a portion of the substrate. The wafer stack package structure of claim 1, further comprising a plurality of conductive balls disposed under the substrate. The wafer stack package structure of claim 1, wherein the groove has at least one opening. A method for manufacturing a wafer stack package structure, comprising: providing a substrate; providing a flip chip, disposed on the substrate and electrically connected to the substrate; providing a wafer, wherein the bottom surface of the wafer has a groove; and a spacer member is disposed On the upper surface of the flip chip; stacking the wafer on the flip chip, wherein the recess is overlying the flip chip; pressing the wafer to fill the spacer member in the recess, thereby encapsulating Covering the flip chip and a portion of the substrate; and electrically connecting the wafer and the substrate with an electrical connection component. The method of fabricating a wafer stack package structure according to claim 6, wherein the step of disposing the spacer member is a dispensing technique. The method of fabricating a wafer stack package structure according to claim 6, wherein the step of disposing the spacer member is a coating technique. The method for fabricating a wafer stack package structure according to claim 6, further comprising coating the wafer, the electrical connection component and a portion of the substrate with an encapsulant to form a wafer stack package structure. The method for fabricating a wafer stack package structure according to claim 6, further comprising setting a plurality of conductive balls under the substrate.