1301665 122〇6twf.doc/006 九、發明說明·· 【發明所屬之技術領域】 本發明是有關於一種線路載板及其電氣封裝結構，且 特別是有關於一種具有被動元件電極平面之線路載板及其 電氣封裝結構。 【先前技術】 近年來，隨著電子技術的日新月異，高科技電子產業 的相繼問世，使得更人性化、功能更佳的電子產品不斷地 推陳出新，並朝向輕、薄、短、小的趨勢設計。目前在電 路佈設方面，線路載板（circuit carrier)是經常使用的構 裝元件，例如是印刷電路板（PCB)或晶片載板（chip carrier)等線路載板。常見之線路載板主要是由多層圖案 化線路層及多層介電層交替疊合所構成，其中介電層配置 =任二相鄰之圖案化線路層之間，而圖案化線路層可藉由 貝穿介電層之導通孔（Plated Through Hole，PTH)或導電 孔（via)而彼此電性連接。由於線路載板具有佈線細密、 組裝緊湊以及性能良好等優點，因此線路載板係已廣泛地 應用於電氣封裝結構（package structure)。此外，當訊號 在線路載板之間傳遞時，可將電容等被動元件配置於線路 =板上，來有效抑制訊號在線路之間傳遞時的電感性耦 a，用以減少訊號在切換時所產生之雜訊串音干擾（cr〇ss talk)，並維持訊號之傳輸品質。 、一 flA繪示習知一種線路載板與組裝之電子元件的俯 視不意圖。請參考圖1A，線路載板1〇〇具有多個電子元 1301 顿 66twf.doc/006 Γ: :〇 ’其配置於-基板110的表面上。1中，電 2件ΗΜ例如為晶片’其配置於基板ug之晶片、接人區 “上’而電子元件13〇例如為電容、電感或電阻^被 動兀件（passive component )，装配罟^v 其 4 元件接合區13〇a上。 、配置於基板110之被動 此外’請參考圖1B及圖lc，苴中 _ ^被動元件接合區的俯視示意圖， 干胃不=^ =;對動元件沿】·ι線的剖面示意圖。、= 被動70件電極平面112、114係 _ β中 ，合區丨施的表面，並由最外層之; ’而一防銲層120覆蓋於基板110之表曰面1301665 122〇6twf.doc/006 IX. OBJECT DESCRIPTION OF THE INVENTION · TECHNICAL FIELD The present invention relates to a line carrier and an electrical package structure thereof, and more particularly to a line carrying a passive element electrode plane Board and its electrical package structure. [Prior Art] In recent years, with the rapid development of electronic technology, the high-tech electronics industry has emerged, making more humanized and functional electronic products continue to evolve, and are designed toward light, thin, short, and small trends. Currently, in terms of circuit layout, a circuit carrier is a frequently used component such as a printed circuit board (PCB) or a chip carrier such as a chip carrier. The common circuit carrier is mainly composed of a plurality of patterned circuit layers and a plurality of dielectric layers alternately stacked, wherein the dielectric layer configuration is between two adjacent patterned circuit layers, and the patterned circuit layer can be The bumps are electrically connected to each other by a through hole (PTH) or a via (via) of the dielectric layer. Since the line carrier has the advantages of fine wiring, compact assembly, and good performance, the line carrier has been widely used in electrical package structures. In addition, when the signal is transmitted between the line carriers, a passive component such as a capacitor can be disposed on the line=board to effectively suppress the inductive coupling a when the signal is transmitted between the lines, so as to reduce the signal when switching. Generates noise crosstalk (cr〇ss talk) and maintains the transmission quality of the signal. A flA shows a conventional view of a line carrier and assembled electronic components. Referring to FIG. 1A, the line carrier board 1 has a plurality of electronic components 1301 66 66 twf.doc / 006 : : ’ ' disposed on the surface of the substrate 110. In the first embodiment, the electric device is, for example, a wafer which is disposed on the wafer of the substrate ug, the upper portion of the substrate, and the electronic component 13 is, for example, a capacitor, an inductor or a resistor, a passive component, and is assembled. The four-element junction area 13〇a is disposed on the substrate 110. In addition, please refer to FIG. 1B and FIG. 1c, and the schematic diagram of the passive component junction area is omitted, and the dry stomach is not =^=; 】·The cross-section of the ι line., = Passive 70 pieces of electrode plane 112, 114 series _ β, the surface of the joint area, and the outermost layer; 'and a solder mask 120 covering the surface of the substrate 110 surface
Marefined,s；Dr；^ 元=極平面m、114係可作為線路载板^ $ 一被動元件130之接點。 电【生運接 直声，被動元件130具有多個電極132、134， 之被動元料財面„2、丨14料似載板7 將這些電極！32、134銲接至這些被動元件電極平二2在 114的過程中’射藉由助銲劑㈤χ)來增加 126的接合性。此外，在被動元件、厂 之後，殘留於、祕«⑽上__=^由路—载 13〇吸_06 驟加2除’之後被動元件m之表面還可以一封膠128 加以U復，以構成一電氣封裝結構102。 ,1C中，由於被動元件13〇係橫跨於線路載板11〇 之兩被動讀電極平面112、114之間，而被動元件130 與防銲層120之間的間隙1〇8過小，導致殘留在被動元件 130與防銲層12〇之間的助鮮劑無法有效地清除。此外， 在被動το件130組裝於線路載板之後，若具有被動元 件130之線路載板⑽再次經過高溫製程，例如迴鲜 (refl〇W)時，兩鲜料124、126可能會流入被動元件13〇 之下方的縫隙109 (其形成於封膠128及防銲層12〇之 間），因而導致兩被動元件電極平φ 112、114發生短路， 進而導致被動元件130失效，此即所謂的通道效應。 為了解決上述的問題，習知技術乃是在二被動元件電 極平面112、114之間的防銲層12〇形成一狹長狀之第二 防銲開π (未繪示），崎於有效地清洗殘留於被動元件 130與防銲層120之間的助銲劑，進而降低兩銲料124、126 流入縫隙109的機率。此外，由於上述之第二防銲開口更 可增加縫隙109之沿兩被動元件電極平面112、114的路 徑長度，使得兩銲料124、126在流入縫隙1〇9之後仍不 易相互連接。然而，在防銲開口之對位精度上，由於狹長 之第二防銲開口分別與其他防銲開口 122a、122b之間的 間距相當地小，所以必須使用對位精度較高之製程設備來 製作第二防銲開口，因而導致線路載板11〇之製作成本的 增加。此外，當兩被動元件電極平面112、114之間的間 1301665 12266twf.doc/006 距D朝微間距（fine pitch)之趨勢發展時，製作上述之 狹長的第二防銲開口其困難度將相對增加，甚至會產生兩 防銲開口 122a、122b之間距D不以形成第二防銲開口 等問題。因此，在防制習知之通道效應導致被動元件13〇 失效的作法上必須尋求其他解決之道。 【發明内容】 、據此，本發明的目的是提供一種線路基板，用以改善 被動元件輝接至線路載板之後所產生之通道效應。 此外，本發明的目的是提供一種電氣封裝^構，用以 改善被動元件銲接至線路載板之後所產生之通道效應。 為達本發明之上述目的，本發明提出一種線路載板， 適於承載一被動元件，而被動元件具有多數個電極。此線 路載板至少包括一基板、多數個被動元件電極平面、一防 鮮層以及至少-被動元件。其巾，每—被動元件具有多數 個電極；被動元件電極平面設置於基板之表面，以供電性 接合所對應之被動元件；該防銲層係覆蓋於基板之表面， 並具有至少-被動元件防銲開口，其特徵在於每—被動元 件防銲開π只對應到-勸元件，並且每—被動元件防鲜 開口係暴露崎對應之獅元件所接合之錄錄動元件 電極平面之部分表面。而本發明所提出—種電氣封裝結構 即疋包含上述線路载板之封裝體。 ^ 、基於上述，本發明因被動元件與基板之間無防銲層而 形成較大的随，故在將被動元件之電極分別銲接至基板 之兩被動元件電極平面之後，殘留於㈣元件及基板之間 9 1301665 12266twf.doc/006 ^助銲劑可輕易地清除，故可降低習知之通道效應，並提 鬲被動元件於後續高溫製程之組裝良率。 為讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： 【實施方式】 圖2A繪示本發明之一種線路載板與組裝之電子元件 的俯視示意圖。請參考圖2A，線路載板200具有多個電 子元件204、230，其配置於一基板210的表面上。其中， 電子元件204例如為主動式ic晶片，其配置於基板21〇 之晶片接合區204a上，而電子元件23〇例如為電容、電 2或電阻等被動元件，其配置於基板21〇之一被動元件接 合區23〇a上。在本實施例中，被動元件接合區230a例如 與晶片接合區204a同樣位在基板210的上表面，當鈥， 被動元件接合區230a亦可位於基板21〇之下表面（未繪 示），並與晶片接合區2〇4a位在不同的表面上。並且，基 板上亦可配置多數個被動元件，而本實施例僅以一個被^ 、明多考圖2B，其緣示本發明一較佳實施例之一種、彳 路載板的俯視示意圖。本實施例中是以具有兩個電極的; 動疋件為例。線路载板200具有一基板21〇、一第一被3 元件電極平面212、-第二被動元件電極平面214以及_ 22Γ首先’第一、第二被動元件電極平面212、21 刀另J疋電極平面以及一接地平面，配置於基板^ 1301665 12266twf.d〇c/006 ^同-表面’並延伸於被動轉接 層220則覆蓋於基板21()之表 3= ==，此防銲開口 222暴露出第—、第二被動元件電 件14之部分表面。值得注意的是，二被動元 準产二：二2:2:露出面積應保持一致，若因對位精 ，度使其露“積不—致時，财考慮使用對位精 ^句之衣程稍來製作被動元件防銲開口如。並且， 本發明特徵即在於每-被航件只對應到—個防鲜開口。 此外’在圖2B t ’當第-、第二被動元件電極平面 _、214之間的間距D1、缩小，以朝微間距之趨勢發展時， 同樣可利用對位精度較低的製程設備來製作被動元件防銲 開口 222。因此’第一實施例之防銲開口 222將不會受到 被動元件電極平面212、214之間距m縮小的影響而增 加被動7G件防鮮開Π 222之製作的困難度，此時仍可使用 對位精度較低之製程設備來製作被動元件防銲開口 222。 一 1請同時參考圖2C以及圖2D，其分別繪示本發明另 了車又佳實施例之一種線路載板的俯視示意圖。本實施例中 同樣以具有兩個電極的被動元件為例，而第一、第二被動 兀件電極平面212、214係配置於基板210之表面，且防 銲層220則覆蓋於基板21〇之表面，並具有一被動元件防 銲開口 222，此防銲開口 222暴露出第一、第二被動元件 電極平面212、214之部分表面。與上述實施例不同的是， 為避免二被動元件電極平面212、214因對位精準度限制 而使其露出面積不一致，特別於每一被動元件電極平面 11Marefined, s; Dr; ^ element = polar plane m, 114 series can be used as the contact of the line carrier ^ $ a passive component 130. The electric transmission is connected to the direct sound. The passive component 130 has a plurality of electrodes 132 and 134, and the passive element material „2, 丨14 is like a carrier plate. 7 These electrodes! 32, 134 are soldered to these passive component electrodes. 2 In the process of 114, 'by flux (5) χ) to increase the bondability of 126. In addition, after the passive components, the factory, the residue, the secret «(10) __=^ by the road - 13 〇 _06 After the addition of 2, the surface of the passive component m can be further re-coated with a glue 128 to form an electrical package structure 102. In 1C, since the passive component 13 is traversed across the line carrier 11 The gap between the electrode faces 112, 114 is read, and the gap 1 〇 8 between the passive component 130 and the solder resist layer 120 is too small, so that the freshener remaining between the passive component 130 and the solder resist layer 12 is not effectively removed. In addition, after the passive carrier 130 is assembled to the line carrier, if the line carrier (10) having the passive component 130 is again subjected to a high temperature process, such as refraction (refl〇W), the two fresh materials 124, 126 may flow into the passive component. a slit 109 below the 13 inch (which is formed between the sealant 128 and the solder resist 12 〇 Therefore, the short circuit of the two passive component electrodes φ 112, 114 is short-circuited, which leads to the failure of the passive component 130, which is called channel effect. In order to solve the above problem, the conventional technique is to use the passive component electrode planes 112, 114. The solder resist layer 12 is formed between a strip-shaped second solder resist π (not shown), which effectively cleans the flux remaining between the passive component 130 and the solder resist layer 120, thereby reducing the solder. 124, 126 the probability of flowing into the slit 109. In addition, since the second solder resist opening described above can increase the path length of the slit 109 along the two passive element electrode planes 112, 114, the two solders 124, 126 are flowing into the slit 1〇9. After that, it is still not easy to connect to each other. However, in the alignment accuracy of the solder resist opening, since the distance between the narrow second solder resist opening and the other solder resist openings 122a, 122b is relatively small, it is necessary to use the alignment accuracy. The high process equipment is used to make the second solder mask opening, thereby causing an increase in the manufacturing cost of the line carrier board 11. In addition, when the two passive component electrode planes 112, 114 are between 1301665 12266twf.doc/006 When the trend from D to fine pitch is developed, the difficulty of making the above-mentioned narrow second solder resist opening will be relatively increased, and even the distance between the two solder resist openings 122a, 122b will not be generated. In order to form a second solder resist opening, etc., therefore, other solutions must be sought in the practice of preventing the conventional channel effect from causing the passive component 13 to fail. [Invention] Accordingly, it is an object of the present invention to provide a The circuit substrate is used to improve the channel effect generated after the passive component is fused to the line carrier. Furthermore, it is an object of the present invention to provide an electrical package structure for improving the channel effect produced after soldering of a passive component to a line carrier. To achieve the above objects of the present invention, the present invention provides a line carrier adapted to carry a passive component and a passive component having a plurality of electrodes. The line carrier board includes at least a substrate, a plurality of passive component electrode planes, a containment layer, and at least a passive component. The towel has a plurality of electrodes for each passive component; the passive component electrode is disposed on the surface of the substrate to electrically connect the corresponding passive component; the solder resist layer covers the surface of the substrate and has at least a passive component The soldering opening is characterized in that each of the passive component solder-proof openings π corresponds to only the component, and each of the passive component's fresh-proof openings exposes a portion of the surface of the recording element electrode plane to which the lion component corresponding to the squid corresponds. The electrical package structure proposed by the present invention is a package including the above-mentioned line carrier. ^ Based on the above, the present invention forms a large follow-up between the passive component and the substrate without the solder resist layer. Therefore, after the electrodes of the passive component are respectively soldered to the planes of the passive component electrodes of the substrate, they remain in the (4) component and the substrate. Between 9 1301665 12266twf.doc/006 ^ Flux can be easily removed, thus reducing the known channel effect and improving the assembly yield of passive components in subsequent high temperature processes. The above and other objects, features, and advantages of the present invention will become more apparent and understood. A schematic top view of an inventive circuit board and assembled electronic components. Referring to FIG. 2A, the line carrier 200 has a plurality of electronic components 204, 230 disposed on a surface of a substrate 210. The electronic component 204 is, for example, an active ic wafer disposed on the wafer bonding region 204a of the substrate 21, and the electronic component 23 is, for example, a passive component such as a capacitor, an electric 2 or a resistor, and is disposed on one of the substrates 21 Passive component land 23a. In the present embodiment, the passive component bonding region 230a is located on the upper surface of the substrate 210, for example, the wafer bonding region 204a. When the substrate bonding region 230a is located, the passive component bonding region 230a may also be located on the lower surface of the substrate 21 (not shown). It is located on a different surface from the wafer bonding region 2〇4a. Moreover, a plurality of passive components can be disposed on the substrate, and the present embodiment is only a schematic view of a carrier board in accordance with a preferred embodiment of the present invention. In this embodiment, a moving member having two electrodes is taken as an example. The line carrier 200 has a substrate 21, a first 3 element electrode plane 212, a second passive element electrode plane 214, and _ 22 Γ first 'first and second passive element electrode planes 212, 21 The plane and a ground plane are disposed on the substrate ^ 1301665 12266 twf.d 〇 c / 006 ^ the same - surface 'and extends over the passive transfer layer 220 over the substrate 21 () Table 3 = = =, the solder resist opening 222 A portion of the surface of the first and second passive component electrical components 14 is exposed. It is worth noting that the two passive elements are expected to produce two: two 2:2: the exposed area should be consistent, if the degree is fine, the degree will make it "not accumulate - when it is time, the financial considerations use the matching fine sentence sentence clothes. The process of making a passive component solder-proof opening is as follows. Moreover, the present invention is characterized in that each of the voyages corresponds to only one anti-fresh opening. Further, in Figure 2B t 'when the first and second passive component electrode planes _ When the distance D1 between the two ends 214 is reduced to a smaller pitch, the passive component solder resist opening 222 can also be fabricated by using a process device having a lower alignment accuracy. Therefore, the solder resist opening 222 of the first embodiment. The difficulty of making the passive 7G anti-fresh opening 222 will not be affected by the reduction of the distance m between the passive component electrode planes 212, 214. At this time, the passive component can be fabricated using the processing equipment with lower alignment accuracy. The soldering prevention opening 222. 1 Please refer to FIG. 2C and FIG. 2D simultaneously, which respectively show a schematic top view of a circuit carrier board according to another preferred embodiment of the present invention. In this embodiment, the passive circuit has two electrodes. Component as an example, and first The second passive element electrode planes 212 and 214 are disposed on the surface of the substrate 210, and the solder resist layer 220 covers the surface of the substrate 21 and has a passive component solder resist opening 222. The solder resist opening 222 is exposed. 1. Part of the surface of the second passive component electrode planes 212, 214. Different from the above embodiment, in order to avoid the two passive component electrode planes 212, 214 having inconsistent exposure areas due to alignment accuracy limitations, especially for each Passive component electrode plane 11
Otwf.doc/006 Γ電二少一開口。如圖2C所示，每-被動元 ，電極千面212、214分別具有二開σ 212a，b、2i4ab， 222之四個㈣區域’使得原本矩形 t出2義少掉二如部分㈣成凸字形 此外’圖2D之每一被動元件電極平面 = ，-長方形之開…、214c，例如平行二^ =2,緣區域，且其長度略大於防銲開口 222之：Otwf.doc/006 ΓElectricity is less than one opening. As shown in FIG. 2C, for each passive element, the electrode faces 212, 214 have two open σ 212a, b, 2i4ab, and four (four) regions of the 222, so that the original rectangle t is less than 2, and the second (four) is convex. In addition to the glyphs of each passive element of Fig. 2D = , - the opening of the rectangle ..., 214c, for example parallel two ^ 2, the edge region, and its length is slightly larger than the solder resist opening 222:
、長又，使仵原本矩形之露出面積因少掉此長方形之開 口而形成較小之露出面積。 =請參考圖m，其緣示目2A之線路載板與被動 兀件石者Π·Π線的剖面示意圖。在本實施例之中，被動 元件23G具有—第—電極232以及-第二電極234，其位 於被動元件防銲開口 222中，且第一電極232卩及第二電 極_234之表面分別藉由銲料224、22ό，而與對應之一被 動元件電極平面212、2M電性及結構性連接。其中，在 將兩電極232、234分別銲接至兩被動元件電極平面212、Long, so that the exposed area of the original rectangle is smaller than the opening of the rectangle to form a smaller exposed area. = Please refer to Figure m, which shows the cross-section of the line carrier and the passive element stone Π·Π line. In this embodiment, the passive component 23G has a first electrode 232 and a second electrode 234, which are located in the passive component solder mask opening 222, and the surfaces of the first electrode 232 and the second electrode 234 are respectively The solders 224, 22 are electrically and structurally coupled to a corresponding one of the passive component electrode planes 212, 2M. Wherein, the two electrodes 232, 234 are respectively soldered to the two passive element electrode planes 212,
21^的過程中，還可藉由助銲劑來增加銲料224、22ό的 接S性。、此外’將被動元件230之兩電極232、234銲接 至線路载板200之兩被動元件電極平面212、214以後， 助1 于劑還可藉由一清洗步驟加以清除，之後被動元件230 之表面還可以一封膠228加以包覆，以構成一電氣封裝結 構 202。 值得注意的是，在圖2E中，在兩電極232、234分 別知接至兩被動元件電極平面212、214之後，由於被動 12 I3〇16261fdoc/006 元件230與基板210之間無防銲層，使得被動元件23〇與 基板210之間的間隙208加大，所以助銲劑在清除時較不 易殘留在被動元件230與基板210之間。因此，當具有被 動元件230之線路載板2〇〇在經歷後續高溫製程（例如迴 知）時，兩銲料224、226將不易流入在封膠228及基板 210所形成的缝隙209，以提高被動元件230於後續高溫 製程之組裝良率。 請參考圖2F，其繪示本發明之一種電氣封裝結構的 剖面示意圖。此電氣封裝結構202主要包括一封裝基板 ❿ 210、至少一主動元件2〇4、至少一被動元件23〇、多數個 被動元件電極平面212、214以及一防銲層22〇。被動元 件電極平面212、214係設置於封裝基板21〇之表面，以 4、電f生接合所對應之被動元件230。此外，主動元件204 例如透過多條導線206而電性連接至封裝基板21〇，或以 覆晶（flip chip)的方式而電性連接至封裝基板21〇。另 外，被動元件230例如是一電容，其位於封裝基板21〇之 表面，且每一被動元件230具有多數個電極232、234。 防銲層220係覆蓋於封裝基板21〇之表面，並具有至少一 被動元件防銲開口 222，其中每一被動元件防銲開口 222 係對應到一被動元件230,並且每一被動元件防銲開口 222 係暴露出所對應之被動元件230所接合之多數個被動元件 電極平面212、214的部分表面。最後，封膠228例如包 覆封裝基板210上之主動元件204及/或被動元件23〇， 而封裝基板210之下表面還可形成多數個銲球24〇，其連 13 13〇腦—6 接外部電氣裝置（未繪示），以構成一球格陣列之電氣封 裝結構202。 ” 綜上所述，本發明之線路載板及其電氣封裝結構，且 有下列優點： (1)由於被動元件之底部與基板之間無防銲層，使 得被動元件之底部與基板之間的間隙加大，因此銲接時所 使用的助銲劑可輕易地清除，使得後續銲料 後不會相互連接㈣雜路，故可提賴動元件於後# 溫製程之組裴良率。 曰（2)在防銲開口的對位精度上，本發明之被動元件 ^銲開π的面積範圍係大於—被動元件所對應之多數個被 ^件電極平面的露出面積，故可使用對位精度較低之 備來製作_卩扣，使得線路載板㈣作成本明顯降 雖然本發明已以一較佳實施例揭露如上 以限定本發明，任付孰習士姑蓺本如 並非用 神知A ^胁者，在不脫離本發明之精 乾_，自可作些許之更動躺飾，因此本發明 遵乾圍當視伽之”專職目所界定者為準。 ” 【圖式簡單說明】 圖1A 視示意圖。 緣示習知—種線路雜與組裝之電子元件的俯 =:=:::=r心 始1_。6 面示意圖。 之種線路載板與組裝之電子元件 圖2A繪示本發明 的俯視示意圖。 視示^圖。日林發明—較佳實施例之—種線路載板的俯 圖2C以及圖2D分別繪示本發明另二較佳實施例之 一種線路載板的俯視示意圖。In the process of 21^, it is also possible to increase the bonding properties of the solders 224, 22 by flux. In addition, after the two electrodes 232, 234 of the passive component 230 are soldered to the two passive component electrode planes 212, 214 of the line carrier 200, the auxiliary agent can also be removed by a cleaning step, after which the surface of the passive component 230 is removed. A glue 228 may also be coated to form an electrical package structure 202. It should be noted that, in FIG. 2E, after the two electrodes 232, 234 are respectively connected to the two passive element electrode planes 212, 214, since there is no solder mask between the passive 12 I3 〇 16261fdoc / 006 element 230 and the substrate 210, The gap 208 between the passive component 23A and the substrate 210 is increased, so that the flux is less likely to remain between the passive component 230 and the substrate 210 when removed. Therefore, when the line carrier 2 having the passive component 230 is subjected to a subsequent high temperature process (for example, a known process), the two solders 224, 226 will not easily flow into the gap 209 formed by the sealant 228 and the substrate 210 to improve the passiveness. The assembly yield of component 230 in a subsequent high temperature process. Please refer to FIG. 2F, which is a cross-sectional view showing an electrical package structure of the present invention. The electrical package structure 202 mainly includes a package substrate 210, at least one active device 2〇4, at least one passive component 23A, a plurality of passive component electrode planes 212, 214, and a solder resist layer 22A. The passive component electrode planes 212, 214 are disposed on the surface of the package substrate 21, to electrically connect the corresponding passive components 230. In addition, the active device 204 is electrically connected to the package substrate 21 by, for example, a plurality of wires 206, or is electrically connected to the package substrate 21 by flip chip. In addition, the passive component 230 is, for example, a capacitor located on the surface of the package substrate 21, and each passive component 230 has a plurality of electrodes 232, 234. The solder resist layer 220 covers the surface of the package substrate 21 and has at least one passive component solder resist opening 222, wherein each passive component solder resist opening 222 corresponds to a passive component 230, and each passive component solder resist opening The 222 system exposes a portion of the surface of the plurality of passive component electrode planes 212, 214 to which the corresponding passive component 230 is bonded. Finally, the encapsulant 228 covers, for example, the active component 204 and/or the passive component 23A on the package substrate 210, and the lower surface of the package substrate 210 may also form a plurality of solder balls 24〇, which are connected to the 13-13 brain-6 connection. External electrical devices (not shown) form an electrical package structure 202 of a ball grid array. In summary, the circuit carrier board of the present invention and its electrical package structure have the following advantages: (1) Since there is no solder mask between the bottom of the passive component and the substrate, the bottom of the passive component is between the substrate and the substrate. The gap is increased, so the flux used in soldering can be easily removed, so that the subsequent solders are not connected to each other (4), so the component can be improved in the post-temperature process. 曰(2) In the alignment accuracy of the solder resist opening, the area of the passive component of the present invention is greater than the exposed area of the plurality of electrode planes corresponding to the passive component, so that the alignment accuracy can be used. In order to make the line carrier (4) cost significantly lower, although the present invention has been disclosed in a preferred embodiment as above to limit the present invention, if it is not used by the gods, Without departing from the essence of the present invention, it is possible to make a few changes to the lie, and therefore the present invention is subject to the definition of "the professional". BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1A is a schematic view. The conventional knowledge of the line-like and assembled electronic components is: ==:::=r, the heart begins with 1_.6-side schematic diagram. FIG. 2A is a top plan view of the present invention. FIG. 2C and FIG. 2D respectively show another preferred embodiment of the present invention. A schematic top view of a line carrier.
圖2E緣不圖2A之線路載板與被動元件沿著Π-Π線 的剖面不意圖。 圖2F繪示本發明一較佳實施例之一種電氣封裝結構 的剖面示意圖。 【主要元件符號說明】 100 :線路載板 102 :電氣封裝結構 104 ·晶片 104a ·晶片接合區Figure 2E is not intended to be a cross-section of the line carrier and passive components of Figure 2A along the Π-Π line. 2F is a cross-sectional view showing an electrical package structure in accordance with a preferred embodiment of the present invention. [Main component symbol description] 100: Line carrier 102: Electrical package structure 104 · Wafer 104a · Wafer bonding area
108 :間隙 109 :縫隙 110 ·基板 112、114 :被動元件電極平面 120 :防銲層 122a、122b ·防鮮開口 124、126 :焊料 128 :封膠 15 Ι301665„ 130 :被動元件 130a :被動元件接合區 132、134 :電極 200 :線路載板 202 :電氣封裝結構 204 :晶片（主動元件） 204a:晶片接合區 206 ··導線 208 :間隙 209 :縫隙 210 :基板 212、214 :被動元件電極平面 220 :防銲層 222 :被動元件防銲開口 224、226 :銲料 228 :封膠 230 :被動元件 230a :被動元件接合區 232、234 :電極 240 :銲球108: gap 109: slit 110 · substrate 112, 114: passive element electrode plane 120: solder resist layer 122a, 122b · anti-fresh opening 124, 126: solder 128: sealant 15 Ι 301665 „ 130: passive component 130a: passive component bonding Areas 132, 134: Electrode 200: Line carrier 202: Electrical package structure 204: Wafer (active component) 204a: Wafer bonding area 206 · Wire 208: Gap 209: Slit 210: Substrate 212, 214: Passive element electrode plane 220 : solder mask 222 : passive component solder mask opening 224, 226 : solder 228 : sealant 230 : passive component 230a : passive component junction 232 , 234 : electrode 240 : solder ball