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TWI298915B - Wire bonding apparatus - Google Patents

Wire bonding apparatus Download PDF

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Publication number
TWI298915B
TWI298915B TW094138445A TW94138445A TWI298915B TW I298915 B TWI298915 B TW I298915B TW 094138445 A TW094138445 A TW 094138445A TW 94138445 A TW94138445 A TW 94138445A TW I298915 B TWI298915 B TW I298915B
Authority
TW
Taiwan
Prior art keywords
wire
bonding
bump
waveform
response waveform
Prior art date
Application number
TW094138445A
Other languages
Chinese (zh)
Other versions
TW200629445A (en
Inventor
Shinobu Ishii
Yoshikatsu Hayashizaki
Yoshinobu Suzuki
Masamoto Saito
Original Assignee
Kaijo Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kaijo Kk filed Critical Kaijo Kk
Publication of TW200629445A publication Critical patent/TW200629445A/en
Application granted granted Critical
Publication of TWI298915B publication Critical patent/TWI298915B/en

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Classifications

    • H—ELECTRICITY
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    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/78—Apparatus for connecting with wire connectors
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
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    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wire bonding apparatus for detecting non-deposition even to the device having lower electrostatic capacitance. <P>SOLUTION: In the wire bonding apparatus for connecting with wire an electrode of a semiconductor chip 43 and a lead of lead frame and the wire bonding apparatus for bonding bump to pad of semiconductor chip, this wire bonding apparatus comprises an applying means for applying the DC pulse to wire or bump, a detecting means for detecting response waveform from the wire or bump by applying the DC pulse thereto, and a determining means for determining whether the wire or bump is connected normally with bonding or not by comparing the response waveform with non-bonding response waveform from the wire or bump obtained by applying the DC pulse to the wire or bump where the bonding is completed erroneously. <P>COPYRIGHT: (C)2006,JPO&amp;NCIPI

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1298915 (1) 九、發明說明 ' 【發明所屬之技術領域】 Γ 本發明係有關打線裝置，特別是有關連對電容 (capacitance)很低的設備也能檢查出未結合的打線裝置。 【先前技術】 打線裝置係爲使用由金線、鋁等所製成的銲線（wire) # 來連接形成第1結合點之半導體晶片上的電極和形成第2 結合點的導線（lead)。 藉由搭載於可朝二次元方向移動的X γ工作台上的結 合頭（bonding head)的線性馬達或連結合馬達軸的凸輪等 讓結合支臂朝上下擺動，從安裝於結合支臂之超音波焊頭 (horn)的前端的毛細管送出銲線，於該銲線的前端與放電 電極之間施加高電壓，藉此引起放電。藉由該放電能使銲 線的前端融解，於銲線的前端形成銲球。然後將保持在毛 # 細管之前端的銲球，藉由利用結合支臂之擺動的機械性之 加壓力推抵到屬於第1結合點之半導體晶片的電極，一倂 使用超音波及加熱手段來施行熱壓，對第1結合點來連接 % 銲線。 第6圖（a )至（d )係說明藉由上述打線裝置施行打 線之工程的圖。 如第6圖（a )及（b )所示，在被送出到毛細管2之 前端的銲線1之前端與放電電極4之間引起一定時間的放 電，將銲線I的前端融解而形成銲球2 0，且保持在毛細管 •5- (2) 1298915 2的前端並使毛細管2位於形成第1結合點〗5之半導體晶 * t 片13的電極12的正上方。 〃 其次，如第6圖（C )所示，使毛細管2下降，將銲 球2 0擠壓在電極1 2進行加壓，並且對毛細管2的前端， 透過前述結合支臂的超音波焊頭而施加超音波振動。藉此 於電極連接靜線1。 其次，如第6圖（d )所示，使毛細管2隨著特定的 Φ 迴路控制（1 ο 〇 p c ο n t r ο 1 )上昇而朝屬於第2結合點1 6的導 線1 4方向移動。 其次，使毛細管2下降，將銲線1擠壓在導線1 4進 行加壓，並且對毛細管2的前端透過超音波焊頭而施加超 音波振動，對導線1 4連接銲線1。此後，使毛細管2上昇 而在事先設定的毛細管2之上昇位置關閉切線夾3，切斷 導線1 4上的銲線而完成一次的結合作業。 習知的打線裝置是一種在將銲球20擠壓在半導體晶 ® 片13的電極12而施行接合的狀態，藉由未結合檢查裝置 來判斷結合是否確實完成，即銲線是否爲未結合狀態。該 _ 未結合檢查裝置係按以下的順序進行未結合檢查。 第7圖係表示習知之未結合檢查方法的流程圖。 在結合前總括來設定檢查區間·開始位置、檢查臨限 値（ST1、ST2 )。再者，無法在每個銲線設定檢查區間、 開始位置、檢查臨限値。 其次，進行藉由銲線來連接半導體晶片之電極與導線 的打線（ST3 )。然後進行銲線是否確實結合於在半導體 1298915 (3) 晶片之電極的未結合檢查（S T4 )。此時，判斷銲線爲未 結合的時候，即進行停止打線裝置等的錯誤處理。而判斷 銲線爲確實結合的時候，即進行下次的打線，同樣地進行 未結合檢查（ST3、ST4 )。若已施行全部的打線即結束打 線作業（ST5 )。 其次’針對實施上述未結合檢查方法之未結合檢查裝 置做說明。 第8圖係表示習知之打線裝置的D C專用未結合檢查 裝置的方塊圖。DC專用未結合檢查裝置係爲進行具有DC 特性之半導體晶片專用的未結合檢查。 DC專用未結合檢查裝置係具有DC用未結合檢查基板 44及結合CPU基板1 8。結合CPU基板1 8係具備I /0埠 32。DC用未結合檢查基板44係具備：I /0埠33、 CPU30、A/D變換器35、放大器（AMP) 37、直流發電機 4 5及電阻4 6。 輸出部3 8係連接於第第6圖所示的打線裝置之銲線1 。而接地電位（GND ) 39係透過輸出部38而連接於載置 有半導體晶片1 3的結合台。 使用DC專用未結合檢查裝置來進行未結合檢查時， 在打線時由直流發電機45透過電阻46、輸出部38、銲線 1對半導體晶片1 3的電極1 2施加電壓。然後從半導體晶 片1 3的電極1 2透過銲線1對放大器3 7輸入檢查訊號， 且從放大器37被輸出的輸出訊號，會藉由A/D變換器35 做AD變換，輸入到CPU30。於該CPU30中，若所檢查的 (4) 1298915 訊號在臨限値內’即判斷爲正常結合，若檢查訊號超 限値’即判斷爲異吊結合（即未結合）。然後正常結 「是未結合的訊號會透過I/O ί阜33、32而輸入到結合 基板1 8，進行未結合檢查。 第9圖係表示習知打線裝置之a C專用未結合檢 置的具體構成的電路圖（參照專利文獻1 ) 。A C專用 合檢查裝置係爲進行具有AC特性的半導體晶片專用 φ 結合檢查。 自銲線捲軸（wier spooI)21被遞出的銲線1會通 保持、解放銲線1的切線夾3的保持面之間，插通至 切線夾3之正下方的毛細管2。在屬於銲線捲軸2 1之 之一端的捲軸銲線端22和載置成爲框架之導線框架 爲基準電位點的結合台1 7之間，連接有交流橋路5。 該交流橋路5具備交流發電機5a，前述交流發 5a內裝著以特定頻率產生振盪的正弦波振盪電路。交 • 路5是以：交流發電機5a、和接受來自交流發電機： 輸出訊號的可變電阻器R 1與以電容器C 1所形成的第 聯電路5cl、接受來自交流發電機5之交流訊號的固 阻R2、和包括從捲軸銲線端22直到屬於基準電位點 合台17的電氣路徑之第2串聯電路5 c2而形成閉環。 而前述可變電阻R1與電容器C1之間的第1連接 ，係被連接於差動放大器6之其中一方的輸入端，前 定電阻R2與前述捲軸銲線端22之間的第2連接點Y 連接於前述差動放大器6之另一方的輸入端。 出臨 合或 CPU 查裝 未結 的未 過可 位於 銲線 丨1之 電機 流橋 ;a之 1串 定電 之結 點X 述固 則被 (5) 1298915 在前述固定電阻R2與捲軸銲線端22之間，爲了避免 ^ 外來雜訊的影響連接著同軸電纜5b。因此會產生在同軸電 ^ 纜5b的芯線與外皮之間所產生的同軸電纜5b的電容C2 ，電容C2被等値性地連接在固定電阻R2與結合台1 7之 間。 差動放大器6，係以演算放大器A1、演算放大器A2 、電阻R3、電阻R4、電阻R5所構成。該差動放大器6 # 是用來檢查並輸出從前述第I連接點X、第2連接點Y被 供給到兩輸入端的訊號輸入之差異成份，在前述差動放大 器6的輸出端，係串聯連接電容器C及變壓器7之一次側 輸入端子。 變壓器7的二次側輸出端子係連接於絕對値變換器8 ，絕對値變換器8係爲將自變壓器7被輸出的正極性及負 極性的交流電壓變換成正極性的絕對値電壓。然後在絕對 値變換器8的輸出端連接著第1電平鑑別器9，第1電平 ® 鑑別器9的輸出會輸入到結合判定器26，檢查未結合狀態 〇 t 而於被連接在交流橋路5之第2連接點Y的差動放大 器6之演算放大器A1的輸出端子，連接著低通濾波器23。 低通濾波器23的輸出會輸入到第2電平鑑別器24。第2 電平鑑別器24係低通濾波器23的輸出訊號與先前所設定 的基準之訊號電位做比較，如果低通濾波器23的輸出訊 號爲基準之訊號電位以上，就將邏輯値“ 〇 ”的訊號輸出 到邏輯乘法器25，如果低通濾波器23的輸出訊號爲基準 -9- (6) 1298915 之訊號電位以下，就將邏輯値“丨，，的訊號輸出到邏輯乘 法器25。 結合檢查切換器2 7是在第丨結合（晶片結合）時用 來輸出邏輯値“ 1 ”的訊號，在第2結合（導線結合）時 將邏輯値“ 0 ”的訊號輸出到邏輯乘法器2 5。邏輯乘法器 25係執行結合檢查切換器27之輸出訊號與第2電平鑑別 器24之輸出的邏輯乘法（AND演算），在第1結合（晶 片結合）時，將邏輯値“ 1，，或是“ 〇，，輸出到結合判定器 2 6 ’在第2結合（導線結合）時，常將邏輯値“ 〇，，輸出 到結合判定器2 6。 結合判定器26是當結合連接在作爲第1結合點之半 導體晶片1 3上的電極1 2或是作爲第2結合點之導線框架 1 1的導線1 4時，藉由未結合檢查計時，即來自結合裝置 的指令’在以未結合檢查模式進行檢查的狀態，讀取來自 邏輯乘法器25的輸出訊號，進行未結合檢查的設定。 〔專利文獻1]日本特開2000 — 260808號公報（4〜5 頁、第1圖） 【發明內容】 〔發明欲解決之課題〕 可是，在上述習知打線裝置的未結合檢查裝置中，不 管是DC專用未結合檢查裝置及AC專用未結合檢查裝置 都是藉由針對AC或是DC的輸出電壓來判定檢查電壓之 差來判別爲正常結合或是未結合。以此方式，D C專用未 • 10 - (7) 1298915 結合檢查與AC專用未結合檢查是同時以檢查電壓之波形 Γ 爲定常狀態後的電壓値爲檢查電壓。因此，屬於檢查對象 7 物的半導體晶片及導線框架如果具有一定以上之大小的電 容（例如100PF程度），難以產生在輸出電壓與檢查電壓 之間判疋爲正常結合或是未結合需要的差。換句話就是只 有數PF至數十PF之極低電容的檢查對象物，是無法以習 知的未結合檢查裝置來進行未結合檢查。而檢查對象物的 ® 低電容化朝向愈來愈進步的方向。 本發明係爲考慮如上述之事情的發明，其目的係在於 提供一連對電容較低的設備都能進行未結合檢查的打線裝 置° 〔用以解決課題的手段〕 爲了解決上述課題，有關本發明之打線裝置，係屬於 將半導體晶片的電極與導線框架的導線，利用銲線來連接 鲁 的打線裝置或疋在+導體晶片的婷塾（pad)結合凸塊（bump) 的打線裝置，其特徵爲具備： 將DC脈衝施加於銲線或是凸塊的施加手段、和 檢查來自施加前述DC脈衝所取得的前述銲線或是凸 塊的響應波形的檢查手段、和 藉由將前述響應波形與，來自對結合爲未結合的銲線 或是凸塊施加DC脈衝所取得的前述銲線或是凸塊的未結 合響應波形做比較’以判定銲線或是凸塊是否爲正常地被 結合連接的判定手段。 -11 - (8) 1298915 若藉由上述打線裝置，具有施加DC脈衝的施加手 '，且將施加DC脈衝所取得的響應波形與未結合響應波 r 做比較的緣故，相較於AC正弦波’可檢查階形響應特 。其結果，即使是對電容較低的設備還是能檢查未結合 結合之差，就能完成未結合檢查。 又，於有關本發明的打線裝置中，前述施加手段是 將DC脈衝通過電阻而施加於銲線或是凸塊，並且通過 • 變電阻而施加於電容器的方式被構成， 前述檢查手段是以檢查來自前述銲線或是凸塊的響 波形，並且檢查來自前述電容器的響應波形的方式被構 前述可變電阻是以前述銲線側或是前述凸塊側之容 除以檢查對象物之容量的容量與前述電阻之積爲略等於 述電容器之容量和前述可變電阻之積的方式來調整。 又，有關本發明之打線裝置中，前述檢查手段係具 ^ 用來成形或是加工前述響應波形的電路爲佳。 又’有關本發明之打線裝置中，前述成形或是加工 電路’也可具有通過微分處理並以差動放大器來放大， 一步濾波處理該差動放大的波形，將其變換爲矩形波或 三角波的電路。 又，有關本發明之打線裝置中，前述判定手段，也 藉由比較前述未結合響應波形與經由臨限値係數之積所 得的臨限値及前述響應波形來判定。 有關本發明之打線裝置，係屬於將半導體晶片的電 段 形 性 與 以 可 應 成 量 刖 有 的 進 是 可 取 極 -12- (9) 1298915 與導線框架的導線，利用銲線來連接的打線裝置或是在半 /導體晶片的銲墊結合凸塊的打線裝置，其特徵爲： ^ 具備： 將DC脈衝施加於銲線或是凸塊的施加手段、和 檢查來自施加前述DC脈衝所取得的前述銲線或是凸 塊的響應波形的檢查手段、和 判定銲線或是凸塊是否爲正常地被結合連接的判定手 • 段； 前述判定手段，是在前述銲線或是凸塊接觸於半導體 晶片的電極之前，藉由前述施加手段將D C脈衝施加於前 述銲線或是凸塊，且藉由前述檢查手段來檢查來自於前述 銲線或是凸塊的未結合響應波形，在前述銲線或是凸塊接 觸於半導體晶片的電極之際，藉由前述施加手段將DC脈 衝施加於前述銲線或是凸塊，且藉由前述檢查手段來檢查 來自於前述銲線或是凸塊的正常結合響應波形，由前述未 ® 結合響應波形與前述正常結合響應波形算出臨限値係數， 在前述銲線或是凸塊結合於半導體晶片的電極之後，藉由 前述施加手段將DC脈衝施加於前述銲線或是凸塊，且藉 由前述檢查手段來檢查來自於前述銲線或是凸塊的響應波 形’將該響應波形與，經由前述未結合響應波形與前述臨 限値係數之積所取得的臨限値做比較，藉此進行判定。 若藉由上述打線裝置，在連對電容較低的設備都能完 成檢查未結合與結合之差的未結合檢查方面，可將臨限値 係數與臨限値，藉由軟體控制以自動來設定。 -13- (10) 1298915 〔發明效果〕 如以上說明，若藉由本發明，即可提供一連對電容較 低的設備都能進行未結合檢查的打線裝置。 【實施方式】 〔用以實施發明的形態〕 以下參照圖面’針對本發明之實施形態做說明。 • 第1圖係模式表示利用本發明之實施形態的未結合檢 查裝置的方塊圖。第2圖係表示第1圖所示的檢查電路之 詳細圖。第3圖係槪略表示藉由第1圖所示的低電容檢查 電路部與打線裝置之配線的連接關係以及正常結合波形與 未結合（開放）波形的圖。 再者，在第3圖係模式表示銲線正常地結合連接（結 合）在半導體晶片與銲線未結合（開放）在半導體晶片的 兩種情況，在將DC脈衝電壓階狀地施加於半導體晶片的 ® 情況下，會出現所檢查的波形爲正常結合波形4 8與未結 合（開放）波形49的兩種情況。又，對於具有與習知之 打線裝置相同的構造以及的部分，只說明主要部份，詳細 的說明省略。 藉由本實施形態的未結合檢查裝置，係爲利用因DC 脈衝方式的階形響應（step response)，有關檢查區間、開 始位置等的參數設定項目，就能在每個銲線設定。再者， 連對AC/DC特性混合的設備都能進行未結合檢查。 如第1圖所示，未結合檢查裝置，係具有：未結合檢 -14- i (11) 1298915 查基板1 Ο、低電容檢查電路部4 0及結合頭控制基板1 9。 f 結合頭控制基板1 9，係具備：CPU控制部29及資料通訊 「部32，該CPU控制部29，係被連接在觸控面板（圖未示 )。檢查區間 '開始位置、檢查電位（臨限値）等之每個 銲線的參數可從觸控面板輸入。而CPU控制部2 9，係被 連接在資料通訊部3 2。 未結合檢查基板10，係具備··資料通訊部33、CPU # 控制部30、記憶體34、比較電路（圖未示）、A/D變換 部3 5、D/A變換部3 6及脈衝輸出部2 8。而低電容檢查電 路部40，係具備··電流限制電路3 1、檢查電路41及波形 成形、加工電路42。 資料通訊部3 3的輸入側，係被連接在CPU控制部3 0 ，資料通訊部33的輸出側，係被連接在資料通訊部32。 而CPU控制部30，係被連接在比較電路。CPU控制部30 係各別連接到記憶體34、A/D變換部35及D/A變換部36 ·，D/A變換部36，係被連接在脈衝輸出部28。脈衝輸出 部28，係被連接在電流限制電路3 1，電流限制電路3 1， 係透過銲線（第3圖的參考符號1 )而連接在半導體晶片 (CHIP ) 43。而A/D變換部35，係被連接在波形成形、 加工電路42，波形成形、加工電路42，係被連接在檢查 電路4 1。檢查電路41，係透過銲線（第3圖的參考符號1 )而連接在半導體晶片（CHIP) 43。 如第2圖所示，檢查電路，係具有：電阻R1、可變 電阻VR1、平衡用電容器C1及電阻R2。而檢查電路，係 -15- (12) 1298915 透過銲線1而連接在毛細管電容部W/F、切線夾電容部 &gt; W/C及放電元件電容部EFO。再者，銲線1被結合連接在 半導體晶片43之銲墊時，檢查電路，也透過銲線1而連 接在半導體晶片43。 就是，在銲線與半導體晶片43爲開放狀態的情況下 ，電流限制電路3 1，係透過可變電阻VR 1、平衡用電容器 C1及電阻R2而連接在端子TP1，且透過電阻R1、毛細管 # 電容部W/F、切線夾電容部W/C、放電元件電容部EFO及 電阻R2而連接在端子TP2。而在銲線爲被結合連接在半 導體晶片4 3之銲墊上的狀態之情況下，電流限制電路3 1 ，係透過可變電阻VR1、平衡用電容器C1及電阻R2而連 接在端子TP1，且透過電阻R1、半導體晶片43、毛細管 電容部W/F、切線夾電容部W/C、放電元件電容部ef〇及 電阻R2而連接在端子TP2。即，開放狀態與銲線被連接 在半導體晶片4 3之狀態的檢查電路之不同，就只是在電 • 流限制電路3 1與端子TP2之間連接不連接半導體晶片43 的不同而已。藉由本實施形態的未結合檢查裝置，係藉由 利用前述不同，來檢查是正常結合還是未結合的情形。 前述平衡用電容器c 1，係具有略等於毛細管、切線 夾、放電元件及各配線的電容之和（W/F電容+ W/C電容 + EFO電容+配線電容）的電容値。然後，以成爲 VRlxCl=Rlx (W/F電容+ W/C電容+ EFO電容+配線電 容）地來調整V R 1的電阻値。就是’形成以電流限制電路 31與端子TP1之間（VRlxCl)以及電流限制電路Μ與端 -16- (13) 1298915 子TP2之間（Rix (w/F電容+ W/C電容+ EFO 線電容）爲一致地取得平衡的構成。 如第3圖所示，低電容檢查電路部4 〇的各 檢查’係連接在銲線（金線）1。而接地電位（ 係連接在載置著半導體晶片43的結合台。 其次，針對利用上述未結合檢查裝置來進行 查的方法，邊參照第1圖至第5圖邊說明。 第4圖（A)係表示藉由第1圖所示的未結 置針對最初的1晶片邊自動設定臨限値邊進行未 之流程的流程圖。第4圖（B)係表示藉由第1 未結合檢查裝置針對第2晶片以後的晶片進行未 之流程的流程圖。 第5圖係表示藉由第1圖所示的未結合檢查 未結合檢查之際，將輸出電壓E施加於銲線後， 間T的檢查電壓Vc之變化的圖。參考符號49， 結合（開放）波形，參考符號48，係表示正常結 參考符號47，係表示階狀施加的DC脈衝電壓的: 首先，在連接半導體晶片與導線，進行結合 對連接在半導體晶片43的每個銲線，從觸控面 查區間、開始位置、DC脈衝等的參數設定項目 對結合頭控制基板19的CPU控制部29輸入參 §。 其次，應用軟體控制，前述參數設定項目會 控制基板1 9的CPU控制部29通過資料通訊部 電容+配 個輸出及 GND )， 未結合檢 合檢查裝 結合檢查 圖所示的 結合檢查 裝置進行 因經過時 係表示未 合波形。 皮形。 之前，針 板輸入檢 。藉此， 數設定項 從結合頭 32 、 33 ， -17- (14) 1298915 通知未結合檢查基板1 0的C P U控制部3 Ο，儲存在記憶體 ‘ 34 ° '其次，如第4圖（A )所示，讀入銲線開放波形（ ST1 1 )。具體而言，係融解第3圖所示的銲線（金線）j 之HU师i而形成錦球’且保持在毛細管2的前端，並在使毛 細管2位在屬於第1結合點之半導體晶片43的電極之正 上方之際，或使毛細管2下降之際，將第5圖所示的電壓 # E之DC脈衝47從電流限制電路3 1階狀地施加到銲線。 就是，如第2圖所示，DC脈衝47，係透過可變電阻VR1 而施加到平衡用電容器C1，來自該電容器C1的響應是透 過電阻R2而以端子TP1檢查。於此同時，DC脈衝47， 係透過電阻R 1而施加到毛細管電容部W/F、切線夾電容 部W/C及電元件電容部EFO，來自該些電容部的響應是透 過電阻R2而以端子TP2檢查。此時，銲線1爲未連接在 半導體晶片43之開放狀態的緣故，以端子TP2檢查的階 • 形響應波形則爲第5圖所示的座標4 9。再者，所施加的 DC脈衝47，可改變爲ΙΚΗζ〜20KHz。 其次，將以檢查電路4 1所檢查的前述銲線開放波形 49藉由波形成形、加工電路42來進行成形及加工。即， 對前述銲線開放波形49，通過HPF (微分處理）而以差動 放大器來放大，將該差動放大的波形進一步地進行濾波處 理（例如雜訊除去），變換爲矩形波（例如峰値保持 (peak hold)或是採樣保持（sample hold))或是三角波（例 如積分處理）。將該變換的銲線開放波形在A/D變換部 -18- 30 (15) 1298915 35進行A/D變換。將該A/D變換的値以CPU控制部 &gt; 讀入。然後’像這樣地將成形、加工且讀入的銲線開放 ^ 形儲存在記憶體34，且由記憶體34設定到比較電路。 而以電流限制電路31與端子TP1之間的（VRlxCl 以及電流限制電路31與端子TP2之間的（Rlx ( W/F電 + W/C電容+ EFO電容+配線電容））爲一致地，來調 可變電阻VR1而取得平衡。 # 在此，由端子TP1所檢查的檢查電壓Vcl與檢查時 T1的關係，係以式（1 )表示，由端子TP2所檢查的檢 電壓Vc 1與檢查時間T2的關係，係以式（2 )表示。1298915 (1) IX. INSTRUCTIONS INSTRUCTIONS [Technical field to which the invention pertains] Γ The present invention relates to a wire bonding device, and particularly to a device having a low capacitance (capacitance), which can also detect an unbonded wire bonding device. [Prior Art] The wire bonding device connects the electrodes on the semiconductor wafer forming the first bonding point and the lead forming the second bonding point by using a wire # made of gold wire, aluminum or the like. The coupling arm is swung up and down by a linear motor mounted on a bonding head on the X γ table movable in the second element direction or a cam coupled to the motor shaft, and is mounted on the coupling arm. The capillary at the tip end of the horn is fed with a bonding wire, and a high voltage is applied between the tip end of the bonding wire and the discharge electrode, thereby causing discharge. By this discharge, the front end of the wire can be melted, and a solder ball is formed at the front end of the wire. Then, the solder ball held at the front end of the capillary tube is pushed to the electrode of the semiconductor wafer belonging to the first bonding point by the mechanical pressing force of the swing of the bonding arm, and the ultrasonic wave and the heating means are used. Hot pressing is performed, and the % bonding wire is connected to the first bonding point. Fig. 6 (a) to (d) are diagrams showing the construction of the wire by the above-described wire splicing device. As shown in Fig. 6 (a) and (b), a discharge is caused between the front end of the bonding wire 1 sent to the front end of the capillary 2 and the discharge electrode 4, and the tip end of the bonding wire I is melted to form a solder ball. 2 0, and held at the front end of the capillary •5-(2) 1298915 2 and the capillary 2 is located directly above the electrode 12 of the semiconductor crystal piece 13 forming the first bonding point. 〃 Next, as shown in Fig. 6(C), the capillary 2 is lowered, the solder ball 20 is pressed against the electrode 12 for pressurization, and the front end of the capillary 2 is passed through the ultrasonic ultrasonic head of the combined arm. Ultrasonic vibration is applied. Thereby, the static line 1 is connected to the electrode. Next, as shown in Fig. 6(d), the capillary 2 is moved in the direction of the wire 14 belonging to the second junction 16 as the specific Φ loop control (1 ο 〇 p c ο n t r ο 1 ) rises. Next, the capillary 2 is lowered, the bonding wire 1 is pressed against the wire 14 to be pressurized, and the tip end of the capillary 2 is ultrasonically vibrated by the ultrasonic horn, and the wire 1 is connected to the wire 14. Thereafter, the capillary 2 is raised, and the tangential clip 3 is closed at the rising position of the capillary 2 set in advance, and the bonding wire on the wire 14 is cut to complete the bonding operation once. The conventional wire bonding device is a state in which the bonding of the solder ball 20 to the electrode 12 of the semiconductor chip 13 is performed, and it is judged whether or not the bonding is completed by the unincorporated inspection device, that is, whether the bonding wire is unbonded. . The _ unbonded inspection device performs unbonded inspection in the following order. Figure 7 is a flow chart showing a conventional uncombined inspection method. The inspection section, the start position, and the inspection threshold 値 (ST1, ST2) are set in total before the combination. Furthermore, it is not possible to set an inspection section, a starting position, and a check threshold for each bonding wire. Next, bonding of the electrodes of the semiconductor wafer and the wires by the bonding wires is performed (ST3). Then, whether or not the bonding wire is indeed bonded to the unbonded inspection (S T4 ) of the electrode of the semiconductor 1298915 (3) wafer is performed. At this time, when it is judged that the bonding wire is unbonded, the error processing such as stopping the wire bonding device is performed. When it is judged that the bonding wire is actually combined, the next bonding is performed, and the uncombined inspection is performed in the same manner (ST3, ST4). If all the lines have been applied, the line operation is completed (ST5). Next, an explanation will be given of an unincorporated inspection apparatus that performs the above-described unincorporated inspection method. Fig. 8 is a block diagram showing a D C-specific unbonded inspection device of a conventional wire bonding device. The DC-unbound unchecked inspection device is an unbonded inspection dedicated to semiconductor wafers having DC characteristics. The DC dedicated unbonded inspection device has a DC unbonded inspection substrate 44 and a combined CPU substrate 18. The CPU board 18 is provided with I / 0 埠 32. The DC unbonded inspection substrate 44 includes I/0埠33, a CPU 30, an A/D converter 35, an amplifier (AMP) 37, a DC generator 45, and a resistor 46. The output unit 38 is connected to the bonding wire 1 of the wire bonding device shown in Fig. 6 . The ground potential (GND) 39 is connected to the bonding stage on which the semiconductor wafer 13 is placed via the output unit 38. When the unbonded inspection is performed using the DC-unbound inspection device, the DC generator 45 transmits a voltage to the electrode 12 of the semiconductor wafer 13 through the resistor 46, the output portion 38, and the bonding wire 1 at the time of wire bonding. Then, an inspection signal is input from the electrode 1 of the semiconductor wafer 13 through the bonding wire 1 to the amplifier 37, and an output signal output from the amplifier 37 is AD-converted by the A/D converter 35, and input to the CPU 30. In the CPU 30, if the detected (4) 1298915 signal is within the threshold, it is judged to be a normal combination, and if the inspection signal is exceeded, it is judged to be a different combination (i.e., uncombined). Then, the normal junction "is that the uncombined signal is input to the bonded substrate 1 through I/O 阜 33, 32 for unbonded inspection. Fig. 9 shows the unbonded inspection of the conventional C-wire device. A circuit diagram of a specific configuration (see Patent Document 1). The AC-dedicated inspection apparatus is a φ-bonding inspection for semiconductor wafers having AC characteristics. The bonding wire 1 that is ejected from the wier spoo I 21 is held, Between the holding faces of the tangential clips 3 of the liberating bonding wire 1, the capillaries 2 directly under the tangential clips 3 are inserted. At the end of the reel wire end 22 belonging to one end of the wire reel 2 1 and the wire placed as a frame An AC bridge 5 is connected between the junctions 17 at which the frame is the reference potential point. The AC bridge 5 is provided with an alternator 5a, and the AC wave 5a is provided with a sine wave oscillation circuit that oscillates at a specific frequency. • The road 5 is an alternator 5a, and receives a variable resistor R1 from the alternator: output signal and a first circuit 5cl formed by the capacitor C1, and receives an alternating current signal from the alternator 5. Solid resistance R2, and package The second series circuit 5 c2 from the reel wire end 22 to the electrical path belonging to the reference potential spotting stage 17 forms a closed loop. The first connection between the variable resistor R1 and the capacitor C1 is connected to the difference. An input end of one of the movable amplifiers 6, a second connection point Y between the front fixed resistor R2 and the reel wire end 22 is connected to the other input end of the differential amplifier 6. The output or the CPU is installed. The unconnected motor bridge can be located in the wire 丨1; the node X of the string 1 is fixed by (5) 1298915 between the fixed resistor R2 and the wire end 22 of the reel, in order to avoid ^ The influence of the external noise is connected to the coaxial cable 5b. Therefore, the capacitance C2 of the coaxial cable 5b generated between the core wire and the sheath of the coaxial cable 5b is generated, and the capacitor C2 is equally connected to the fixed resistor R2 and The differential amplifier 6 is composed of an operational amplifier A1, an operational amplifier A2, a resistor R3, a resistor R4, and a resistor R5. The differential amplifier 6# is used to check and output the first connection from the foregoing. Point X and the second connection point Y are supplied to the two inputs The difference component of the signal input at the end is connected to the primary side input terminal of the capacitor C and the transformer 7 at the output end of the differential amplifier 6. The secondary side output terminal of the transformer 7 is connected to the absolute sigma converter 8, absolute 値The inverter 8 converts the positive and negative AC voltages output from the transformer 7 into a positive absolute voltage, and then connects the first level discriminator 9 to the output terminal of the absolute sigma converter 8, the first The output of the level® discriminator 9 is input to the combination determiner 26, and the uncombined state 〇t is checked to the output terminal of the operational amplifier A1 of the differential amplifier 6 connected to the second connection point Y of the AC bridge 5. A low pass filter 23 is connected. The output of the low pass filter 23 is input to the second level discriminator 24. The second level discriminator 24 compares the output signal of the low pass filter 23 with the signal potential of the previously set reference. If the output signal of the low pass filter 23 is above the reference signal potential, the logic will be "値" The signal is output to the logic multiplier 25. If the output signal of the low pass filter 23 is below the signal potential of the reference -9-(6) 1298915, the signal of the logical 値 "丨," is output to the logical multiplier 25. The combination check switch 27 outputs a signal for outputting a logic 値 "1" when the second combination (wafer bonding), and outputs a signal of logic 値 "0" to the logical multiplier 2 at the second combination (wire bonding). 5. The logical multiplier 25 performs a logical multiplication (AND calculation) combining the output signal of the check switch 27 and the output of the second level discriminator 24, and the logic 値 "1" in the first combination (wafer bonding) Or, " 〇, the output to the combination determinator 2 6 ' is in the second combination (wire bonding), and the logic 値 "〇," is output to the combination determinator 26. The bonding determiner 26 is when the electrode 12 connected to the semiconductor wafer 13 as the first bonding point or the wire 1 of the lead frame 11 as the second bonding point is bonded, by the uncombined inspection timing, that is, The command from the combining device reads the output signal from the logical multiplier 25 in a state of being checked in the uncombined inspection mode, and performs setting of the uncombined check. [Patent Document 1] Japanese Laid-Open Patent Publication No. 2000-260808 (4 to 5 pages, first drawing) [Explanation] [Problem to be solved by the invention] However, in the unbonded inspection device of the above-described conventional wire bonding device, Both the DC dedicated unincorporated inspection device and the AC dedicated unintegrated inspection device are determined to be normally combined or uncombined by determining the difference between the inspection voltages for the output voltage of AC or DC. In this way, D C is not used. • 10 - (7) 1298915 The combination check and the AC-specific uncombined check are performed at the same time to check the voltage waveform Γ. The voltage 値 is the check voltage. Therefore, if the semiconductor wafer and the lead frame belonging to the object to be inspected have a capacitance of a certain size or more (e.g., about 100 PF), it is difficult to determine the difference between the output voltage and the inspection voltage as being normally combined or uncombined. In other words, an object to be inspected having a very low capacitance of only a few PF to several tens of PF cannot be unbonded by a conventional unbonded inspection device. The low capacitance of the inspection object is moving towards an increasingly progressive direction. The present invention is an object of the present invention, and an object of the present invention is to provide a wire bonding device capable of performing unbonded inspection on a device having a low capacitance. [Means for Solving the Problems] In order to solve the above problems, the present invention relates to the present invention. The wire bonding device belongs to a wire bonding device that connects a wire of a semiconductor wafer and a wire frame, and uses a bonding wire to connect a wire bonding device or a pad bonding bump of a + conductor wafer. In order to provide: a method of applying a DC pulse to a bonding wire or a bump, and an inspection means for inspecting a response waveform of the bonding wire or bump obtained by applying the DC pulse, and by using the aforementioned response waveform Comparing the unbonded response waveforms of the aforementioned bonding wires or bumps obtained by applying DC pulses combined with unbonded bonding wires or bumps to determine whether the bonding wires or bumps are normally joined. The means of judgment. -11 - (8) 1298915 If the application of the DC pulse is applied by the above-mentioned wire-drawing device, and the response waveform obtained by applying the DC pulse is compared with the uncombined response wave r, compared with the AC sine wave 'Check the step response. As a result, uncombined inspection can be completed even if the device with a lower capacitance can check the difference of the unbonded combination. Further, in the wire bonding device according to the present invention, the applying means is configured such that a DC pulse is applied to a bonding wire or a bump through a resistor, and is applied to the capacitor by a variable resistor, and the inspection means is inspection. The waveform from the wire bond or the bump is detected, and the response waveform from the capacitor is checked. The variable resistor is configured such that the capacity of the inspection object is divided by the wire side or the bump side. The product of the capacity and the aforementioned resistance is adjusted to be slightly equal to the product of the capacity of the capacitor and the variable resistor. Further, in the wire bonding device of the present invention, it is preferable that the inspection means is a circuit for forming or processing the response waveform. Further, in the wire bonding device of the present invention, the forming or processing circuit ' may have a differential processing by differential processing and a differential amplifier to process the differentially amplified waveform and convert it into a rectangular wave or a triangular wave. Circuit. Further, in the wire bonding device of the present invention, the determining means is also determined by comparing the threshold 値 and the response waveform obtained by the product of the unbonded response waveform and the threshold coefficient. The wire bonding device of the present invention belongs to a wire which is connected by a bonding wire by connecting the electric segment shape of the semiconductor wafer to the wire of the lead frame 12- (9) 1298915 and the wire frame which are available in a measurable amount. The device or the wire bonding device for bonding the bumps on the half/conductor wafer is characterized by: ^ having: applying a DC pulse to the bonding wire or the bump, and checking the obtained from applying the DC pulse The inspection means for the response waveform of the bonding wire or the bump, and the determining hand or segment for determining whether the bonding wire or the bump is normally connected; the determining means is that the bonding wire or the bump is in contact with Before the electrodes of the semiconductor wafer, a DC pulse is applied to the bonding wires or bumps by the applying means, and the uncombined response waveform from the bonding wires or bumps is inspected by the inspection means, and the welding is performed. When a line or a bump contacts the electrode of the semiconductor wafer, a DC pulse is applied to the bonding wire or the bump by the applying means, and is inspected by the foregoing inspection means. From the normal bonding response waveform of the bonding wire or the bump, the threshold coefficient is calculated from the uncombined response waveform and the normal combined response waveform, after the bonding wire or the bump is bonded to the electrode of the semiconductor wafer, Applying a DC pulse to the bonding wire or the bump by the applying means, and checking the response waveform from the bonding wire or the bump by the foregoing inspection means to transmit the response waveform and the uncombined response via the foregoing The determination is made by comparing the threshold obtained by the product of the waveform with the aforementioned threshold coefficient. According to the above-mentioned wire-punching device, the uncombined inspection which checks the difference between the uncombined and the combined can be completed in the device with the lower capacitance, and the threshold coefficient and the threshold can be set automatically by the software control. . -13- (10) 1298915 [Effect of the Invention] As described above, according to the present invention, it is possible to provide a wire bonding device capable of performing unbonded inspection on a device having a low capacitance. [Embodiment] [Embodiment for Carrying Out the Invention] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. • Fig. 1 is a block diagram showing an unbonded inspection apparatus using an embodiment of the present invention. Fig. 2 is a detailed view showing the inspection circuit shown in Fig. 1. Fig. 3 is a view schematically showing the connection relationship between the low capacitance inspection circuit portion and the wiring of the wire bonding device shown in Fig. 1, and the normal combined waveform and the uncoupled (open) waveform. Furthermore, in the third figure, the mode indicates that the bonding wires are normally bonded (bonded) in the case where the semiconductor wafer and the bonding wires are not bonded (opened) in the semiconductor wafer, and the DC pulse voltage is applied stepwise to the semiconductor wafer. In the case of ®, the two waveforms of the normal combined waveform 48 and the unbound (open) waveform 49 appear. Further, the same components as those of the conventional wire bonding device will be described, and only the main portions will be described, and detailed description will be omitted. According to the unincorporated inspection apparatus of the present embodiment, the parameter setting items such as the inspection section and the start position can be set for each bonding wire by using the step response of the DC pulse method. Furthermore, uncombined inspections can be performed on devices that mix AC/DC characteristics. As shown in Fig. 1, the unbonded inspection apparatus includes an unbonded inspection-14-i (11) 1298915 inspection substrate 1 Ο, a low capacitance inspection circuit portion 40, and a bonding head control substrate 19. The f-head control board 19 includes a CPU control unit 29 and a data communication unit 32. The CPU control unit 29 is connected to a touch panel (not shown). The inspection section starts at a position and checks the potential ( The parameters of each of the bonding wires, such as the threshold 可, can be input from the touch panel, and the CPU control unit 209 is connected to the data communication unit 32. The unconnected inspection substrate 10 is provided with the data communication unit 33. The CPU # control unit 30, the memory 34, the comparison circuit (not shown), the A/D conversion unit 35, the D/A conversion unit 36, and the pulse output unit 28. The low capacitance check circuit unit 40 is The current limiting circuit 3 1 and the inspection circuit 41 and the waveform shaping and processing circuit 42 are provided. The input side of the data communication unit 3 3 is connected to the CPU control unit 30 and the output side of the data communication unit 33 is connected. The data communication unit 32 is connected to the comparison circuit. The CPU control unit 30 is connected to the memory 34, the A/D conversion unit 35, and the D/A conversion unit 36, respectively, D/A. The conversion unit 36 is connected to the pulse output unit 28. The pulse output unit 28 is connected to the current limit circuit 31. The current limiting circuit 3 1 is connected to the semiconductor wafer (CHIP) 43 through a bonding wire (reference numeral 1 in Fig. 3), and the A/D conversion unit 35 is connected to the waveform forming and processing circuit 42, and waveform forming The processing circuit 42 is connected to the inspection circuit 41. The inspection circuit 41 is connected to the semiconductor wafer (CHIP) 43 through a bonding wire (reference numeral 1 in Fig. 3). As shown in Fig. 2, the inspection circuit is shown. The system has a resistor R1, a variable resistor VR1, a balancing capacitor C1, and a resistor R2. The inspection circuit is connected to the capillary capacitor portion W/F and the tangential capacitor portion through the bonding wire 1 by -15-(12) 1298915. &gt; W/C and discharge element capacitor portion EFO. When the bonding wire 1 is bonded to the pad of the semiconductor wafer 43, the inspection circuit is also connected to the semiconductor wafer 43 via the bonding wire 1. That is, in the bonding wire When the semiconductor wafer 43 is in an open state, the current limiting circuit 315 is connected to the terminal TP1 through the variable resistor VR1, the balancing capacitor C1, and the resistor R2, and the transmission resistor R1, the capillary #capacitor portion W/F , tangential clip capacitor part W/C, discharge element capacitor The EFO and the resistor R2 are connected to the terminal TP2. When the bonding wire is bonded to the pad of the semiconductor wafer 43, the current limiting circuit 3 1 transmits the variable resistor VR1 and the balancing capacitor C1. The resistor R2 is connected to the terminal TP1, and is connected to the terminal TP2 through the resistor R1, the semiconductor wafer 43, the capillary capacitor portion W/F, the tangential capacitor portion W/C, the discharge capacitor portion ef, and the resistor R2. That is, the difference between the open state and the inspection circuit in which the bonding wires are connected to the state of the semiconductor wafer 43 is different only in the case where the semiconductor wafer 43 is not connected between the current limiting circuit 31 and the terminal TP2. According to the unbonded inspection apparatus of the present embodiment, it is checked whether the combination is normal or not by using the above difference. The balance capacitor c1 has a capacitance 略 which is slightly equal to the sum of the capacitance of the capillary, the tangential clip, the discharge element, and the respective wirings (W/F capacitor + W/C capacitor + EFO capacitor + wiring capacitor). Then, adjust the resistance V of V R 1 to become VRlxCl=Rlx (W/F capacitor + W/C capacitor + EFO capacitor + wiring capacitor). That is, 'between current limit circuit 31 and terminal TP1 (VRlxCl) and current limit circuit Μ and terminal -16- (13) 1298915 sub-TP2 (Rix (w/F capacitor + W/C capacitor + EFO line capacitor) In order to achieve a balanced balance, as shown in Fig. 3, each inspection of the low capacitance inspection circuit unit 4 is connected to the bonding wire (gold wire) 1. The ground potential is connected to the semiconductor wafer. The bonding table of 43. Next, the method of performing the inspection using the above-described unbonded inspection device will be described with reference to Figs. 1 to 5. Fig. 4(A) shows the open state shown in Fig. 1. A flow chart for automatically setting the threshold for the first wafer side. Fig. 4(B) shows the flow of the wafer for the second wafer after the first unbonded inspection device. Fig. 5 is a view showing a change in the inspection voltage Vc between the T after the output voltage E is applied to the bonding wire by the unbonded inspection unbonded inspection shown in Fig. 1. Reference numeral 49, (open) waveform, reference symbol 48, indicates normal junction reference symbol 4 7, the system indicates the DC pulse voltage applied in steps: First, the semiconductor wafer and the wire are connected, and each bonding wire connected to the semiconductor wafer 43 is bonded, and the interval, the start position, the DC pulse, and the like are checked from the touch surface. The parameter setting item inputs a parameter to the CPU control unit 29 of the bonding head control board 19. Next, the software control is applied, and the parameter setting item controls the CPU control unit 29 of the substrate 19 to pass through the data communication unit capacitor + output and GND) The unincorporated inspection and inspection device is combined with the inspection device shown in the inspection chart to indicate the unconformity waveform due to the elapsed time. The skin shape. Before, the needle plate is input. Thereby, the number setting items are from the bonding head 32, 33, - 17- (14) 1298915 The CPU control unit 3 that is not connected to the inspection substrate 10 is notified to be stored in the memory '34 °'. Next, as shown in Fig. 4 (A), the wire bonding open waveform (ST1 1) is read. Specifically, it melts the HU of the bonding wire (gold wire) j shown in FIG. 3 to form a ball and keeps it at the front end of the capillary 2, and places the capillary 2 at the first bonding point. Semiconductor wafer 43 When the pole is directly above, or when the capillary 2 is lowered, the DC pulse 47 of the voltage #E shown in Fig. 5 is applied to the bonding wire stepwise from the current limiting circuit 3 1. That is, as shown in Fig. 2 The DC pulse 47 is applied to the balancing capacitor C1 through the variable resistor VR1, and the response from the capacitor C1 is checked by the terminal TP1 through the resistor R2. At the same time, the DC pulse 47 is transmitted through the resistor R1. It is applied to the capillary capacitor portion W/F, the tangential clamp capacitor portion W/C, and the capacitor capacitance portion EFO, and the response from the capacitor portions is checked by the terminal TP2 through the resistor R2. At this time, the bonding wire 1 is not connected to the open state of the semiconductor wafer 43, and the step response waveform examined by the terminal TP2 is the coordinate 49 shown in Fig. 5. Furthermore, the applied DC pulse 47 can be changed to ΙΚΗζ 20 kHz. Next, the wire bonding open waveform 49 inspected by the inspection circuit 41 is formed and processed by the wave shaping and processing circuit 42. In other words, the wire bonding open waveform 49 is amplified by a differential amplifier by HPF (differential processing), and the differentially amplified waveform is further subjected to filtering processing (for example, noise removal) to be converted into a rectangular wave (for example, a peak). Peak hold (peak hold) or sample hold (sample hold) or triangle wave (such as integral processing). The converted wire bond open waveform is A/D-converted in the A/D conversion unit -18- 30 (15) 1298915 35. The A of the A/D conversion is read in by the CPU control unit &gt;. Then, the wire which is formed, processed, and read is opened in the memory 34, and is set by the memory 34 to the comparison circuit. The current limit circuit 31 and the terminal TP1 (VRlxCl and the current limiting circuit 31 and the terminal TP2 (Rlx (W/F power + W/C capacitor + EFO capacitor + wiring capacitance)) are consistent with each other. The variable resistor VR1 is adjusted to achieve balance. # Here, the relationship between the inspection voltage Vcl checked by the terminal TP1 and the inspection time T1 is expressed by the equation (1), and the detection voltage Vc 1 and the inspection time checked by the terminal TP2. The relationship of T2 is expressed by the formula (2).

Tl = 一 VRlxClxLn{l — ( Vcl/E ) }…（1) T2 = - RlxC(W/C + W/F+ EFO + 配線）xLn { 1 — (Vcl/E ) }…（2 ) ® 再者，開放狀態的情況，因在檢查電路41取得平 ，故T 1 = T2。對此，銲線爲連接在半導體晶片43之電 的正常結合狀態的情況，因只有半導體晶片這部分平衡 壞，故ΤΙ # T2。而第3圖所示的正常結合波形48的情 ，T1 # T2的緣故，與未結合波形49相比，波形變大， 未結合（開放）波形49的情況，ΤΙ = T2的緣故，與正 結合波形48相比，波形變小。 其次，進行1次打線，讀入正常結合波形（S T 1 2 ) 即，使毛細管2下降，將銲球推抵於電極而加壓，同時 波 容 整 間 查 衡 極 朋 況 但 常 對 -19- (16) 1298915 著毛細管2的前端，透過結合支臂的超音波焊頭來 /音波振動，藉此在電極連接銲線1之際，將第5圖 ^ 電壓E的DC脈衝47，從電流限制電路3 1階狀地 正常結合，由端子TP2來檢查正常結合波形。就是 2圖所示，D C脈衝4 7，係透過電阻R 1而施加到半 片43的電極、毛細管電容部W/F、切線夾電容部 放電元件電容部EFO，來自該些電容部的響應是透 φ R2而以端子TP2檢查。此時，銲線1爲連接在半 片4 3之結合狀態的緣故，以端子TP 2所檢查的階 波形，則成爲第5圖所示的座標4 8。再者，由端 來檢查與未結合（開放）波形相同的波形。 其次，將以檢查電路4 1所檢查的前述正常結 4 8藉由波形成形、加工電路4 2來進行成形及加工 對前述正常結合波形48，通過HPF (微分處理）而 放大器來放大，將該差動放大的波形進一步地進行 ® 理（例如雜訊除去），變換爲矩形波（例如峰値保 採樣保持）或是三角波（例如積分處理）。將該變 常結合波形在A/D變換部35進行A/D變換。將該 換的値以CPU控制部3 0讀入。然後，像這樣地將 加工且讀入的正常結合波形儲存在記憶體3 4，且由 3 4設定到比較電路。 其次，在比較電路中’由未結合（開放）波形 正常結合波形4 8算出臨限値係數，且儲存到記憶| ST13)。 施加超 所示的 施加到 ，如第 導體晶 W/C及 過電阻 導體晶 形響應 子 TP1 合波形 。即， 以差動 爐波處 持或是 換的正 A/D變 成形、 記憶體 4 9與 I 34 ( -20- (17) 1298915 其次’使毛細管2隨著特定的迴路控制而上昇，在 ^ 其移動到爲第2結合點的導線方向之際，將第5圖所示 ; 電壓E的DC脈衝47，從電流限制電路3 1階狀地施加 銲線’由端子TP2來檢查階形響應波形。再者，由端 TP 1來檢查與未結合（開放）波形相同的波形。 其次’分別將以檢查電路4 1所檢查的前述階形響 波形及未結合（開放）波形藉此波形成形、加工電路 • 來進行成形及加工。即，分別對前述階形響應波形及未 合（開放）波形，通過HPF (微分處理）而以差動放大 來放大’將該差動放大的波形進一步地進行濾波處理（ 如雜訊除去），變換爲矩形波（例如峰値保持或是採樣 持）或是三角波（例如積分處理）。分別將該變換的階 響應波形及未結合（開放）波形在A/D變換部3 5進 A/D變換。將該A/D變換的値以CPU控制部30讀入。 後，像這樣地分別將成形、加工且讀入的階形響應波形 • 未結合（開放）波形儲存在記憶體34，且由記憶體34 定到比較電路。 其次，在比較電路中，由未結合（開放）波形與前 臨限値係數導出臨限値，加以比較該臨限値與前述階形 應波形。臨限値與階形響應波形爲同等的情況，即判定 未結合，同等以外的情況，即判定爲正常結合（ST1 4 ) 像這樣來進行打線時的未結合檢查。再者，該些處理是 用軟體控制來執行。 在未結合狀態（銲線開放狀態）與正常結合狀態（ 使 的 到 子 應 42 結 器 例 保 形 行 然 及 設 述 響 爲 〇 應 正 -21 · 1298915 (18) 常結合狀態），只有半導體晶片43的電容這部分會在階 形響應波形產生差異的緣故，在正常結合波形48與未結 合（開放）波形49，會產生如第5圖所示的差異。該差異 ’係由前述式（2)即可明白，與半導體晶片之電容成正 比的緣故’連檢查對象物（半導體晶片）之電容極小的情 況下都能進行檢查。藉由檢查該差異，即可判定銲線爲正 常結合、未結合。將該差異經由變換爲HPF、濾波處理、 • 矩形波或是三角波來擴大，就易於正常結合、未結合的判 定。 前述之結合/未結合的結果，係透過資料通訊部3 3、 3 2而通知到結合頭控制基板1 9的C P U控制部2 9。通知 銲線爲未結合的情況下，即停止打線裝置等進行錯誤處理 。而通知銲線爲正常結合（確實被結合）的情況下，即進 行下一個打線。 判斷銲線爲確實被結合的情況下，針對下一個打線， • 藉由軟體控制來執行參數設定項目的設定，於打線時進行 未結合檢查（S T 1 2〜S T 1 4 )。如果重複到〗晶片銲線數， 且完成第1晶片所有打線結合的話，即結束打線作業（ ST15)。 之後，針對第2晶片以後的晶片進行打線及未結合檢 查。有關第2晶片以後的晶片，係應用以最初的1晶片所 設定之臨限値係數的緣故，省略設定臨限値的步驟。以下 ，針對第2晶片以後的晶片之未結合檢查，邊參照第4圖 (B )邊說明。 -22- (19) 1298915 如第4圖（B )所示，讀入銲線開放波形（ST21 ) 該ST21的具體方法，因與前述之ST11相同，故省略詳 ^ 的說明。 其次，將以檢查電路4 1所檢查的前述銲線開放波 藉由波形成形、加工電路42來進行成形及加工，將該 形及加工的銲線開放波形在A/D變換部35進行A/D變 。將該A/D變換的値以CPU控制部30讀入。然後，像 • 樣地將成形、加工且讀入的銲線開放波形儲存在記憶體 ，且由記憶體3 4設定到比較電路。而且調整可變電 VR 1取得平衡。連該些處理都與第1晶片的情況相同。 其次，在半導體晶片的電極連接銲線之後，使毛細 2隨著特定的迴路控制而上昇，在使其移動到爲第2結 點的導線方向之際，將第5圖所示的電壓E的DC脈衝 ，從電流限制電路3 1階狀地施加到銲線，由端子TP2 檢查階形響應波形（ST22 )。再者，由端子TP1來檢查 ® 未結合（開放）波形相同的波形。 其次，分別將以檢查電路4 1所檢查的前述階形響 波形及未結合（開放）波形藉由波形成形、加工電路 來進行成形及加工，且分別將該成形及加工的階形響應 形及未結合（開放）波形在A/D變換部35進行A/D變 。將該A/D變換的値以CPU控制部30讀入。然後，像 樣地分別將成形、加工且讀入的階形響應波形及未結合 開放）波形儲存在記憶體34，且由記憶體34設定到比 電路。 細 形 成 換 這 34 阻 管 合 47 來 與 應 42 波 換 這 ( 較 -23- 1298915 (20) 其次’在比較電路中’由未結合（開放）波形與前述 臨限値係數導出臨限値’加以比較該臨限値與前述階形響 應波形。臨限値與階形響應波形爲同等的情況，即判定爲 未結合’同等以外的情況’即判定爲正常結合（S τ 1 4 )。 像适樣來進行打線時的未結合檢查。再者，該些處理是應 用軟體控制來執行。 前述之結合/未結合的結果，係透過資料通訊部3 3、 ί 3 2而通知到結合頭控制基板1 9的C p u控制部2 9。通知 婷線爲未結合的情況下，即停止打線裝置等進行錯誤處理 。而通知銲線爲正常結合（確實被結合）的情況下，即進 行下一個打線。 判斷銲線爲確實被結合的情況下，針對下一個打線， 藉由軟體控制來執行參數設定項目的設定，於打線時進行 未結合檢查（ST22、ST24 )。如果重複到特定的銲線數， 全部完成打線的話，即結束打線作業（S T2 5 )。 I 上述的打線及未結合檢查，係有關對第6圖所示之第 1結合點1 5的半導體晶片之電極的打線做說明，但連有關 於第6圖所示之第2結合點1 6的導線之打線都能利用上 述的未結合檢查方法來進行未結合檢查，而且融解銲線1 的前端’形成銲球，有關以該銲球作爲凸瑰而連接在半導 體晶片的電極或是銲墊的情況，係能略同於上述之未結合 檢查方法來進行未結合檢查。 藉由上述實施形態，如第2圖所示，檢查電路41，係 具有：電阻R1、可變電阻VR1、平衡用電容器C1及電阻 -24 - (21) 1298915 R2，而檢查電路4 1，係透過銲線1而連接在毛細管電容 ^ 部W/F、切線夾電容部W/C及放電元件電容部EFO。由端 '子TP1所檢查的檢查電壓Vcl與檢查時間T1的關係，係 以前述式（1 )表示，由端子TP2所檢查的檢查電壓Vcl 與檢查時間T2的關係，係以前述式（2 )表示。對於開放 狀態的情況，在檢查電路4 1取得平衡，故T1 = T2，且在 銲線爲連接在半導體晶片43之電極的正常結合狀態的情 # 況，因只有半導體晶片這部分平衡崩壞，故T1#T2。因 而，在未結合狀態（銲線開放狀態）與正常結合狀態（正 常結合狀態），只有半導體晶片43的電容這部分會在階 形響應波形產生差異，該差異，係由前述式（2 )即可明 白，與半導體晶片之電容成正比的緣故，連檢查對象物（ 半導體晶片）之電容極小的情況下都能進行檢查。因此， 連無法利用習知之未結合檢查裝置進行未結合檢查之只有 極低電容的檢查對象物都能進行未結合檢查。Tl = a VRlxClxLn{l — ( Vcl/E ) }...(1) T2 = - RlxC(W/C + W/F+ EFO + Wiring)xLn { 1 — (Vcl/E ) }...(2 ) ® In the open state, since the inspection circuit 41 is flat, T 1 = T2. In this regard, the bonding wire is in a state of being normally connected to the semiconductor wafer 43. Since only the portion of the semiconductor wafer is balanced, ΤΙ # T2. On the other hand, in the case of the normal combined waveform 48 shown in Fig. 3, the waveform of T1 #T2 is larger than that of the uncombined waveform 49, and the waveform of 49 is not combined (open), ΤΙ = T2, and Compared to waveform 48, the waveform becomes smaller. Next, the wire is punched once, and the normal combined waveform (ST 1 2 ) is read, that is, the capillary 2 is lowered, the solder ball is pushed against the electrode and pressurized, and the wave volume is checked and the balance is often -19 - (16) 1298915 The front end of the capillary tube 2 is vibrated by the ultrasonic welding head of the combined arm, so that when the electrode is connected to the bonding wire 1, the DC pulse 47 of the voltage E of Fig. 5 is taken from the current. The limiting circuit 3 1 is normally combined in a stepwise manner, and the normal combined waveform is checked by the terminal TP2. As shown in Fig. 2, the DC pulse 47 is applied to the electrode of the half piece 43, the capillary capacitance portion W/F, and the tangential capacitor portion discharge element capacitance portion EFO through the resistor R1, and the response from the capacitance portions is transparent. φ R2 and check with terminal TP2. At this time, the bonding wire 1 is connected to the half-piece 4, and the step waveform examined by the terminal TP 2 becomes the coordinate 48 shown in Fig. 5. Furthermore, the same waveform as the unbound (open) waveform is checked by the end. Next, the normal junction 48 inspected by the inspection circuit 41 is formed and processed by the waveform shaping and processing circuit 42, and the normal combined waveform 48 is amplified by an amplifier by HPF (differential processing). The differentially amplified waveform is further processed (eg, noise removed) into a rectangular wave (eg, peak-to-sample hold) or a triangular wave (eg, integral processing). This abnormal combination waveform is A/D-converted by the A/D conversion unit 35. The changed 値 is read by the CPU control unit 30. Then, the processed and read normal combined waveform is stored in the memory 34 as it is, and is set to the comparison circuit by 34. Next, in the comparison circuit, the threshold coefficient is calculated from the uncombined (open) waveform normal combined waveform 48 and stored in the memory | ST13). Applying a super applied pattern, such as the first conductor crystal W/C and the over-resistance conductor crystal response TP1 combined waveform. That is, the positive A/D that is held by the differential furnace wave or changed into a shape, the memory 4 9 and I 34 ( -20- (17) 1298915 secondly, causes the capillary 2 to rise with a specific loop control, ^ When moving to the direction of the wire of the second junction point, as shown in Fig. 5; the DC pulse 47 of the voltage E is applied in a stepwise manner from the current limiting circuit 3 1 'Check the step response from the terminal TP2 Waveform. Further, the same waveform as the uncombined (open) waveform is checked by the terminal TP 1. Next, the waveforms of the aforementioned stepped waveform and the uncombined (open) waveform examined by the inspection circuit 41 are respectively formed by the waveform. Processing circuit • For forming and processing, that is, the stepped response waveform and the unclosed (open) waveform are respectively amplified by HPF (differential processing) by differential amplification to further the waveform of the differential amplification. Filtering (such as noise removal), transforming into rectangular waves (such as peak hold or sample hold) or triangular waves (such as integral processing). The transformed step response waveform and uncombined (open) waveform are respectively in A. /D conversion unit 3 5 into A /D conversion: The A/D converted 値 is read by the CPU control unit 30. Then, the stepped response waveforms that are formed, processed, and read are stored in the memory 34 in an uncoupled (open) waveform. And, the memory 34 is fixed to the comparison circuit. Secondly, in the comparison circuit, the unbound (open) waveform and the forward limit coefficient are used to derive the threshold 値, and the threshold 値 and the aforementioned step waveform are compared. The limit is equal to the step response waveform, that is, the uncombined test is judged to be uncombined, that is, the normal combination (ST1 4 ) is determined as the unbonded test at the time of wire bonding. Further, the processes are used. The software control is executed. In the unbonded state (bonded wire open state) and the normal combined state (to make the sub-container, the shape is fixed and the setting is ringing as 〇 Yingzhen-21 · 1298915 (18) often combined State), only the portion of the capacitance of the semiconductor wafer 43 will be different in the step response waveform. In the normal combined waveform 48 and the unbound (open) waveform 49, a difference as shown in Fig. 5 is produced. It can be understood from the above formula (2) that it is inspected in proportion to the capacitance of the semiconductor wafer. When the capacitance of the inspection object (semiconductor wafer) is extremely small, the inspection can be performed. By checking the difference, the welding can be determined. The line is normally combined and uncombined. The difference is expanded by transforming into HPF, filtering, • rectangular wave or triangular wave, and it is easy to combine and uncombined. The above combined/unbound result is transmitted through the data. The communication unit 3 3, 3 2 notifies the CPU control unit 29 of the bonding head control board 19. When the bonding wire is notified that the bonding wire is unbonded, the wire bonding device or the like is stopped to perform error processing. In the case where the bonding wire is notified of normal bonding (actually combined), the next bonding line is performed. When it is judged that the bonding wire is actually combined, for the next wire bonding, • the setting of the parameter setting item is performed by the software control, and the uncombined inspection is performed at the time of wire bonding (S T 1 2 to S T 1 4 ). If the number of wafer bonding wires is repeated, and all the bonding of the first wafer is completed, the wire bonding operation (ST15) is ended. Thereafter, the wafers after the second wafer were subjected to wire bonding and unbonded inspection. Regarding the wafer after the second wafer, the step of setting the threshold 省略 is omitted by applying the threshold coefficient set by the first wafer. Hereinafter, the unbonded inspection of the wafer after the second wafer will be described with reference to Fig. 4(B). -22- (19) 1298915 As shown in Fig. 4(B), the wire bonding open waveform (ST21) is read. The specific method of ST21 is the same as that of ST11 described above, and the detailed description is omitted. Next, the wire bonding open wave inspected by the inspection circuit 41 is formed and processed by the wave shaping and processing circuit 42, and the wire bonding open waveform of the shape and the machining is performed in the A/D conversion unit 35. D changes. The A/D converted 値 is read by the CPU control unit 30. Then, the wire bonding open waveform formed, processed, and read is stored in the memory as it is, and is set by the memory 34 to the comparison circuit. Moreover, the variable power VR 1 is adjusted to achieve balance. These processes are the same as in the case of the first wafer. Next, after the electrode of the semiconductor wafer is connected to the bonding wire, the capillary 2 is raised with the control of the specific circuit, and when the wire is moved to the direction of the wire of the second node, the voltage E shown in FIG. 5 is used. The DC pulse is applied stepwise from the current limiting circuit 3 1 to the bonding wire, and the step response waveform is checked by the terminal TP2 (ST22). Furthermore, it is checked by the terminal TP1 that the waveforms of the unbound (open) waveform are the same. Next, the stepped waveform and the unbonded (open) waveform inspected by the inspection circuit 41 are respectively formed and processed by a waveform forming and processing circuit, and the stepped response of the forming and processing is respectively The A/D conversion unit 35 performs A/D conversion on the unbound (open) waveform. The A/D converted 値 is read by the CPU control unit 30. Then, the stepped response waveform and the uncombined open waveform which are formed, processed, and read are respectively stored in the memory 34, and are set by the memory 34 to the ratio circuit. Finely form the 34 resistors to replace the 47 with the 42 waves (cf. -23-1298915 (20) and then 'in the comparison circuit' from the unbound (open) waveform and the aforementioned threshold coefficient to derive the threshold 値' The threshold 値 is compared with the step response waveform. The threshold 値 is equal to the step response waveform, that is, it is determined that the condition is not combined with 'the equivalent', that is, the normal combination is determined (S τ 1 4 ). It is suitable to perform the uncombined inspection when the wire is wired. Further, the processes are executed by the application software control. The combined/uncombined result is notified to the bonding head through the data communication unit 3 3, ί 3 2 The CPU control unit 29 of the substrate 19 notifies that the wire is unbonded, that is, stops the wire bonding device or the like and performs error processing. When the wire is notified that the wire is normally bonded (consistently combined), the next step is performed. When the wire is judged to be combined, the setting of the parameter setting item is performed by the software control for the next wire, and the unbonded inspection is performed at the time of wire bonding (ST22, ST24). If the number of specific bonding wires is completed, the wire bonding operation (S T2 5 ) is completed. I The above-mentioned wire bonding and unbonded inspection are electrodes of the semiconductor wafer with respect to the first bonding point 15 shown in FIG. The wire is explained, but the wire of the wire of the second joint point 16 shown in Fig. 6 can be used for the unbonded inspection by the unbonded inspection method described above, and the front end of the melted wire 1 is welded. In the case where the ball is connected to the electrode or the pad of the semiconductor wafer by using the solder ball as a bump, the unbonded inspection can be performed in the same manner as the unbonded inspection method described above. As shown in the figure, the inspection circuit 41 has a resistor R1, a variable resistor VR1, a balancing capacitor C1, and a resistor -24 - (21) 1298915 R2, and the inspection circuit 411 is connected to the capillary capacitor through the bonding wire 1. ^ Part W/F, tangential clamp capacitance part W/C and discharge element capacitance part EFO. The relationship between the inspection voltage Vcl checked by the terminal 'sub-TP1 and the inspection time T1 is expressed by the above formula (1), by the terminal TP2 Checked voltage Vcl and inspection The relationship of the time T2 is expressed by the above formula (2). In the case of the open state, the check circuit 4 1 is balanced, so T1 = T2, and the bonding wire is in the normal bonding state of the electrode connected to the semiconductor wafer 43. In other words, since only the balance of the semiconductor wafer collapses, T1#T2. Therefore, in the unbonded state (bonded wire open state) and the normal bonded state (normal combined state), only the capacitance of the semiconductor wafer 43 will be A difference occurs in the step response waveform, which is understood by the above formula (2), and is proportional to the capacitance of the semiconductor wafer, and can be inspected even when the capacitance of the inspection object (semiconductor wafer) is extremely small. . Therefore, even an object to be inspected which has an extremely low capacitance which cannot be unbonded by a conventional unincorporated inspection device can be subjected to an unbonded inspection.

® 而在本實施形態中，施加DC脈衝47的緣故，與AC 正弦波相比，可檢查階形響應特性，其結果易於檢查開放 與結合的差異。而且將施加DC脈衝時的階形響應波形， 只取出HPF處理（微分處理）而上升的變化，藉此更易於 檢查未結合與正常結合的差異。 再者，本發明並不限於上述實施形態，在不脫離本發 明之主旨的範圍內可做各種變更。例如，在本實施形態， 雖是將檢查區間、開始位置等的參數設定項目設定在每個 銲線，但就全部的銲線來看，也可統一性地設定參數設定 -25- (22) 1298915 項目來實施本發明。 而在本實施形態中，在使毛細管2移動到爲第2結合 點的導線方向之際，只要一次由端子TP2來檢查階形響應 波形的步驟，即，將DC脈衝47施加到銲線，其響應波形 的檢查只要進行一次，但在1次打線方面，也可將DC脈 衝47複數次施加到銲線，檢查複數的響應波形。此時， 也可分別將複數的響應波形與臨限値做比較來進行判定， # 也可比較複數的響應波形的平均波形與臨限値來進行判定 ，還可以比較複數的響應波形的最大値之平均値或是最小 値之平均値，或是兩者與臨限値來進行判定。 而在上述實施形態中，雖是使用第4圖（A)所示的 流程圖，以自動來設定臨限値，但也可以不用第4圖（A )所示的流程圖，將事先準備的臨限値以運算子 (operator)輸入到未結合檢查裝置後，利用第4圖（B )所 示的流程圖來進行未結合檢查。 ® 前述事先準備的臨限値，例如藉由具備第1圖及第2 圖所示的未結合檢查裝置的打線裝置，分別在第1結合點 、第2結合點或是結合凸塊的每個銲線，事先實測正常結 合波形與未結合（開放），使用將臨限値以（正常結合波 形+未結合波形）/2所算出的亦可。而且複數次進行正常 結合波形與未結合波形的測定亦佳，此時，以複數測定値 之中的平均値爲臨限値較爲理想。 而在上述實施形態中，雖是形成將低電容檢查電路部 40離開未結合檢查基板1 〇的構成，但也可形成將低電容 -26- (23) 1298915 檢查電路部40配置在未結合檢查基板內的構成。 【圖式簡單說明】 〔第1圖]模式表示利用本發明之實施形態的未結合 檢查裝置的方塊圖。 〔第2圖〕表示第1圖所示的檢查電路之詳細圖。 〔第3圖〕槪略表示藉由第1圖所示的低電容檢查電 ® 路部與打線裝置之配線的連接關係以及正常結合波形與未 結合（開放）波形的圖。 〔第4圖〕（A )係表示針對最初的1晶片進行未，結 合檢查之流程的流程圖，（B )係表示針對第2晶片以_ 的晶片進行未結合檢查之流程的流程圖。 〔第5圖〕表不藉由第1圖所不的未結合檢查裝置進 行未結合檢查之際，將輸出電壓E施加於銲線後，医!,經_ 時間τ的檢查電壓Vc之變化的圖。 • 〔弟6圖〕（a)至（d)係說明藉由打線裝置進行打 線之工程的圖。 〔第7圖〕表示習知之未結合檢查方法的流程_。 〔弟8圖〕表不習知之打線裝置的DC專用未，結合 查裝置的方塊圖。 〔第9圖〕表示習知之打線裝置的AC專用未g @ 查裝置的具體構成的電路圖。 【主要元件符號說明】 -27- 1298915 (24) 1…銲線、2…毛細管、3…切線夾、4…放電電稻 ···交流橋路、5a···交流發電機、5b…同軸電纜、3c 1… 串聯電路、5c2…第2串聯電路、X…第1連接點、Y 2連接點、6…差動放大器、7…變壓器、8…絕對値變 、9…第1電平鑑別器、1 〇…未結合檢查基板、；! i… 框架、12…半導體晶片的電極、13…半導體晶片、η 線、1 5…第1結合點、1 6…第2結合點、1 7…結合台 Φ …結合CPU基板、19…結合頭控制基板、20…銲球 …銲線捲軸、22···捲軸銲線端、23···低通濾波器、24 2電平鑑別器、25…邏輯乘法器、26···結合判定器、 結合檢查切換器、28···脈衝輸出部、29··· CPU控制部 …CPU、3 1…電流限制電路、32，33…資料通訊部、 記憶體、35…A/D變換部、36…D/A變換部、37…放 (AMP ) 、38…輸出部、39…接地電位（GND ) 、40 電容檢查電路部、41…檢查電路、42···波形成形、加 • 路、43…半導體晶片、44…DC用未結合檢查基板、 直流發電機、46···電阻、47··· DC脈衝、48···正常結 形、49…未結合（開放）波形 第1 …第 換器 導線 …導 、18 、21 …第 27… 、30 34… 大器 …低 工電 45… 合波 -28-In the present embodiment, the DC pulse 47 is applied, and the step response characteristic can be checked as compared with the AC sine wave, and as a result, it is easy to check the difference between the opening and the bonding. Further, the step response waveform at the time of applying the DC pulse is taken out only by the HPF processing (differential processing), thereby making it easier to check the difference between the unbound and the normal combination. The present invention is not limited to the embodiments described above, and various modifications can be made without departing from the spirit and scope of the invention. For example, in the present embodiment, the parameter setting items such as the inspection section and the start position are set for each bonding wire, but the parameter setting can be uniformly set for all the bonding wires -25 - (22) 1298915 The item is to implement the invention. On the other hand, in the present embodiment, when the capillary 2 is moved to the direction of the wire of the second joint point, the step of inspecting the step response waveform by the terminal TP2 once, that is, applying the DC pulse 47 to the wire, is The inspection of the response waveform may be performed once, but in the case of one wire bonding, the DC pulse 47 may be applied to the bonding wire a plurality of times to check the complex response waveform. At this time, the complex response waveform can also be compared with the threshold 値 to determine, # can also compare the average waveform of the complex response waveform with the threshold 进行 to determine, and can also compare the maximum response waveform of the complex 値The average 値 or the minimum 値 average, or both and the threshold 进行 to determine. On the other hand, in the above embodiment, the threshold is automatically set using the flowchart shown in Fig. 4(A), but it may be prepared in advance without using the flowchart shown in Fig. 4(A). After the input is input to the unbonded inspection device by an operator, the uncombined inspection is performed using the flowchart shown in FIG. 4(B). ® The previously prepared threshold 値, for example, by the wire bonding device having the unbonded inspection device shown in Figs. 1 and 2, respectively, at the first bonding point, the second bonding point, or each of the bonding bumps The bonding wire is measured in advance and the normal combined waveform is uncombined (open). It can also be calculated by using the threshold (normal combined waveform + uncombined waveform)/2. Further, it is preferable to perform the measurement of the normal combined waveform and the uncombined waveform in plural times. In this case, it is preferable to determine the average 値 among the 値 as a threshold. In the above embodiment, the low capacitance inspection circuit portion 40 is formed to be separated from the unbonded inspection substrate 1A. However, the low capacitance -26-(23) 1298915 inspection circuit portion 40 may be disposed in the uncombined inspection. The structure inside the substrate. BRIEF DESCRIPTION OF THE DRAWINGS [Fig. 1] A block diagram showing an unbonded inspection apparatus according to an embodiment of the present invention. [Fig. 2] shows a detailed view of the inspection circuit shown in Fig. 1. [Fig. 3] A diagram showing the connection relationship between the wiring of the low capacitance inspection electric circuit section and the wire bonding device shown in Fig. 1, and the normal combined waveform and the uncombined (open) waveform. [Fig. 4] (A) is a flow chart showing the flow of the unbonded inspection for the first wafer, and (B) is a flow chart showing the flow of the unbonded inspection for the wafer of the second wafer. [Fig. 5] When the uncombined inspection is performed by the unbonded inspection device shown in Fig. 1, the output voltage E is applied to the bonding wire, and the inspection voltage Vc of _ time τ is changed. Figure. • (Fig. 6) (a) to (d) are diagrams showing the construction of the wire by the wire bonding device. [Fig. 7] shows the flow of the conventional unincorporated inspection method. [Department 8] The DC of the wire-bonding device, which is not known, is not combined with the block diagram of the device. [Fig. 9] is a circuit diagram showing a specific configuration of an AC dedicated non-g@ checking device of a conventional wire bonding device. [Description of main component symbols] -27- 1298915 (24) 1...welding wire, 2...capillary, 3...tangential clamp, 4...discharge electric rice···AC bridge, 5a···Alternator, 5b...coaxial Cable, 3c 1... series circuit, 5c2... 2nd series circuit, X... 1st connection point, Y 2 connection point, 6... differential amplifier, 7... transformer, 8... absolute enthalpy change, 9... first level discrimination , 1 〇...not combined with the inspection substrate; ! i... frame, 12...electrode of semiconductor wafer, 13...semiconductor wafer, η line, 1 5...first junction point, 16 6...second junction point, 1 7... Bonding table Φ ... combined with CPU substrate, 19... bonding head control substrate, 20... solder ball... wire reel, 22 · reel wire end, 23 · low-pass filter, 24 2 level discriminator, 25 ...logic multiplier, 26··· combination determiner, combined check switch, 28··· pulse output unit, 29··· CPU control unit...CPU, 3 1...current limit circuit, 32,33...data communication unit , memory, 35...A/D converter, 36...D/A converter, 37...ample (AMP), 38...output, 39...ground potential (GND), 40 capacitor check Section, 41... inspection circuit, 42··· Waveform shaping, addition, road, 43... semiconductor wafer, 44...DC unbonded inspection substrate, DC generator, 46···resistance, 47··· DC pulse, 48 ···Normal shape, 49...Uncombined (open) waveform 1st...Transformer wire...lead,18,21...27...,30 34... Large...Low power 45... Hebrew-28-

Claims (1)

K98915 月％修(是)正替搗買 十、申請專利範圍 第941 3 8445號專利申請案 中文申請專利範圍修正本 民國97年3月24日修正 1. 一種打線裝置（wire bonding apparatus)，係屬於 將半導體晶片的電極與導線框架的導線，利用銲線（wire φ )來連接的打線裝置，或是在半導體晶片的銲墊（pad)進行 結合（bonding)凸塊（bump)的打線裝置；其特徵爲具備 將DC脈衝施加於銲線或是凸塊的施加手段、和 檢查來自施加前述D C脈衝所取得的前述銲線或是凸 塊的響應波形的檢查手段、和 藉由將前述響應波形，與來自對結合爲未結合的銲線 或是凸塊、施加DC脈衝所取得的前述銲線或是凸塊的未 結合響應波形做比較，以判定銲線或是凸塊是否爲正常地 被結合連接的判定手段。 2. 如申請專利範圍第1項所記載的打線裝置，其中： 前述施加手段是以將D C脈衝通過電阻而施加於銲線 或是凸塊，並且通過可變電阻而施加於電容器的方式被構 成， 前述檢查手段是以檢查來自前述銲線或是凸塊的響應 波形，並且檢查來自前述電容器的響應波形的方式被構成K98915%% repair (Yes) is to buy ten, apply for patent scope No. 941 3 8445 Patent application Chinese patent application scope amendments Amendment of March 24, 1997. 1. A wire bonding apparatus, a wire bonding device for connecting an electrode of a semiconductor wafer and a lead frame, a wire bonding device by wire φ, or a bonding device for bonding a bump on a pad of a semiconductor wafer; The invention is characterized in that it has an application means for applying a DC pulse to the bonding wire or the bump, and an inspection means for inspecting a response waveform of the bonding wire or the bump obtained by applying the DC pulse, and by using the aforementioned response waveform Comparing with the uncombined response waveform from the bonding wire or bump obtained by combining the unbonded bonding wires or bumps and applying a DC pulse to determine whether the bonding wire or the bump is normally The means of determining the connection. 2. The wire bonding device according to claim 1, wherein the applying means is configured to apply a DC pulse to a bonding wire or a bump through a resistor, and apply the capacitor to the capacitor through a variable resistor. The foregoing inspection means is constructed by inspecting a response waveform from the bonding wire or the bump and checking a response waveform from the capacitor. 月％丨修(类)正替換頁 1298915 前述可變電阻，是以前述銲線側或是前述凸塊側之容 量扣除檢查對象物之容量的容量與則述電阻之積爲’略等 於前述電容器之容量和前述可變電阻之積的方式來調整。 3 ·如申請專利範圍第1項或第2項所記載的打線裝置 ，其中： 前述檢查手段係具有用來成形或是加工前述響應波形 的電路。 4.如申請專利範圍第3項所記載的打線裝置，其中 前述成形或是加工的電路’係具有通過微分處理並以 差動放大器來放大，進一步濾波處理該差動放大的波形’ 將其變換爲矩形波或是三角波的電路。 5 .如申請專利範圍第1項或第2項所記載的打線裝置 ，其中： 前述判定手段，係比較藉由前述未結合響應波形與經 由臨限値係數之積所取得的臨限値、及前述響應波形來判 定。 6.如申請專利範圍第3項所記載的打線裝置，其中： 前述判定手段，係比較藉由前述未結合響應波形與經 由臨限値係數之積所取得的臨限値、及前述響應波形來判 定。 7·如申請專利範圍第4項所記載的打線裝置，其中： 前述判定手段，係比較藉由前述未結合響應波形與經 由臨限値係數之積所取得的臨限値、及前述響應波形來判 定。 1298915 月肩#(秒t勢換頁 8. —種打線裝置，係屬於將半導體晶片的電極與導線 框架的導線，利用銲線來連接的打線裝置，或是在半導體 晶片的銲墊進行結合凸塊的打線裝置；其特徵爲： 具備： 將DC脈衝施加於銲線或是凸塊的施加手段、和 檢查來自前述銲線或是凸塊的響應波形的檢查手段、 和 判定銲線或是凸塊是否爲正常地被結合連接的判定手 段； 前述判定手段，是在前述銲線或是凸塊接觸於半導體 晶片的電極之前，藉由前述施加手段將DC脈衝施加於前 述銲線或是凸塊，且藉由前述檢查手段來檢查來自於前述 銲線或是凸塊的未結合響應波形，在前述銲線或是凸塊接 觸於半導體晶片的電極之際，藉由前述施加手段將DC脈 衝施加於前述銲線或是凸塊，且藉由前述檢查手段來檢查 來自於前述銲線或是凸塊的正常結合響應波形，由前述未 結合響應波形與前述正常結合響應波形算出臨限値係數， 在前述銲線或是凸塊結合於半導體晶片的電極之後，藉由 前述施加手段將DC脈衝施加於前述銲線或是凸塊，且藉 由前述檢查手段來檢查來自於前述銲線或是凸塊的響應波 形，將該響應波形與，經由前述未結合響應波形與前述臨 限値係數之積所取得的臨限値做比較，藉此進行判定。In the case of the above-mentioned varistor, the capacity of the above-mentioned wire-bonding side or the above-mentioned bump side is deducted from the capacity of the object to be inspected, and the product of the electric resistance is 'slightly equal to the above-mentioned capacitor. The capacity is adjusted in a manner that is a product of the aforementioned variable resistors. 3. The wire bonding device according to the first or second aspect of the invention, wherein: the inspection means has a circuit for shaping or processing the response waveform. 4. The wire bonding device according to claim 3, wherein the formed or processed circuit has a waveform that is subjected to differential processing and amplified by a differential amplifier, and further filters the differentially amplified waveform. A circuit that is a rectangular wave or a triangular wave. 5. The wire bonding device according to claim 1 or 2, wherein: the determining means compares the threshold obtained by the product of the uncombined response waveform and the threshold coefficient, and The aforementioned response waveform is determined. 6. The wire bonding device according to claim 3, wherein: the determining means compares the threshold 値 obtained by the product of the uncombined response waveform and the threshold coefficient, and the response waveform. determination. 7. The wire bonding device according to claim 4, wherein: the determining means compares the threshold 値 obtained by the product of the unbonded response waveform and the threshold coefficient, and the response waveform. determination. 1298915月肩# (Second t potential page 8. A type of wire-bonding device, which is a wire-bonding device that connects a wire of a semiconductor wafer and a wire frame, a wire bonding device by a bonding wire, or a bonding pad on a semiconductor wafer pad The wire bonding device is characterized by: having: applying a DC pulse to the bonding wire or the bump, and checking the response waveform from the bonding wire or the bump, and determining the bonding wire or the bump Whether or not the means for determining connection is normally connected; wherein the determining means applies a DC pulse to the bonding wire or the bump by the applying means before the bonding wire or the bump contacts the electrode of the semiconductor wafer. And checking the unbonded response waveform from the bonding wire or the bump by the foregoing inspection means, and applying a DC pulse to the electrode of the semiconductor wafer when the bonding wire or the bump contacts the electrode of the semiconductor wafer The bonding wire or the bump, and the normal bonding response waveform from the bonding wire or the bump is inspected by the foregoing inspection means, Calculating the threshold coefficient according to the waveform and the normal combined response waveform, after the bonding wire or the bump is bonded to the electrode of the semiconductor wafer, applying a DC pulse to the bonding wire or the bump by the applying means, and borrowing The response waveform from the bonding wire or the bump is inspected by the inspection means, and the response waveform is compared with the threshold obtained by the product of the uncombined response waveform and the threshold coefficient. Make a decision.
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