[go: up one dir, main page]

TWI283010B - Chip embedded package structure and fabrication method thereof - Google Patents

Chip embedded package structure and fabrication method thereof Download PDF

Info

Publication number
TWI283010B
TWI283010B TW094127084A TW94127084A TWI283010B TW I283010 B TWI283010 B TW I283010B TW 094127084 A TW094127084 A TW 094127084A TW 94127084 A TW94127084 A TW 94127084A TW I283010 B TWI283010 B TW I283010B
Authority
TW
Taiwan
Prior art keywords
layer
wafer
embedded
carrier
opening
Prior art date
Application number
TW094127084A
Other languages
Chinese (zh)
Other versions
TW200707532A (en
Inventor
Shih-Ping Hsu
Original Assignee
Phoenix Prec Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Phoenix Prec Technology Corp filed Critical Phoenix Prec Technology Corp
Priority to TW094127084A priority Critical patent/TWI283010B/en
Priority to JP2006215062A priority patent/JP2007049154A/en
Publication of TW200707532A publication Critical patent/TW200707532A/en
Application granted granted Critical
Publication of TWI283010B publication Critical patent/TWI283010B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/24195—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being a discrete passive component
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

A chip embedded package structure and a fabrication method thereof. A supporting board with at least one opening is provided and a heat conducting block is located in the opening. A semiconductor chip is placed on the heat conducting block. A dielectric layer and a circuit layer are formed on the chip and supporting board successively, and the circuit layer is electrically connected to the chip. Thereafter, a built-up structure may be formed on the circuit layer as a circuit structure to electrically connect to other devices. Therefore, a chip embedded package structure has a heat dissipating layer provided by heat conducting block in the supporting board. Furthermore, the warped outcome in the later process is prevented by the arrangement of the supporting board, the heat conducting block and the dielectric layer and the quality of the package is improved.

Description

1283010 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種晶片嵌埋式構裝結構及其製 法’尤指一種欲埋半導體晶片並使其直接向外作電性延伸 之構裝結構及其製法。 【先前技術】 隨著半導體封裝技術的演進，半導體裝置 (Semiconductor device)已開發出不同的封裝型態，其中球 •柵陣列式（Ball grid array，BGA)為一種先進的半導體封裝 技術，其特點在於採用一基板來安置半導體晶片，並利用 自動對位（Self-alignment)技術以於該基板背面植置複數個 成柵狀陣列排列之錫球（Solder ball)，使相同單位面積之半 導體晶片承載件上可以容納更多輸入/輸出連接端（I/O connection)以符合高度集積化（Integration)之半導體晶片 所需，以藉由此些錫球將整個封裝單元銲結並電性連接至1283010 IX. Description of the Invention: [Technical Field] The present invention relates to a wafer embedded structure and a method for manufacturing the same, and more particularly to a structure for embedding a semiconductor wafer and directly extending it outward. Structure and its method of production. [Prior Art] With the evolution of semiconductor packaging technology, semiconductor devices have developed different package types, in which Ball grid array (BGA) is an advanced semiconductor packaging technology, its characteristics The semiconductor wafer is disposed by using a substrate, and a plurality of solder ball arrays arranged in a grid array are disposed on the back surface of the substrate by using a self-alignment technology to enable semiconductor wafers of the same unit area to be carried. The device can accommodate more I/O connections to meet the requirements of a highly integrated semiconductor wafer to solder and electrically connect the entire package unit to the solder balls.

外部之印刷電路板。 另自IBM公司在1960年早期引入覆晶封裝（Flip chip package)技術以來，相較於打線（Wire bond)技術，覆晶技 術之特徵在於半導體晶片與基板間的電性連接係透過銲錫 凸塊而非一般之金線。而該種覆晶技術之優點在於該技術 可提高封裝密度以降低封裝元件尺寸，同時，該種覆晶技 術不需使用長度較長之金屬導線，故可提高電性性能，以 滿足高密度、高速度之半導體裝置需求。 在現行覆晶（flip chip)技術中，半導體晶片的表面上配 5 18413 1283010 ===lectrc)de pads)，而供承載晶片之電路板上亦 二也4=接觸銲墊，在該晶片以及電路板之間可以適 田也叹置！干錫凸塊或其他導電黏著材料，使該 性接觸面朝下的方式設置 :日曰，、电 塊或導電黏著材料提#該晶^5上’其中，該輝錫凸 輪n , 及電路板間的電性輸入/ 翰出（I/O)以及機械性的連接。 請參閱第1圖，係說明_接明上 件，種名知的覆晶式半導體元 12，以及於千片11之電極塾110上形成有金屬凸塊 及於书路板13之接觸銲墊13() 的預銲錫凸塊15，以將預名m ^成由麵料所製成 屬凸換12丄 凸塊15迴銲至相對應之金 屬凸塊12形成銲錫接。另可進一牛 路板13間的間隙中埴 :在片11以及該電 及该電路杯η „ ，、有枝底骖14，以抑制該晶片11以 /的熱膨脹差並降低料錫接的應力。 ，述習知覆晶封裝技術需經過凸塊|y程、廷 程及填膠製程方可完成該半導體 H骑製 _接，不僅提高製程步驟盥^ 與该琶路板之電性連 險之增加，另於制 同時伴隨製程中信賴性風 體晶材形成供該半導 問題片二;:=電性連接之銲錫結構，因而面臨環保 錫結構之品質可靠戶::：，了製程後’導致所形成的銲 品質降低。、度Μ’進而導致最終產品之電性連接 此外，習知之封裝技術係將半導體 接 黏貼於電路板頂面，再進行打線(w J: _接合封裝，並於基板之背面植接_，:=:;;^ 18413 1283010 . . 到高腳數的目的，但由於丰逡雕 得電路板表面饰線難度辦加 面積及體積限制使 尺寸二 表面，因而不利於半導體元件封褒、结構 尺寸之纟侣小及性能的提高。 =，-般半導體元件之製程，首先係由晶片承載 生產適用於該半導體元件之晶片承載件，如基板或 進行Ϊ日之L、再將該些晶片承载件交由半導體封裝業者 卜山=日日、㈣、以及植球等製程，最後，方可完成客戶 :斤:八之電子功能之半導體元件。其間涉及不同製程業者 有晶片承载件製造業者與半導體封裝業者)，因此 :貫際製造過程中不僅步驟繁項且界面整合不易，不符合 需求變更彈性與經濟效益。 ' 夕再者，隨著電子產業的蓬勃發展，電子產品亦逐漸邁 能、高性能的研發方向。為滿足半導體封裝結構高 積本度（Integratl0n)以及微型化（Miniaturizati〇n)的封 裝需求，半導體晶片於運作時所產生之熱量將明顯增加， 2及時將半導體晶片產生之熱量有效逸散，將嚴重縮短 丁導體晶片之性能及壽命。 一爲此逐有將半導體晶片埋入基板之作法。如第2圖 所示’係如美國專利第6,841，413號，其主要係於一散熱 板21(heat spreader)上接置一半導體晶片22(_似牆咖 die) ’而s玄半導體晶片22之作用面上具有電極墊 221 (electrical c〇nnected)，於該散熱板2 i之上表面及半導 體晶片22的作用面形成—介電層23(dieleCtnc ]ayer)，而 18413 7 1283010 · 該介電層23經圖案化製程形成有開孔23〇藉以露出半導體 晶片22的電極墊221，而在該介電層23表面及㈣㈣ 中形成一線路層24(Conductive trace)，再於該介電層23及 線路層24表面形成另一介電層25，且該介電層25經圖案 化製程形成有開孔25G以露出該線路層24之連接塾部份， 之後再於該介電層25表面及其開孔250中形成另一線路層 26，再於該介電層25及線路層％表面形成—絕緣保護層 27(solder msk material)，且該絕緣保護層27經圖案化製程 Φ以开y成開孔2 7 0用以頒路该線路層2 6之電性連接墊2 61， 最後再於該露出的電性連接墊261表面上形成如錫球之導 電元件28。 。玄半V體晶片22係先接置在該散熱板2丨的表面，使 該半導體晶片22可藉由散熱板21直接散熱，以解決上述 習知技術之缺失。然而，由於散熱板2丨、介電層23之熱 月取脹係數（Coefficient of Thermal Expansion，CTE )差異 •大’此種封裝結構於製程中之溫度變化下，如烘烤 (Baking)、後續熱循環（Thermal Cycle)作業等環境下，各組 成元件上分別產生不同之熱應力（Thernial Stress)，易造成 結構發生翹曲（Warpage)現象，嚴重者可能造成結構層間產 生脫層，甚或擠壓至半導體晶片，造成晶片破裂。^若增 加政熱板厚度以穩定溫度變化時封裝結構受熱變形，改盖 基板翹曲現象，但增設散熱板厚度將增加封裝結構成品的 體積與厚度，並會導致製程成本之增加。 因此，如何提出一種晶片嵌埋式封裝結構，以克服習 18413 8 1283010 ::導體封裝結構製程中結構發生輕 重夏及成本增加、界面整合制。t衣、、，口構厗度、 性品質降低、無法有效散熱等問題;：工驟”:產品電 攻克之難題。 Λ成爲目前業界亟待 【發明内容】 鑒於上述習知技術之缺失， 提供一種晶片嵌埋式構裝結構及J^主要目的及在於 體構裳製程中造成結_曲現象Γ 错以避免於半導 έ士構及另目的即在於提供一種晶片嵌埋式構裝 本發明之再-目㈣在成本° 結構及其製法，以鼓人日ίΓ 種嵌埋式構裝 以搓供空0 正&日日片承載件與晶片構裝之製程，藉 Μ、各戶端較大需求彈性，並 面整合問題。 衣社乂知、成本及介 本發明之又再一目的即在 裝結構及其製法，以有 、f = I埋式構 的熱量。 戚牛蜍脰日日片運作過程中產生 構裝:二=其Π ::本發明係揭露-種晶片嵌埋式 一開口，且於該開口中形成導熱塊；於筆塊 上接置一半導體晶片，且 於該承載板騎半導… 片具有多數電極墊； 摩片上形成一介電層，且令該介電 ^體^之電極塾；以及於該介電層上形成 a U線路層電性連接至該半導體^之電極 18413 9 1283010 . =路:Γΐ可於該線路層上形成一線路增層結構，且使該 "e ^书性連接至該線路層，以及於該線路钍 表面植鈒容叙i首+ 曰m構外 夕數V电TL件，以供該半導體晶片電 部電子裝置。 甩『生連接至外 括另一晶片欲埋式構裝結構之製法，係包 -開口 :、且：irt載板’該第一承載板中形成有至少 且於遠開口中形成導熱塊，藉以 構，同時於古女笛—71， $戟、、口 形成有門 載板中對應該第一承載板開口位置亦 開口，並於該第二承載板開口中接 日日片，精以形成第二承載結構；將兮筮_ 承载結構接置於哕筮_ “ 傅’將5亥弟一 置對應接置於令導㈣樣、，°構上’且使該半導體晶片位 電層’且令該介電層外露出該半 载成-介 於該介電層上形成一線路層，且入極墊；以及 半導體晶片之電轉。彳路層笔性連接至該 ^ 俊，奴可於該線路；μ游Λ、 L，Ojb L結構，且使該線路增層電性 ：‘ 該線路增層結構外表面植設多 =路層，以及於 晶片電性連接至外部電子裝置數W7L件’以供該半導體 本發明再揭露一種晶片嵌 致與上述製法相同，惟於該切:：構之製法，其大 上形成介電層及線路層，1 ^先於第二承載結構 結構接置於該第一承裁結構上將形成有線路層之第二承載 送過上述製程，本發明恭 構，係包括：呈至少_f1 ”各—種晶片嵌埋式構裝結 …開口之承載板，且該開口中形成有 18413 10 1283010 導熱塊，至少一且多激恭托糾—、上、" 導㈣卜.一入 之+導體晶片’係接置於該 A’…，）丨包層’係形成於該承載板及該半導俨曰片 上，且外露出該半導體晶片之電極塾；以及練路ί = 成於该介電層上且與該半導體晶片之電 :，：晶片嵌埋式構裝結構復包括有形成於該二： 與遠線路層電性連接之線路增層結構。 上且 構，述f程本發明又揭露一種晶片嵌埋式構裝結 >开成至少一開口之第—承载板，且該開口中传 =有¥熱塊；接置於該第一承载板上且具至少—開口以 =出該導熱塊之第二承载板；至少—接置於 :設於該第二承載板開口之半導體晶片，該半導體= ^電極墊形成於該第二承載板及該半導體晶片上: 介電層，且該介電層係外露出該半導體晶片之電： 及形成於該介電層上且於該半導 U ，以 之線路層，其中，該構，二二 性連接 且與該線路層電性連接之線二路層上 增層結構表面之導電元件。層、.，。構及形成於該線路 相較於，本㈣m埋式 =主要係將半導體晶片接置在形成於承載板開口中： 入先、塊上’亚可藉由該承載板、導熱塊及介電層之搭配组 3 ’以避免製程之溫度變化對構裝結構產生輕曲 同 =可避免習知技術中增加散熱板厚度來改善製程 =程中構裝結構產生的輕曲狀況時，所引起的構裝結構厚 度、重量及製程成本之增加。 18413 11 1283010 層上又復=發:::晶片嵌埋式構裝結構之介電層及線路 片之承载製程’藉以在該我埋有半導體晶 可在線路結構外表面植設複數導電：：物結構，同時 載板中之半導體晶片得以直接至夕 =嵌埋於承 此’本發明亦可整合晶片承載 :二因 提佴宏6 ^， 衣1卞及日日片構裝製程， 協調問題半導體業者製程與介面 了挺升取終構I產品之電性品質。 屬、：==中供半導體晶片接置之導熱塊係可由金 導體機㈣4製成，⑽可黯於其上之半 長半產生的熱量及時、有效的逸散至外界，延 牛V肢日日片之胥命及構裝結構之可靠性。 【實施方式】 以下藉由特定的具體實施例說明本發明之實施方 ^解ίί此技藝之人士可由本說明書所揭示之内容輕易地 其他優點及功效。本發明亦可藉由其他不同 =貫施例加以施行或應用’本說明書中的各項細節亦 口土方、不同的觀點與應用，在不悖離本發明之精神下進行 ^種修飾與變更。另為簡化圖*及説明，細财結構中 肷埋有兩個半導體晶片為例進行如下之説明，但並非以此 限制本發明之範圍。 如苐3A至3E圖所示，係為詳細説明本發明之晶片嵌 ，式構裝結構之製法第一實施例之剖面示意圖。須注意的 是，該等圖式均為簡化之示意圖，僅以示意方式說明：發 18413 12 1283010 7之電路板之製程。惟該等圖式 ::’其所顯示之元件非為實際實施時之態樣 二之:件數目、形狀及尺寸比例為—種選擇性之設^且匕 兀件佈局型態可能更行複雜。 板3〇tt閱第从圖，首先提供—承載板3G，且於該承載 而於，/成有開口 3〇0，復以導熱材料填充該開口 300， ΓΓΓ·中形成導熱塊則，以供後續於該導熱塊 ►成之。、置+導體晶片。上述該承載板30係由有機材料形 層板或多層板，而該導熱塊31〇可例如金屬、陶究 或热機南散熱材料其中之一者製成。 麟曰請參閲第3B圖，接著，於該導熱塊31〇上接置半 二曰片320。該半導體晶片32〇具有多數電極墊伽，且 八糸透過一導熱黏著層（未圖示）接置於該導埶塊31〇上 此外，另可在該承載板3〇上接置至少一且 。 / 具有多數電極墊 322\之被動元件322，，且該被動元件322係'透過一黏著 層（未圖示）而接置於該承載板3〇上。 请麥閲第3C圖，於該承载板3〇、該半導體晶片3汕 及該被動元件322上形成一介電層33,且令該介電層Μ 形成有多數開孔330以露出該半導體晶片32〇及該被動元 件322之電極墊3施、322a。該介電層33係可例如為環 虱樹脂（EP〇xy resin)、聚乙醯胺（p〇丨yimide)、氰脂 ester)、玻璃纖維（Giass flbe〇、雙順丁烯二酸醯亞胺/三氮 拼（BT，Bismaleimide triazme)或混合環氧樹脂與破璃纖維 寻材質所構成。 18413 13 1283010 請參閲第3D圖，於該介電層33上形成一線 ， ^該線路層Μ得以電性連接至該半導體晶片咖及㈣ /二Γ 了:線路層3 4係可透過形成於該介電層3 3開 之導電結構340 (例如導電盲孔或導電凸 連？至該半導體晶片320及該被動元件322之電極 為章=2 a。惟’形成該線路層3 4之技藝係有多種且 為業"所智知，故在此不再為文贅述。 、酋ϋ此，本發明主要係透過形成於該承載板％開口中 ’之導熱塊310來接置丰導#曰ΰ w ^ t 導埶抬接置牛¥肢日日片，亚可藉由該承载板30、 二：=及介電層33之搭配組合，以避免製程溫度的變 仏成^結構產生龜曲現象’同時可避免習知技術 增加散熱板厚度所引起的構裝結構厚度、重量 曰 本之增加等缺失。 衣私成 I閱第3E ®，之後復可於該線路層3 增層製程，以於兮岣玫爲以退盯、，表路 H袁路層34上形成一線路增層結構％， ，且令㈣路增層結構35得以電性連接至該線路層％。龙 中，該線路增層結構3 5係包括至少一絕緣層3 5置於 該絕緣層350上之衅玖jg且夏於 Mb β 線路層352、以及穿過該絕緣層350以 (、冰路層352電性連接至絕緣層下方線路層34之導電姓 構352a，該導電結構352a 、、、。 另，增層結構35之外:::線路層上則形成 有义數*性連㈣3 5 4，且被覆有_ = 緣保護層36且右容盤門力，、，M + &巴 ”有夕數開孔以外露出該電性連接墊354 ”遣且夕數之導電兀件37 ’例如為錫球（s〇】齡ba⑴、導 18413 】4 1283010 電柱或焊柱，進而可供接置於該承載板3〇導熱塊3ι〇之 導體晶片％〇得以電性導接至外部電子t置。此外，應需 注意者’係該線路增層結構非以圖示之層數為限，: 應實際需求增加層數。 透過上述製程形成之晶片嵌埋式構裝結構係包括：具 開口 300之承載板30,且於該承載板3〇心_ 有導熱塊310;接置於該導熱塊31〇上之半導體晶片wo . 形成於該承載板30及該半導體晶片32〇上之介電曰声％ ; ’ >以及形成於該介電層33上且電性連接接至該； 32〇之線路層34。此外，該構裝結構復包括^曰曰 及線路增層結構35。 兀彳干 杯SI玄承載板3〇係由有機材料形成之單層板或多層 料其中之一i所製成由金屬、陶究及高散熱無機材 r曰η體晶片320係具有多數電極墊320a，且該半導 係：有”二可t置於該導熱塊310上。該被動元件322 於該承载板30上 被動70件322係可直接接置 片層33係具有多數開孔330以露出該半導體晶 片32j及该被動元件322之電極墊32〇a、322a。 …該線路層34,係形成於該介電㉟33上，且 係透過形成於該介電層中導 " 丰導蝴曰u 包s甲之¥电結構340電性連接至該 •版日日片320及該被動元件322之電極墊32〇&、32^。 该線路增層結構35係形成於該線路層34上且與該線 18413 15 1283010 上電二連接。此外’該線路增層結構35之外表面之 則：成有多數電性連接墊354，且於該最外層線 运上知被復有一係如防焊層 ^ ^ ^ . 干曰之矣巴緣保護層36，該絕緣保 4層36係具有多數開口以外 ^ m ^ ^ 出该電性連接墊354，用以 之導電元件37,俾供接置於該承載板30 子=上之該半導體晶片32G得以電性導接至外部電 圖至4E圖所示，係為詳細説明本發明之晶片 肷埋式構裝結構之製法第二實施例之剖面示意圖。 請蒼閱第4A圖，首先提供第一承載板4〇及第二承載 反4卜並於該第一承載才反4〇中形成開〇 _，復以導執材 料填充於該開π糊中以形成導熱塊倒，藉以形成第一 承載結構4a。同時於該第二承載板41中對應該第一承載 板開口 400位置形成有開口 41〇，以將半導體晶片㈣收 納且固定於該開口 41〇中，此外，該第二承載板“中復可 形成有開口 412用以收納並固定至少一被動元件432,藉 以形成第二承載結構4b。 。。上述該第-、第二承載板4G、41可由有機材料製成 之早層板或多層板。該導熱塊42G可由金屬、陶究及高散 熱無機材料其中之一者所製成。該半導體晶片43〇係具有 多數電極墊430a，而該被動元件432係具有多數電極墊 432a 〇 請參閱第4B圖，將該第二承載結構仆透過一黏著層 (不圖不）接置於该第一承載結構4a上，且使讓半導體晶 18413 16 1283010 片43〇ι對應接置於該第一承載結構乜之導熱塊4如上。 請參閱第4C圖，接著於該第二承載結構仆上形成一 介電層44,且該介電層44係形成有多數開孔44〇: 一 該半導體晶片430及被動元件432上之多數電極= 432a。 ！外地 請參閱第4D圖所示，於該介電層44上形成—線 45，且該線路層45係透過形成於該介電層料中之 構450而電性連接至該半導體晶片43〇及被動元件 攀之電極墊430a、432a。 後續於本發明中，亦可依據實際需要於該介電層44 : = ::5上進行線路增層製程’以構成所需電心計之 線路第4E圖，於該介電層44及線路層45上進行 盖θ a衣程以形成一線路增層結構46，且 構46係雷μ徨技石外μ 八崎〜肩結 妗禮心 路層45。如圖所示，該線路增層 •之線路；糸包括至少一絕緣層460’疊置於該絕緣層460上 電㈣1 462 ’以及穿過該絕緣層460以供該線路層462 為導〜至絕緣層下方線路層45之導電結構462a (例如 為導電盲孔）。 j 有二=層結構46之外表面之線路層上則形成 —絕缘伴464，且於該最外層線路層上係被覆有 露=二該絕緣保護層47係具有多數開孔以外 供接置^妾藝偏，用以提供植置有導電元件48 ’俾 、 乐—承載板40開口中之導熱塊420上且容設於該 18413 17 1283010 第二承載板開。410中之半導體晶片43〇得以 外UU。此外’應需注意者’㈣線路增層妹構非 以圖不之層數為限，而可因應實際需求增加層數:。 復請蒼閱第5 A i 5 E圖，係為本發 裝結構之製法第二者 日日月瓜埋式構 係與第二〜彳丨Γ ’本實施例之製法 載::構上Π③相同’主要差異在於係可先在第二承 ° 仃、，表路增層製程以完成半導體晶片向外之電性 =承=完成線路增層製程之第二承載結構接置於 如第5A圖所示’首先製備第一及第二承载結構 Π玄弟一承载結構4a具第一承載板40及形成於該第 -承载板開π中之導熱塊42()，該第二承載結構朴具第二 承載板41及容設於該第二承載板開口中之半導體晶片伽 被動元件432，且該半導體晶片43〇及被動元件m上 設有多數電極墊43〇a、432a。 _人+請參閱第5B圖，接著於該第二承載結構4b上形成一 η包層44 ’且该介電層中形成多數開孔440以露出該半導 體晶片430及該被動元件432之電極墊43〇3、432&。 凊麥閲第5C圖所示，於該介電層層44上形成一線路 層45，且該線路層45係透過形成於該介電層開孔44〇中 之導電結構450電性連接至該半導體晶片43〇及該被動元 件432之電極墊430a、432a。 5月麥閱第5D圖，之後復可於該線路層45上進行線路 增層裂程以形成一線路增層結構46，其中，該線路增層結 18 18413 460 1283010 曰 毛性連接至絕緣層下方線路層45之導電結構 462&^此外，該線路增層結構46之外表面之線路層上則形 夕數電性連接墊464，且被覆有一絕緣保護層47，該 、巴、彖保邊層47係具有多數開孔以外露出該電性 464 〇 丄 、凊茶閱第5E圖，將該完成線路製程之第二承載結構 朴透過了黏著層（未圖示）接置於該第一承載結構4a上， 且使忒半導體晶片430係對應於該導熱塊420位置處；最 Ϊ於^、絕緣保護層47之開孔中的電性連接塾464上形成導 透過上述製程形成之晶片嵌埋式構裝結構係包括：具 開口 400之第一承載板4〇,且於該開口彻中形成有導熱 塊4 2 0 ;接置於該第—承載板4 Q上之第二承载板*!，且= 第二承載板4〗中對應該第一承載板開口 4 〇 〇位置形成有開 _ 口 410以露出該導熱塊42〇 :半導體晶片43〇係接置於該 導熱塊420上且容設於該第二承載板開口 41〇中；形成於 該第二承載板41及該半導體晶片43〇上之介電層;以 及形成於該介電層44上且與該半導體晶片43〇電性連接之 線路層45。此外，本發明之晶片篏埋式構i结構復包括至 少一接置於該第一承載板4〇上且埋設與該第二承載板Μ 中之被動元件432 ’以及形成於該線路層45上且與該線路 層45電性連接之線路增層結構46。此外，該線路增層結 構4 6之外表面之線路層上則形成有多數電性連接塾S^， 18413 19 1283010 且於該最外層線路層上係被覆有一絕緣保護層47，該絕緣 保暖層47係具有多數開孔以外露出該電性連接墊464，用 以提供植置有多數之導電元件48。 相較於習知技術，本發明之構裝結構及其製法，主要 係將半導體晶片接置於承載板（或第—承載板）開口中所 形成的導熱塊上，並直接自該晶片完成其向外之電性連 接，藉以形成一晶片嵌埋式構裝結構，因此本發明可藉由 。玄承载板與形成於該承載板之組合結構，以平衡製程之溫 ^變化對構裝結構所產生的熱應力，從而可避免製程溫^ =過程中構裝結構麵曲現象之產生，同時可避免習知技 術中猎由增加散熱板厚度導致構裝結構厚度、重量及製程 問題。又，本發明可依據實際設計需要:: 動元件及被動元件，進而可形成整合有多 件之模組化構裝結構，以符合現今 路声上ΑS明之晶片嵌埋式構裝結構之介電層及4 曰，後可進行祕增層製程，藉以在 、 晶片之承載板上形成高密度及細線人： 時可在崎跋έ士描此生 夕層、、表路結構’戶 了了在aL卜表面植設複數導電 承載板中之半導體晶片得以直 ：肖以供肷㈣ 此，本發明亦可整A s # 至外部裝置，区 ^ J正。日日片承載件之製造與 各戶端較大需求彈性以及簡化半、提供 問題。 ^業者製程與介面協調 再者本鲞明之晶片嵌埋式構f M .. 筹衣、4構之導熱塊係由高 18413 1283010 =熱之金屬材料、陶变材料、無機材料其中之_ =可藉由該導熱塊作爲散熱路經將直接接置於並上衣之半 帽生的熱量快速、有效的散逸至外界，延 、+ ¥胆晶片之舞命及構裝結構之可靠性。 ▲上述實施例僅為例示性說明本發明之原理及其功 而非用於限制本發明。任何熟習此項技藝之人士均可 在不違背本發明之精神及㈣下，對上述實施例進行修 改。因此本發明之制保護範圍，應如後述之申請專 圍所列。 【圖式簡單説明】 =1圖係為習知之覆晶式半導體元件剖面示意圖； 第2圖係為美國專利第6,841，413號之剖面示意圖； 、〜第3 A至3E圖係為本發明之晶片嵌埋式構裝結構之製 法第一實施例之剖面示意圖； 第4A至4E圖係為本發明之晶片嵌埋式構裝結構之製 去第二實施例之剖面示意圖；以及 、第5A至5E圖係為本發明之晶片嵌埋式構裝結構之製 去弟二貫施例之剖面示意圖。 【主要元件符號說明】 11 日曰片 110 電極墊 12 金屬凸塊 13 電路板 13〇 接觸銲墊 18413 21 1283010 14 底膠 15 預銲錫凸塊 21 散熱板 230, 250,270 開孔 22 晶片 221 電極墊 24,25 線路層 30 承載板 300 開口 330,440 開孔 310,420 導熱塊 320,430 半導體晶片 320a5322a5430a5432a 電極墊 33,44 介電層 34,45 線路層 340,450 導電結構 322,432 被動元件 35?46 線路增層結構 350,460 絕緣層 352,462 線路層 352a，462a 導電結構 354,464 電性連接墊 36,47 絕緣保護層 37,48 導電元件 22 18413 1283010 40 第 41 第 400,410,412 開 4a 第 4b 第 一承載板 二承載板 v 一承載結構 二承載結構External printed circuit board. Since IBM introduced the Flip chip package technology in the early 1960s, the flip chip technology is characterized by the fact that the electrical connection between the semiconductor wafer and the substrate is transmitted through the solder bumps compared to the wire bond technology. Not a general gold line. The advantage of this flip chip technology is that the technology can increase the package density to reduce the size of the package component. At the same time, the flip chip technology does not need to use a long metal wire, so the electrical performance can be improved to meet high density, High speed semiconductor device requirements. In the current flip chip technology, the surface of the semiconductor wafer is provided with 5 18413 1283010 ===lectrc), and the circuit board for carrying the chip is also 4=contact pad, on the wafer and You can also sigh between the boards! Dry tin bumps or other conductive adhesive materials, such that the sexual contact surface is facing downwards: the sundial, the electric block or the conductive adhesive material is raised on the crystal ^5, wherein the tin tin cam n, and the circuit board Electrical input / I/O and mechanical connections. Please refer to FIG. 1 for the description of the upper part, the flip-chip semiconductor element 12 of the known name, and the metal bumps and the contact pads of the book board 13 formed on the electrode layer 110 of the thousand 11 The pre-solder bumps 15 of 13() are soldered to the corresponding metal bumps 12 by a pre-fabrication of the embossed 12-bumps 15 made of the fabric to form a solder joint. In addition, a gap between the slabs 13 can be entered: in the sheet 11 and the electric and the circuit cup η „, with the bottom 骖 14 to suppress the thermal expansion difference of the wafer 11 and reduce the stress of the solder joint It is said that the flip chip packaging technology needs to pass the bump |y process, the tempering process and the filling process to complete the semiconductor H riding system, which not only improves the process steps, but also the electrical connection with the circuit board. The addition of the system is accompanied by the formation of a reliable wind crystal in the process for the semi-conducting problem piece 2::=Electrically connected solder structure, thus facing the quality of the environmentally friendly tin structure:::, after the process 'The resulting weld quality is reduced. The degree Μ' leads to the electrical connection of the final product. In addition, the conventional packaging technology attaches the semiconductor to the top surface of the board and then wire (w J: _ joint package, and Attached to the back of the substrate _,:=:;;^ 18413 1283010 . . to the purpose of high number of feet, but due to the difficulty of carving the surface of the circuit board to increase the area and volume limit to make the size of the two surfaces, thus unfavorable Small monks in semiconductor components, structural dimensions And the improvement of the performance. The process of the semiconductor component is firstly carried out by the wafer carrier to produce a wafer carrier suitable for the semiconductor component, such as a substrate or the next day, and then the wafer carrier is transferred to the semiconductor package. The industry's Bushan = day, (four), and ball planting processes, and finally, the customer can complete the customer: Jin: eight electronic components of the semiconductor components. In the process involving different process manufacturers have chip carrier manufacturers and semiconductor packaging companies), therefore : In the continuous manufacturing process, not only the steps are complicated, but the interface integration is not easy, and it does not meet the elasticity of change of demand and economic benefits. 'Even again, with the vigorous development of the electronics industry, electronic products are gradually developing and high-performance research and development. In order to meet the packaging requirements of semiconductor package structure (Integral0n) and miniaturization, the heat generated by the semiconductor wafer during operation will be significantly increased. 2 The heat generated by the semiconductor wafer will be effectively dissipated in time. Seriously shorten the performance and life of the D-conductor wafer. One is to bury the semiconductor wafer into the substrate. Figure 2 is a splicing of a semiconductor wafer 22 (a wall-like die) on a heat spreader 21, as in U.S. Patent No. 6,841,413. The active surface has an electrode pad 221 (electrical c〇nnected), and the upper surface of the heat dissipation plate 2 i and the active surface of the semiconductor wafer 22 form a dielectric layer 23 (dieleCtnc ]ayer), and 18413 7 1283010 · the dielectric The layer 23 is formed with an opening 23 through the patterning process to expose the electrode pad 221 of the semiconductor wafer 22, and a conductive layer 24 is formed on the surface of the dielectric layer 23 and (4) and (4), and then the dielectric layer 23 is formed. And forming another dielectric layer 25 on the surface of the circuit layer 24, and the dielectric layer 25 is formed with an opening 25G through a patterning process to expose the connection portion of the circuit layer 24, and then on the surface of the dielectric layer 25 and Another circuit layer 26 is formed in the opening 250, and an insulating material layer 27 is formed on the surface of the dielectric layer 25 and the circuit layer %, and the insulating protective layer 27 is patterned by a process Φ to open y. The opening hole 270 is used to extend the electrical connection pad 2 61 of the circuit layer 2 6 , and finally Further, a conductive member 28 such as a solder ball is formed on the surface of the exposed electrical connection pad 261. . The semi-V-body wafer 22 is first placed on the surface of the heat sink 2, so that the semiconductor wafer 22 can be directly dissipated by the heat sink 21 to solve the above-mentioned drawbacks. However, due to the difference in the coefficient of thermal expansion (CTE) between the heat sink 2 and the dielectric layer 23, the package structure is subjected to temperature changes in the process, such as baking and subsequent In the environment of thermal cycle operation, different thermal stresses (Thernial Stress) are generated on each component, which may cause warpage of the structure. In severe cases, delamination or even squeezing may occur between the structural layers. To the semiconductor wafer, the wafer is broken. ^ If the thickness of the hot plate is increased to stabilize the temperature change, the package structure is thermally deformed to change the substrate warpage. However, adding the thickness of the heat sink will increase the volume and thickness of the finished package structure, and will increase the process cost. Therefore, how to propose a wafer embedded package structure to overcome the light weight and weight increase and interface integration of the structure in the process of the package structure of the 18413 8 1283010: t clothing,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, The embedded structure of the wafer and the main purpose of the method and the phenomenon of causing a knot in the process of the body-worn process to avoid the semi-conducting gentleman structure and the other purpose is to provide a wafer embedded structure. Re-head (four) in the cost ° structure and its method of production, in the drums of the human body, the embedded structure is used to provide the space for the 0 positive & day carrier and wafer assembly process, by borrowing, each household Great demand elasticity, face-to-face integration problem. Yishe knows, costs and media another object of the invention is to install the structure and its method to have the heat of the f = I buried structure. The device is fabricated during the operation of the film: 2 = Π :: The invention discloses a wafer embedded with an opening, and a heat conducting block is formed in the opening; a semiconductor wafer is attached to the pen block, and the bearing is Board riding semi-conducting... The sheet has a majority of electrode pads; a dielectric layer, and an electrode of the dielectric layer; and an a U line layer formed on the dielectric layer is electrically connected to the electrode of the semiconductor electrode 18813 9 1283010. = Road: Γΐ can be on the circuit layer Forming a line build-up structure on the line, and connecting the "e^ book to the circuit layer, and on the surface of the line, the surface of the circuit is + 首 + + 构 构 构 , , , , , The electronic device of the chip electric part. 甩 "The method of manufacturing the external structure to the external chip to be buried structure, the package-opening: and: the irt carrier plate" is formed at least in the first carrier plate The heat-conducting block is formed in the middle, and at the same time, the opening position of the first carrier plate is also opened in the door carrier plate formed by the ancient female flute-71, $戟, and the mouth, and is connected to the opening of the second carrier plate. a sheet, which is formed to form a second load-bearing structure; the 兮筮_-bearing structure is placed in the 哕筮 _ "Fu", the 5 haidi one is placed in the corresponding guide (four), and the semiconductor wafer is a dielectric layer 'and exposing the dielectric layer to the outside of the dielectric layer - forming a wiring layer on the dielectric layer The pad electrode; and an electrical switch of a semiconductor wafer. The road layer is connected to the ^Jun, the slave can be on the line; the μ-tour, L, Ojb L structure, and the electric layer of the line is added: 'The outer surface of the line-added structure is planted more = road layer And electrically connecting the wafer to the external electronic device number W7L' for the semiconductor. The invention further discloses that the wafer is embedded in the same manner as the above method, but in the method of forming the dielectric layer, the dielectric layer is formed on the upper surface. The circuit layer, 1 ^ is placed on the first receiving structure prior to the second load-bearing structure, and the second carrier formed with the circuit layer is sent through the above process. The present invention comprises: at least _f1 ” - a wafer embedded structure ... an open carrying plate, and the opening is formed with 18413 10 1283010 thermal block, at least one and more enthusiasm -, upper, " guide (four) b. one into the + conductor The wafer is “connected to the A′...,) the germanium layer is formed on the carrier and the semiconductor wafer, and the electrode of the semiconductor wafer is exposed; and the circuit is formed by the dielectric On the layer and with the semiconductor wafer::: the embedded structure of the wafer includes Formed in the second: a line build-up structure electrically connected to the remote circuit layer. The present invention further discloses a wafer embedded structure junction> a first carrier plate that is opened into at least one opening, And passing through the opening=there is a hot block; the second carrier board is disposed on the first carrier board and has at least the opening to output the heat conducting block; at least—connected to: the second carrier board An open semiconductor wafer, the semiconductor = ^ electrode pad is formed on the second carrier and the semiconductor wafer: a dielectric layer, and the dielectric layer exposes the semiconductor wafer: and is formed on the dielectric layer And in the semi-conducting U, the circuit layer, wherein the structure, the bipolar connection and the line layer electrically connected to the circuit layer are electrically connected to the surface of the conductive layer. The layer, the structure, and the formation Compared with the circuit, the (four) m buried type is mainly used to connect the semiconductor wafer to the opening formed in the carrying plate: the first, the upper block can be connected by the carrier plate, the heat conducting block and the dielectric layer. 3 'to avoid temperature changes in the process to produce a slight curvature of the structure = Increase the thickness of the heat sink in the conventional technology to improve the thickness, weight and process cost of the structure caused by the structure of the process structure. 18413 11 1283010 Layers are repeated =::: The dielectric layer of the embedded structure of the wafer and the carrying process of the circuit board 'therefore, in which I buried the semiconductor crystal, a plurality of conductive:: structure can be implanted on the outer surface of the circuit structure, and the semiconductor wafer in the carrier can be directly至夕=Embedded in this. 'The invention can also integrate the wafer bearing: II. Tionghong 6 ^, Yi Yi and the Japanese film assembly process, coordination problem semiconductor industry process and interface The electrical quality of the product. Dependent, :== The heat conduction block for the semiconductor wafer is connected by the gold conductor machine (4) 4, and (10) the heat generated by the half length of the semiconductor can be dissipated to the outside in a timely and effective manner. , the fate of the Yanniu V limbs and the reliability of the structure. [Embodiment] The following is a description of the embodiments of the present invention by way of specific specific embodiments. Those skilled in the art can readily appreciate other advantages and functions. The invention may be practiced or applied by other different embodiments. The details of the present invention are also subject to modification and alteration without departing from the spirit and scope of the invention. Further, in order to simplify the drawing and the description, in the fine structure, two semiconductor wafers are buried as an example, but the scope of the present invention is not limited thereto. As shown in Figs. 3A to 3E, there is shown a cross-sectional view showing a first embodiment of the method for fabricating a wafer-embedded structure of the present invention. It should be noted that these drawings are simplified schematic diagrams and are only illustrated in a schematic manner: the process of the board of 18413 12 1283010 7 . However, the drawings:: 'The components they display are not the actual implementation of the two aspects: the number of pieces, shape and size ratio is - the choice of the choice ^ and the layout of the piece may be more complicated . The board 3〇tt is read from the figure, firstly provided with a carrier plate 3G, and in the bearing, there is an opening 3〇0, the opening 300 is filled with a heat conductive material, and a heat conducting block is formed in the middle, for Followed by the thermal block ► into it. , set + conductor wafer. The carrier plate 30 is made of an organic material layer or a multi-layer board, and the heat-conducting block 31 can be made of, for example, one of a metal, a ceramic, or a heat-resistant heat-dissipating material. Please refer to Figure 3B. Next, the semiconductor chip 320 is attached to the heat conducting block 31A. The semiconductor wafer 32 has a plurality of electrode pads, and the tantalum is placed on the guide block 31 through a thermally conductive adhesive layer (not shown). Further, at least one of the carrier plates 3 can be attached to the carrier. . / Passive component 322 having a plurality of electrode pads 322\, and the passive component 322 is attached to the carrier plate 3 through an adhesive layer (not shown). Referring to FIG. 3C, a dielectric layer 33 is formed on the carrier substrate 3, the semiconductor wafer 3A and the passive component 322, and the dielectric layer is formed with a plurality of openings 330 to expose the semiconductor wafer. 32〇 and the electrode pad 3 of the passive component 322, 322a. The dielectric layer 33 can be, for example, an epoxy resin (EP〇xy resin), a polyethylamine (p〇丨yimide), a cyanide ester, a glass fiber (Giass flbe〇, a bis-succinate). BT, Bismaleimide triazme or mixed epoxy resin and glass fiber material. 18413 13 1283010 Please refer to the 3D figure, a line is formed on the dielectric layer 33, ^ the circuit layer Μ Electrically connected to the semiconductor wafer and (4) / second: the wiring layer 34 is permeable to the conductive structure 340 formed on the dielectric layer 33 (for example, a conductive blind via or conductive bump? to the semiconductor wafer 320 and the electrode of the passive component 322 are chapter = 2 a. However, the technical system for forming the circuit layer 34 has a variety of techniques and is known as the industry, so it is no longer described here. The invention mainly connects the conductive guides through the heat-conducting block 310 formed in the % opening of the carrier plate, and the support device 30 Two: = and the combination of the dielectric layer 33, in order to avoid the process temperature change into a ^ structure to produce a tortuo phenomenon ' while avoiding It is known that the thickness of the structure and the increase in the weight of the structure caused by the increase in the thickness of the heat sink are missing. The clothing is made into the 3E ® and can be added to the circuit layer 3 to increase the layer process. Detach the mark, form a line build-up structure % on the road surface H Yuan road layer 34, and make the (four) road build-up structure 35 electrically connected to the circuit layer %. Longzhong, the line build-up structure 3 5 series The insulating layer 35 is disposed on the insulating layer 350 and is disposed on the insulating layer 350, and the insulating layer 350 is passed through (the ice layer 352 is electrically connected to the circuit layer below the insulating layer). Conductive structure 352a of 34, the conductive structure 352a, ,. In addition, outside the build-up structure 35::: the circuit layer is formed with a number of *4 (3) 3 5 4, and is covered with _ = edge protection layer 36 And the right side of the door force,, M + & Ba "except the number of openings open the electrical connection pad 354 "transfer and the number of conductive elements 37 ' for example, solder balls (s〇) age ba (1), Guide 18413 】 4 1283010 electric column or welding column, which can be connected to the carrier plate 3 〇 heat conduction block 3 〇 conductor wafer% 〇 The connection to the external electrons is set. In addition, it should be noted that the line build-up structure is not limited to the number of layers shown: the number of layers should be increased according to actual needs. The embedded structure of the wafer formed by the above process The structure includes: a carrier board 30 having an opening 300, and a heat conducting block 310 on the carrier board 3; a semiconductor wafer mounted on the heat conducting block 31A. The carrier board 30 and the semiconductor wafer are formed on the board The dielectric hum of the 32 ;; ' > and the circuit layer 34 formed on the dielectric layer 33 and electrically connected to the 32 。. In addition, the package structure includes a plurality of lines and a build-up structure 35. The dry cup SI sinusoidal carrier 3 is made of a single layer or a multilayer material formed of an organic material. The metal, ceramics and high heat dissipation inorganic material 曰 体 body wafer 320 has a plurality of electrode pads 320a. And the semi-conducting system: there is a "two can be placed on the heat-conducting block 310. The passive component 322 is passively on the carrier plate 30, 70 pieces 322 can be directly connected to the sheet layer 33 has a plurality of openings 330 to expose The semiconductor wafer 32j and the electrode pads 32A, 322a of the passive component 322. The circuit layer 34 is formed on the dielectric 3533, and is formed in the dielectric layer by a conductive layer. The electrical structure 340 of the package s is electrically connected to the stencil 320 and the electrode pads 32 〇 & 32 of the passive component 322. The circuit buildup structure 35 is formed on the circuit layer 34. And connected to the line 18413 15 1283010 power-on two. In addition, the outer surface of the line build-up structure 35: a plurality of electrical connection pads 354, and the outermost line is transported to know that there is a system Solder layer ^ ^ ^ . Dry 曰 矣 缘 保护 保护 保护 36 36 , , , , 36 36 36 36 36 36 36 36 The electrical connection pad 354 is used for the conductive component 37, and the semiconductor wafer 32G, which is placed on the carrier board 30, is electrically connected to the external electrogram to the figure 4E. DETAILED DESCRIPTION OF THE DRAWINGS A cross-sectional view of a second embodiment of a method for fabricating a buried structure of a wafer according to the present invention is provided. Please refer to FIG. 4A to first provide a first carrier plate 4 and a second carrier member 4b and the first carrier. Forming an opening _ in the reverse ,, the filling material is filled in the opening π paste to form a heat conducting block, thereby forming the first bearing structure 4a. At the same time, the first bearing is corresponding to the second carrier 41 An opening 41A is formed in the plate opening 400 to receive and fix the semiconductor wafer (4) in the opening 41. Further, the second carrier plate may be formed with an opening 412 for receiving and fixing at least one passive component 432. Thereby forming a second load-bearing structure 4b. . . The first and second carrier plates 4G, 41 described above may be made of an organic material or an early laminate or a multilayer laminate. The heat conducting block 42G can be made of one of metal, ceramics and highly heat-dissipating inorganic materials. The semiconductor wafer 43 has a plurality of electrode pads 430a, and the passive element 432 has a plurality of electrode pads 432a. Referring to FIG. 4B, the second carrier structure is placed through an adhesive layer (not shown). The first load-bearing structure 4a is disposed on the heat-conducting block 4 of the first load-bearing structure by the semiconductor die 18413 16 1283010. Referring to FIG. 4C, a dielectric layer 44 is formed on the second carrier structure, and the dielectric layer 44 is formed with a plurality of openings 44: a plurality of electrodes on the semiconductor wafer 430 and the passive component 432. = 432a. ! In the external view, as shown in FIG. 4D, a line 45 is formed on the dielectric layer 44, and the circuit layer 45 is electrically connected to the semiconductor wafer 43 through a structure 450 formed in the dielectric layer. The passive component climbs the electrode pads 430a, 432a. In the following, in the present invention, the line build-up process can be performed on the dielectric layer 44 := ::5 to form the line 4E of the desired core meter, and the dielectric layer 44 and the line are formed. The layer 45 is subjected to a cover θ a process to form a line build-up structure 46, and the structure 46 is a Ray 徨 徨 徨 μ 八 八 〜 肩 肩 肩 肩 肩 肩 。 。 。 。 。 。 。 。. As shown in the figure, the circuit of the circuit layer is formed; the germanium includes at least one insulating layer 460' stacked on the insulating layer 460 to electrically (4) 1 462 ' and pass through the insulating layer 460 for the circuit layer 462 to be guided to The conductive structure 462a of the circuit layer 45 under the insulating layer (for example, a conductive blind hole). j having an outer surface of the second layer structure 46 is formed with an insulating 464, and the outermost wiring layer is covered with a dew = two. The insulating protective layer 47 has a plurality of openings for connection. The second carrier plate is opened on the heat conducting block 420 which is disposed in the opening of the conductive member 48', the music-bearing plate 40, and is accommodated in the 18213 17 1283010. The semiconductor wafer 43 in 410 can be externally UU. In addition, the 'required attention' (4) line addition layer is not limited to the number of layers, but can increase the number of layers according to actual needs: Please refer to the 5th A i 5 E diagram, which is the second method of the manufacturing method of the hairpin structure, and the second 彳丨Γ 构 彳丨Γ 彳丨Γ 彳丨Γ 彳丨Γ 彳丨Γ 彳丨Γ 彳丨Γ 彳丨Γ 彳丨Γ 本 本 : : : : : : : : : : The same 'main difference is that the second load-bearing process can be completed in the second pass, the surface-addition process to complete the electrical properties of the semiconductor wafer. = The second load-bearing structure of the completed line-adding process is placed as shown in Figure 5A. The first load-bearing structure 4a has a first carrier plate 40 and a heat-conducting block 42 () formed in the first carrier plate opening π, which is prepared as shown in the first embodiment. The second carrier plate 41 and the semiconductor wafer absorbing passive component 432 are disposed in the opening of the second carrier, and the plurality of electrode pads 43A and 432a are disposed on the semiconductor chip 43 and the passive component m. Referring to FIG. 5B, an n-cladding layer 44' is formed on the second carrier structure 4b, and a plurality of openings 440 are formed in the dielectric layer to expose the semiconductor wafer 430 and the electrode pads of the passive component 432. 43〇3, 432&. As shown in FIG. 5C, a circuit layer 45 is formed on the dielectric layer 44, and the circuit layer 45 is electrically connected to the conductive structure 450 formed in the dielectric layer opening 44. The semiconductor wafer 43 and the electrode pads 430a, 432a of the passive component 432. In May, the 5D image of the wheat is read, and then the line build-up process is performed on the circuit layer 45 to form a line build-up structure 46, wherein the line build-up junction 18 18413 460 1283010 is bristle-bonded to the insulation layer. The conductive structure 462 of the lower circuit layer 45 is further provided with a conductive connection pad 464 on the circuit layer on the outer surface of the circuit build-up structure 46, and is covered with an insulating protective layer 47. The layer 47 has a plurality of openings to expose the electrical 464 〇丄, and the tea is read 5E. The second load-bearing structure of the completed circuit process is placed on the first load through an adhesive layer (not shown). In the structure 4a, the germanium semiconductor wafer 430 is corresponding to the position of the heat conducting block 420; the electrical connection layer 464 in the opening of the insulating protective layer 47 is formed to be embedded in the wafer formed by the above process. The structure comprises: a first carrier plate 4 having an opening 400, and a heat conducting block 410 is formed in the opening; and a second carrier plate* placed on the first carrier plate 4Q! And = the second carrier plate 4 corresponds to the first carrier opening 4 〇 The position is formed with an opening 410 to expose the heat conducting block 42. The semiconductor wafer 43 is electrically connected to the heat conducting block 420 and received in the second carrying plate opening 41A. The second carrying plate 41 is formed on the second carrying plate 41. And a dielectric layer on the semiconductor wafer 43; and a wiring layer 45 formed on the dielectric layer 44 and electrically connected to the semiconductor wafer 43. In addition, the wafer buried structure of the present invention includes at least one passive component 432 ′ disposed on the first carrier plate 4 and embedded in the second carrier plate 以及 and formed on the circuit layer 45. And a line build-up structure 46 electrically connected to the circuit layer 45. In addition, a plurality of electrical connections 塾S^, 18413 19 1283010 are formed on the circuit layer on the outer surface of the line build-up structure 46, and an insulating protective layer 47 is coated on the outermost circuit layer, and the insulating thermal insulation layer is The 47 series has a plurality of openings to expose the electrical connection pads 464 for providing a plurality of conductive elements 48. Compared with the prior art, the structure of the present invention and the manufacturing method thereof are mainly for attaching a semiconductor wafer to a heat conducting block formed in an opening of a carrier board (or a carrier layer), and directly completing the wafer from the wafer. The present invention can be utilized by externally electrically connecting to form a wafer embedded structure. The combination structure of the sinuous load-bearing plate and the load-bearing plate can balance the thermal stress generated by the temperature change of the process on the structure of the structure, thereby avoiding the occurrence of the surface curvature of the structure during the process temperature and the process; Avoiding the problem of thickness, weight and process of the structure caused by increasing the thickness of the heat sink in the prior art. Moreover, the present invention can be based on actual design requirements:: dynamic components and passive components, and thus can form a modular structure with integrated components to conform to the dielectric of the current embedded structure of the circuit. After the layer and 4 曰, the secret build-up process can be carried out, so as to form a high-density and thin-line person on the carrier plate of the wafer: When the singer can describe the eve layer, the surface structure is 'household' in aL The surface of the semiconductor wafer in the plurality of conductive carrier plates can be straightened: (4) Therefore, the present invention can also integrate the A s # to the external device, and the area is positive. The manufacture of day-to-day sheet carriers and the greater demand elasticity of each terminal and the simplification of the problem. ^Industry Process and Interface Coordination 鲞本鲞明's Wafer Embedded Structure f M.. The heat-conducting block of the 4th frame is made up of high-level 18413 1283010 = hot metal material, ceramic material, inorganic material _ = The heat-dissipating block acts as a heat-dissipating path to quickly and effectively dissipate the heat generated by the half-hat directly attached to the top and the outer layer, and the reliability of the dance and the structure of the structure. The above-described embodiments are merely illustrative of the principles and advantages of the invention and are not intended to limit the invention. Any person skilled in the art can modify the above embodiments without departing from the spirit of the invention and (d). Therefore, the scope of protection of the present invention should be as listed in the application section described later. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 2 is a schematic cross-sectional view of a conventional flip-chip semiconductor device; FIG. 2 is a schematic cross-sectional view of U.S. Patent No. 6,841,413; BRIEF DESCRIPTION OF THE DRAWINGS FIG. 4A to FIG. 4E are cross-sectional views showing a second embodiment of the wafer embedded structure of the present invention; and, FIG. 5A to 5E is a schematic cross-sectional view of a second embodiment of a wafer embedded structure of the present invention. [Main component symbol description] 11-day wafer 110 electrode pad 12 metal bump 13 circuit board 13〇 contact pad 18413 21 1283010 14 primer 15 pre-solder bump 21 heat sink 230, 250, 270 opening 22 wafer 221 electrode pad 24 25 circuit layer 30 carrier plate 300 opening 330, 440 opening 310, 420 thermal block 320, 430 semiconductor wafer 320a5322a5430a5432a electrode pad 33, 44 dielectric layer 34, 45 circuit layer 340, 450 conductive structure 322, 432 passive component 35? 46 line buildup structure 350, 460 insulation layer 352, 462 line Layer 352a, 462a Conductive structure 354, 464 Electrical connection pad 36, 47 Insulation protective layer 37, 48 Conductive element 22 18413 1283010 40 41st 400, 410, 412 Open 4a 4b First carrier plate 2 carrier plate v 1 load bearing structure 2 load-bearing structure

23 1841323 18413

Claims (1)

1283010 卜、申請專利範圍： ./ 一種晶片嵌埋式構裝結構之製法，係包括： :供-形成有至少一開口之承載板，且於該 開口中形成有導熱塊； 將半導體晶片接置於該導熱塊上，且該 具有多數電極墊； 卞v肢日日片 :二=板及該半導體晶片上形成一介電層 电層形成有開孔以外露出該半導體晶片之電極 赞，以及 性連：=:層；形成一線路層’且使該線路層得以電 Γ生連接至该+導體晶片之電極墊。 I 1申軌圍第1項之晶片嵌埋式構裝結構之製 路增層結構係電性連接至該線^路日層〜構，且該線 3.如申請專利範圍第2項之晶片嵌 ，法，復包括於該線路增層結構之外 衣二構之製 件，:供該半導體晶片電性連接^卜^^導電元 t ^申4專利範圍第1項之晶片嵌埋式構 法，該承載板上係接置有至少—被構之製 層電性連接至該被動元件。 牛’且使該線路 5 :申=利二圍gl項之晶片嵌埋式構 6·如申請:利=載議有機封料製成。 法，i中，項之晶片嵌埋式構裝結構之製 塊係由金屬、陶究及無機高散熱材料 24 18413 1283010 其中之一者製成。 如申請專利範圍第1項之晶片嵌埋式構裝結構之製 法，其中，該承載板、導熱塊及介電層之組合得改盖後 續製程中之翹曲現象。 广8· 丨一種晶片嵌埋式構裝結構之製法，係包括： 提供形成有至少一開口之第一承載板及第二承載 板，且於該第一承載板開口中形成有導熱塊，藉以形成 第:承載結構，並將具多數電極墊之半導體晶片容置於 該第二承載板開口中，藉以形成第二承載結構；以及 〜於該第一承載結構上接置第二承載結構，其中，該 tr承载板具有—介電層、線路層及線路增層結構，以 導體晶片對應接置於該導熱塊處，及該增層線路 二電層之導電結構而電性連接至該半導 c: ^申請專利範㈣8項之晶片嵌埋式構裝結構之製 其中’係於㈣二承載結構上先形成—介電 路層及線路增層結構，再接 10 rh ^ 女1 7、4弟一承載結構。 •女申请專利範圍第8項之曰 法， / 負之日日片肷埋式構裝結構之製 /、中’係先將該第二承載έ士槿 構，再於該第二承紗構it㈣置於該弟-承勸 路增層結構。載、，°構上形成一介電層、線路層及名 1 ·如申請專利範圍第8 曰山 法，作4 ) 貝之曰曰片肷埋式構裝結構之製 又匕括於该線路增層纟士 數電性連接墊，、、 籌外表面之線路層上形成多 連接塾亚於該線路增層結構之外表面形成-絕 18413 25 1283010 t =二該絕緣保護層形成有複數開孔以外露出該 申：專利範圍第u項之晶片嵌埋輸結構之製 节半導1’日該絕緣保護層之開孔植設有導電元件，以供 ^ + V肢日日片與外部電子裝置電性連接。 13.=申請專利範㈣8項之晶片嵌埋式構裝結構之f =二；Γ被動元件係可容置於該第二承載板 过泉路層得以電性連接至該被動元件。 ·=申請專·圍第8項之晶片嵌埋式構裝結構之製 15. 如申利及第二承載板係由有機材料製成。 法，並中二趣項之晶片嵌埋式構裝結構之製 其中:-者製Γ:塊係由金屬、陶究及高散熱無機材料 16. -種晶片嵌埋式構裝結構，係包括： I導熱^少―—之承，且該承載㈣口中形成有 至少一接置於該導熱塊上半導 體晶'片係具有多數電極塾；+ 一片，且該半導 該介該半導體晶片上之介電層，且 墊；以及成有開孔以外露出該半導體晶片之電極 —形成於該介電層上之線 接至該半導體晶片之電極塾。 電性連 】7·如申請專利範圍第16項之晶片歲埋式構裝結構，其 】84】3 26 1283010 。亥線路層上復形成有線路增層』 結構係電性導接至該線路層。曰、，。’ f亥線路增層 8.如申峙專利範圍第】7項曰山 中，哕岣玖+、，a i 、日日片甘欠埋式構裝結構，JL 可供該半導體晶片電性連接至外部1夕上電元件，俾 19.如申請專利範圍第’子裝置。 中 J乾圍弟16項之晶片敌埋式構裝結構，盆 。亥承載板係由有機材料製成。 〃 2〇.t申請專利範圍第16項之晶片嵌埋式構裳結構，盆 中，该導熱塊係由金屬、陶瓷 -者所製成。 ，文H賴材料其中之 21=申請專利範圍第16項之晶片嵌埋式構裝結構，其 中5邊承載板上係可接置至少一 二 得以電性連接至該被動元件。 ’且該線路層 22· 一種晶片嵌埋式構裝結構，係包括： 具有至少一開口之第一承載板，且於該第一承載板 開口中形成有導熱塊； 第二承載板，係形成於該第一承載板上，且該第- 承載板中對應該第一承載板開口處形成有開口以露出 該導熱塊； 具電極墊之半導體晶片，係容設於該第二承載板開 口中且接置於該導熱塊上； 介電層，係形成於該第二承載板及該半導體晶片 上且鉻出该半導體晶片之電極塾；以及 一線路層，係形成於該介電層上且電性連接至該半 27 18413 1283010 導體晶片之電極墊。 2 3. ^申，專利範圍第2 2項之晶片嵌埋式财 線路層上復形成一線路增層結構，且，其 結構係可電性導接至該線路層。 〜、泉路增層 24.:申請專利範圍第23項之晶片嵌埋式構裝 中，該線路增層結構外表面係植設有多數導=，其 可供該半導體晶片電性連接至外部電子褒置π件，俾 2 5.申請！利範圍第2 2項之晶片谈埋式構裝結構，发 ，邊第一及第二承載板係由有機材料製成。“ 26. 如申請專利範圍第22項之晶片嵌埋式構農結構，其 中，該導熱塊係由金屬、陶究及無機高散 ； 一者所製成。 卞，、Τ之 27. 如申請專利範圍第22項之晶片㈣式構裝結構，其中， 至少一被動元件係可容置於該第二承載板中，且該 線路層得以電性連接至該被動元件。 18413 281283010 卜, application patent scope: . / a method of manufacturing a wafer embedded structure, comprising: a carrier plate formed with at least one opening, and a heat conducting block formed in the opening; On the heat-conducting block, and having a plurality of electrode pads; 卞v-limb day-to-day film: two = plate and the semiconductor wafer are formed with a dielectric layer, and an electrode is formed to expose the electrode of the semiconductor wafer, and Connected: =: layer; forms a wiring layer ' and allows the wiring layer to be electrically connected to the electrode pads of the + conductor wafer. The circuit-added structure of the wafer embedded structure of the first aspect of the present invention is electrically connected to the line layer to the structure, and the line is as in the wafer of claim 2 The inlay, the method, and the complex are included in the fabric of the additional layer structure of the circuit, and the wafer embedded structure is provided for the semiconductor wafer to be electrically connected to the semiconductor wafer. The carrier board is coupled to at least a structured layer electrically connected to the passive component. The cow's and the line 5: Shen = Li 2 gl of the embedded structure of the wafer 6 · If the application: Lee = said organic seal material. In the method of i, the wafer embedded structure of the item is made of one of metal, ceramics and inorganic high heat dissipating material 24 18413 1283010. The method of claim 1 , wherein the combination of the carrier plate, the heat conducting block and the dielectric layer is modified to warp in a subsequent process. The method for manufacturing a wafer embedded structure includes: providing a first carrier plate and a second carrier plate formed with at least one opening, and forming a heat conducting block in the opening of the first carrier plate, thereby Forming a first: load-bearing structure, and accommodating a semiconductor wafer having a plurality of electrode pads in the opening of the second carrier to form a second load-bearing structure; and attaching a second load-bearing structure to the first load-bearing structure, wherein The tr carrier board has a dielectric layer, a circuit layer, and a line build-up structure, and the conductor chip is correspondingly disposed at the heat conducting block, and the conductive structure of the second layer of the build-up line is electrically connected to the semiconductor c: ^Applicable to the patent (4) 8 wafer embedded structure structure, which is formed on the (four) two-bearing structure to form the dielectric layer and the circuit-added structure, and then connect 10 rh ^ female 1 7 , 4 The younger one bears the structure. • The woman applies for the stipulation of the 8th item of the patent scope, / the negative day of the 肷 肷 肷 构 构 / / / / / 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二It (4) placed in the brother - the road to increase the layer structure. A dielectric layer, a circuit layer, and a name are formed on the structure of the carrier, and the structure is as follows: 1. The method of the 8th 曰山法 of the patent application is as follows: 4) The system of the 构 构 肷 肷 构 匕 匕 匕 匕 匕The electrical connection pad is added to the electrician, and the multi-connection is formed on the circuit layer of the outer surface of the outer layer. The surface of the additional layer is formed on the outer surface of the circuit--18413 25 1283010 t = two. The insulating protective layer is formed with multiple openings. The hole is exposed outside the hole: the patent embedded scope of the wafer embedded structure of the semiconductor semi-conducting 1' day, the opening of the insulating protective layer is provided with conductive elements for the ^ + V limb day and external electronics The device is electrically connected. 13.=Application of the patent (4) The embedded embedded structure of the wafer of f = 2; the passive component can be placed in the second carrier. The spring layer is electrically connected to the passive component. ·=Application for the embedded embedded structure of the eighth item. 8. The Shenli and the second carrier are made of organic materials. The method of the embedded embedded structure of the method of the second and second interesting items is as follows: - the system is made of metal, ceramics and high heat-dissipating inorganic materials. : I heat-conducting less than -, and the carrier (four) port is formed with at least one of the semiconductor crystals on the thermally conductive block, the film has a plurality of electrodes; + one, and the semiconductor is on the semiconductor wafer a dielectric layer, and a pad; and an electrode having the semiconductor wafer exposed outside the opening - a line formed on the dielectric layer is connected to the electrode of the semiconductor wafer. Electrical connection 】 7 · The patented structure of the wafer of the 16th article of the patent scope, 】 84] 3 26 1283010. The circuit layer is formed on the circuit layer of the sea. The structure is electrically connected to the circuit layer. Hey,,. ' fhai line increase layer 8. If the scope of patent application is the seventh] 7 items in the mountain, 哕岣玖+,, ai, Japanese and Japanese pieces are buried in the structure, JL can be used to electrically connect the semiconductor chip to the outside 1st power-on component, 俾 19. as claimed in the patent scope 'sub-device. In the middle of the J dry brother 16 items of the enemy embedded structure, basin. The haul board is made of organic materials. 〃 2〇.t Patent application No. 16 of the wafer embedded structure structure, in the basin, the heat conduction block is made of metal, ceramics. 21: The wafer embedded structure of claim 16 of the patent application, wherein the five-sided carrier board can be connected to at least one of the two to be electrically connected to the passive component. And the circuit layer 22 includes a first carrier plate having at least one opening, and a heat conducting block is formed in the first carrier plate opening; the second carrier plate is formed An opening is formed in the first carrier plate corresponding to the opening of the first carrier plate to expose the heat conducting block; the semiconductor wafer with the electrode pad is received in the opening of the second carrier plate And the dielectric layer is formed on the second carrier and the semiconductor wafer and chrome the electrode of the semiconductor wafer; and a circuit layer is formed on the dielectric layer and Electrically connected to the electrode pads of the half 27 18413 1283010 conductor wafer. 2 3. ^ Shen, the patent embedded range of the wafer embedded buried circuit layer to form a line build-up structure, and its structure can be electrically connected to the circuit layer. 〜,泉路增层24. In the wafer embedded structure of claim 23, the outer surface of the line build-up structure is provided with a plurality of leads = which can be electrically connected to the outside of the semiconductor wafer Electronic device π pieces, 俾 2 5. Apply! The wafer of the second item of interest is discussed in the buried structure structure, and the first and second carrier plates are made of organic materials. " 26. For example, the wafer-embedded cultivating structure of the patent application scope 22, wherein the heat-conducting block is made of metal, ceramics and inorganic high-dispersion; one of them. 卞, Τ 27 27. The wafer (four) structure of claim 22, wherein at least one passive component is accommodated in the second carrier, and the circuit layer is electrically connected to the passive component.
TW094127084A 2005-08-10 2005-08-10 Chip embedded package structure and fabrication method thereof TWI283010B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW094127084A TWI283010B (en) 2005-08-10 2005-08-10 Chip embedded package structure and fabrication method thereof
JP2006215062A JP2007049154A (en) 2005-08-10 2006-08-07 Chip embedded package structure and manufacturing method therefor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW094127084A TWI283010B (en) 2005-08-10 2005-08-10 Chip embedded package structure and fabrication method thereof

Publications (2)

Publication Number Publication Date
TW200707532A TW200707532A (en) 2007-02-16
TWI283010B true TWI283010B (en) 2007-06-21

Family

ID=37851671

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094127084A TWI283010B (en) 2005-08-10 2005-08-10 Chip embedded package structure and fabrication method thereof

Country Status (2)

Country Link
JP (1) JP2007049154A (en)
TW (1) TWI283010B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI426588B (en) * 2010-10-12 2014-02-11 Advanced Semiconductor Eng Package structure and package process

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101058621B1 (en) * 2009-07-23 2011-08-22 삼성전기주식회사 Semiconductor package and manufacturing method thereof
CN115116864A (en) * 2022-07-28 2022-09-27 中国电子科技集团公司第十研究所 BGA chip packaging method

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11233678A (en) * 1998-02-16 1999-08-27 Sumitomo Metal Electronics Devices Inc Manufacture of ic package
JP4336016B2 (en) * 2000-02-29 2009-09-30 京セラ株式会社 Package for storing semiconductor elements
JP4270769B2 (en) * 2000-12-15 2009-06-03 イビデン株式会社 Manufacturing method of multilayer printed wiring board
JP3888943B2 (en) * 2002-04-12 2007-03-07 イビデン株式会社 Multilayer printed wiring board and method for manufacturing multilayer printed wiring board
JP2004296723A (en) * 2003-03-26 2004-10-21 Kyocera Corp Package for containing semiconductor element and semiconductor device
JP4052955B2 (en) * 2003-02-06 2008-02-27 Ｎｅｃエレクトロニクス株式会社 Manufacturing method of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI426588B (en) * 2010-10-12 2014-02-11 Advanced Semiconductor Eng Package structure and package process

Also Published As

Publication number Publication date
TW200707532A (en) 2007-02-16
JP2007049154A (en) 2007-02-22

Similar Documents

Publication Publication Date Title
TWI294694B (en) Led wafer-level chip scale packaging
TWI245388B (en) Three dimensional package structure of semiconductor chip embedded in substrate and method for fabricating the same
TWI264094B (en) Package structure with chip embedded in substrate
TWI301660B (en) Structure of embedding chip in substrate and method for fabricating the same
TW473962B (en) Cavity down ball grid array package and its manufacturing process
CN102800636B (en) Electronic component package and method for manufacturing the same
TW200828542A (en) Circuit board structure having embedded semiconductor component and fabrication method thereof
TW200913862A (en) Circuit board structure having heat-dissipating structure
CN102610594A (en) Stacked semiconductor assembly with heat sink and build-up circuitry
TWI249796B (en) Semiconductor device having flip chip package
CN113035786A (en) Semiconductor structure and manufacturing method thereof
TWI283050B (en) Substrate structure embedded method with semiconductor chip and the method for making the same
TW200826269A (en) PCB structre having embedded semiconductor chip and fabrication method thereof
TW200908268A (en) Packaging substrate structure with capacitor embedded therein and method for fabricating the same
TW200822336A (en) Stacked type chip package, chip package and process thereof
TW201311073A (en) Semiconductor package structure and its manufacturing method
CN116895636B (en) Package substrate and method for fabricating the same
CN106158785A (en) Heat dissipation type packaging structure and heat dissipation piece thereof
CN103839897B (en) Integrated antenna package and manufacturing method
TWI283462B (en) Bumpless chip package and fabricating process thereof
CN1971894A (en) Chip-embedded modular structure
TW200830975A (en) PCB structure having heat-dissipating member
CN101360393B (en) Circuit board structure with embedded semiconductor chip and manufacturing method thereof
TWI249231B (en) Flip-chip package structure with embedded chip in substrate
TWI237408B (en) Light emitting diode (LED) packaging