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TWI268555B - Silicon wafer and process for producing it - Google Patents

Silicon wafer and process for producing it

Info

Publication number
TWI268555B
TWI268555B TW093123542A TW93123542A TWI268555B TW I268555 B TWI268555 B TW I268555B TW 093123542 A TW093123542 A TW 093123542A TW 93123542 A TW93123542 A TW 93123542A TW I268555 B TWI268555 B TW I268555B
Authority
TW
Taiwan
Prior art keywords
silicon wafer
production
oxygen
silicon
layer
Prior art date
Application number
TW093123542A
Other languages
English (en)
Other versions
TW200507115A (en
Inventor
Christoph Seuring
Robert Hoelzl
Reinhold Wahlich
Ammon Wilfried Von
Original Assignee
Siltronic Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siltronic Ag filed Critical Siltronic Ag
Publication of TW200507115A publication Critical patent/TW200507115A/zh
Application granted granted Critical
Publication of TWI268555B publication Critical patent/TWI268555B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • H01L21/3225—Thermally inducing defects using oxygen present in the silicon body for intrinsic gettering
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T117/00—Single-crystal, oriented-crystal, and epitaxy growth processes; non-coating apparatus therefor
    • Y10T117/10—Apparatus
    • Y10T117/1004—Apparatus with means for measuring, testing, or sensing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T117/00—Single-crystal, oriented-crystal, and epitaxy growth processes; non-coating apparatus therefor
    • Y10T117/10—Apparatus
    • Y10T117/1004—Apparatus with means for measuring, testing, or sensing
    • Y10T117/1008—Apparatus with means for measuring, testing, or sensing with responsive control means
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T117/00—Single-crystal, oriented-crystal, and epitaxy growth processes; non-coating apparatus therefor
    • Y10T117/10—Apparatus
    • Y10T117/1004—Apparatus with means for measuring, testing, or sensing
    • Y10T117/1012—Apparatus with means for measuring, testing, or sensing with a window or port for visual observation or examination

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Recrystallisation Techniques (AREA)
TW093123542A 2003-08-07 2004-08-05 Silicon wafer and process for producing it TWI268555B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE10336271A DE10336271B4 (de) 2003-08-07 2003-08-07 Siliciumscheibe und Verfahren zu deren Herstellung

Publications (2)

Publication Number Publication Date
TW200507115A TW200507115A (en) 2005-02-16
TWI268555B true TWI268555B (en) 2006-12-11

Family

ID=34112006

Family Applications (1)

Application Number Title Priority Date Filing Date
TW093123542A TWI268555B (en) 2003-08-07 2004-08-05 Silicon wafer and process for producing it

Country Status (6)

Country Link
US (2) US7235863B2 (zh)
JP (1) JP5097332B2 (zh)
KR (1) KR100625822B1 (zh)
CN (1) CN100394536C (zh)
DE (1) DE10336271B4 (zh)
TW (1) TWI268555B (zh)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102005013831B4 (de) * 2005-03-24 2008-10-16 Siltronic Ag Siliciumscheibe und Verfahren zur thermischen Behandlung einer Siliciumscheibe
CN100447559C (zh) * 2006-02-17 2008-12-31 无锡乐东微电子有限公司 一种利用Cu诱导硅片表面COP的测试方法
EP1835533B1 (en) * 2006-03-14 2020-06-03 Soitec Method for manufacturing compound material wafers and method for recycling a used donor substrate
DE102007027111B4 (de) 2006-10-04 2011-12-08 Siltronic Ag Siliciumscheibe mit guter intrinsischer Getterfähigkeit und Verfahren zu ihrer Herstellung
JP5654206B2 (ja) * 2008-03-26 2015-01-14 株式会社半導体エネルギー研究所 Ｓｏｉ基板の作製方法及び該ｓｏｉ基板を用いた半導体装置
US7816765B2 (en) * 2008-06-05 2010-10-19 Sumco Corporation Silicon epitaxial wafer and the production method thereof
JP5515406B2 (ja) * 2009-05-15 2014-06-11 株式会社Ｓｕｍｃｏ シリコンウェーハおよびその製造方法
KR101381537B1 (ko) * 2009-06-03 2014-04-04 글로벌웨어퍼스 재팬 가부시키가이샤 실리콘 웨이퍼 및 실리콘 웨이퍼의 열처리 방법
CN110571172A (zh) * 2019-09-06 2019-12-13 大同新成新材料股份有限公司 一种硅晶圆制造方法及制造装置
CN110627031A (zh) * 2019-09-25 2019-12-31 常熟理工学院 一种钼掺杂磷化钴碳珊瑚片复合材料的制备方法

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US4824698A (en) * 1987-12-23 1989-04-25 General Electric Company High temperature annealing to improve SIMOX characteristics
JPH07321120A (ja) * 1994-05-25 1995-12-08 Komatsu Electron Metals Co Ltd シリコンウェーハの熱処理方法
US5994761A (en) * 1997-02-26 1999-11-30 Memc Electronic Materials Spa Ideal oxygen precipitating silicon wafers and oxygen out-diffusion-less process therefor
JP3929557B2 (ja) * 1997-07-30 2007-06-13 三菱電機株式会社 半導体装置およびその製造方法
JP3011178B2 (ja) * 1998-01-06 2000-02-21 住友金属工業株式会社 半導体シリコンウェーハ並びにその製造方法と熱処理装置
WO1999057344A1 (fr) * 1998-05-01 1999-11-11 Nippon Steel Corporation Plaquette de semi-conducteur en silicium et son procede de fabrication
DE19823962A1 (de) * 1998-05-28 1999-12-02 Wacker Siltronic Halbleitermat Verfahren zur Herstellung eines Einkristalls
JP3711199B2 (ja) * 1998-07-07 2005-10-26 信越半導体株式会社 シリコン基板の熱処理方法
JP2000031153A (ja) * 1998-07-13 2000-01-28 Shin Etsu Handotai Co Ltd Ｓｉウエーハ及びその製造方法
JP3800006B2 (ja) * 1998-08-31 2006-07-19 信越半導体株式会社 シリコン単結晶ウエーハの製造方法及びシリコン単結晶ウエーハ
DE69933777T2 (de) * 1998-09-02 2007-09-13 Memc Electronic Materials, Inc. Verfahren zur herstellung von einem silizium wafer mit idealem sauerstoffausfällungsverhalten
JP4038910B2 (ja) * 1999-01-08 2008-01-30 株式会社Ｓｕｍｃｏ 半導体シリコンウェーハの製造方法
DE19905737C2 (de) * 1999-02-11 2000-12-14 Wacker Siltronic Halbleitermat Verfahren zur Herstellung einer Halbleiterscheibe mit verbesserter Ebenheit
JP2000256092A (ja) 1999-03-04 2000-09-19 Shin Etsu Handotai Co Ltd シリコンウエーハ
US6500732B1 (en) * 1999-08-10 2002-12-31 Silicon Genesis Corporation Cleaving process to fabricate multilayered substrates using low implantation doses
EP1212787B1 (en) * 1999-08-10 2014-10-08 Silicon Genesis Corporation A cleaving process to fabricate multilayered substrates using low implantation doses
US6423625B1 (en) * 1999-08-30 2002-07-23 Taiwan Semiconductor Manufacturing Company Ltd. Method of improving the bondability between Au wires and Cu bonding pads
DE19941902A1 (de) 1999-09-02 2001-03-15 Wacker Siltronic Halbleitermat Verfahren zur Herstellung von mit Stickstoff dotierten Halbleiterscheiben
US6423615B1 (en) 1999-09-22 2002-07-23 Intel Corporation Silicon wafers for CMOS and other integrated circuits
JP2002043318A (ja) * 2000-07-28 2002-02-08 Shin Etsu Handotai Co Ltd シリコン単結晶ウエーハの製造方法
JP4304879B2 (ja) * 2001-04-06 2009-07-29 信越半導体株式会社 水素イオンまたは希ガスイオンの注入量の決定方法
DE10131249A1 (de) * 2001-06-28 2002-05-23 Wacker Siltronic Halbleitermat Verfahren zur Herstellung eines Films oder einer Schicht aus halbleitendem Material
JP4147758B2 (ja) * 2001-09-10 2008-09-10 株式会社Ｓｕｍｃｏ ウェーハの製造条件の決定方法
JP4567251B2 (ja) * 2001-09-14 2010-10-20 シルトロニック・ジャパン株式会社 シリコン半導体基板およびその製造方法
WO2003036698A2 (en) * 2001-10-26 2003-05-01 Sige Semiconductor Inc. Method of depositing high-quality sige on sige substrates
DE10205084B4 (de) * 2002-02-07 2008-10-16 Siltronic Ag Verfahren zur thermischen Behandlung einer Siliciumscheibe sowie dadurch hergestellte Siliciumscheibe

Also Published As

Publication number Publication date
TW200507115A (en) 2005-02-16
DE10336271A1 (de) 2005-03-10
KR100625822B1 (ko) 2006-09-20
US20060278157A1 (en) 2006-12-14
US7235863B2 (en) 2007-06-26
CN1581430A (zh) 2005-02-16
US20050032376A1 (en) 2005-02-10
JP5097332B2 (ja) 2012-12-12
JP2005057295A (ja) 2005-03-03
CN100394536C (zh) 2008-06-11
DE10336271B4 (de) 2008-02-07
KR20050015983A (ko) 2005-02-21
US7537657B2 (en) 2009-05-26

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