[go: up one dir, main page]

TWI254396B - Method for manufacturing gold bumps - Google Patents

Method for manufacturing gold bumps Download PDF

Info

Publication number
TWI254396B
TWI254396B TW094107830A TW94107830A TWI254396B TW I254396 B TWI254396 B TW I254396B TW 094107830 A TW094107830 A TW 094107830A TW 94107830 A TW94107830 A TW 94107830A TW I254396 B TWI254396 B TW I254396B
Authority
TW
Taiwan
Prior art keywords
metal
layer
substrate
protective layer
bonding
Prior art date
Application number
TW094107830A
Other languages
Chinese (zh)
Other versions
TW200633093A (en
Inventor
Mei-Jen Liu
Yu-Ting Lai
Kuang-Shin Lee
Ming-Tsung Tung
Original Assignee
United Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by United Microelectronics Corp filed Critical United Microelectronics Corp
Priority to TW094107830A priority Critical patent/TWI254396B/en
Application granted granted Critical
Publication of TWI254396B publication Critical patent/TWI254396B/en
Publication of TW200633093A publication Critical patent/TW200633093A/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A method for manufacturing gold bumps including providing a substrate including a protective layer, which exposes at least a bonding pad, on a surface, covering a photo resist on the surface of the substrate, performing a photolithography process to pattern the photo resist for exposing a portion of the protective layer and the bonding pad, removing a portion of the protective layer, removing the photo resist, and performing a gold bumping process. The present invention makes the thickness of the protective layer coving on the bonding pad smaller than the thickness of the protective layer covering on the substrate.

Description

1254396 九、發明說明: 【發明所屬之技術領域] 本發明係關於一種製造金屬凸塊之方法,尤指一種可 以改善金屬凸塊周緣階梯高度及增加封裝品質的方法。 【先前技術】 _ 隨著攜帶式電子器材的發展,各種輕、薄、短小的封 裝體不斷地被開發出來,覆晶(mp-chip)球閘陣列(ballgrid array,BGA)封裝體就是其中一例。在覆晶bga封裝體中, •晶粒(die)不再是將接合墊金屬(bonding pad)經由打金線 (wire bonding)來連接到封裝基板上,而是反轉過來透過金 屬凸塊(gold bump)或導電聚合物凸塊(c〇n(juctive p〇iymer bump)等等,以連接到封裝基板上,因此覆晶bga封裝體 •可提升電路密度及提昇電氣特性。 覆晶接合屬於面型陣列式(area array)的接合,因此能 應甩於極高密度的構裝。簡單來說,覆晶接合的觀念係先 在晶粒妁接合墊金屬上長成金屬凸塊,然後可利用如異方 性導電膠膜(anisotropic conductive film,ACF)或銀膠等, 將金屬凸塊黏著於封裝基板上,進而完成晶粒與封裝基板 1254396 之接合。這種方式不僅可突破傳統打線技術的數目限制, 適合多腳數元件封裝,而且電性效能也因具有較短的内連 • 線(connection path)而大幅提升。 請參考第1圖,第1圖為習知金屬凸塊20與封裝基板 22接合之示意圖。如第1圖所示,一晶粒1 〇表面包含有 至少一接合墊金屬12、一氧化層14、一氮化石夕μ。其中, Φ 氧化層14與鼠化石夕16係為一保護層18且依序堆疊於晶粒 10表面,並覆蓋於部分接合墊金屬12表面。另外,在晶 粒10上方另具有一金屬凸塊2〇,且其因為保護層18於接 ‘ 合墊金屬12周緣上方具有一階梯高度(step height),因此金 屬凸塊20於形成後,其周緣亦會具有一相對應之階梯高 度。如此一來,當金屬凸塊20與一封裝基板22進行接合 時’便非常容易因為金屬凸塊2〇之周緣所具有之階梯高 •度,而使得部分塗覆於金屬凸塊20與封裝基板22介面間 的異方性導電膠膜24無法確實將金屬凸塊2〇與封裝基板 22接合。 由上述可知’金屬凸塊20周緣之階梯高度如果過大, 會嚴重地影響到封裝的品質,然而若沒有金屬凸塊20周緣 之P白梯门度異方性導電膠膜無法妥善的被聚集於金屬 1254396 凸塊20表面。習知業界通常是利用兩種方法來改善此問 題’第一種方法是將保護層18沉積的厚度變薄,然而此方 法將大幅降低產品的可靠度(reliability)。第二種方法則是 將接合墊金屬12縮小,然而此方法會使得壓合的面積縮小 而導致異方性導電膠膜24不夠均勻。 【發明内容】 有鑑於此,本發明之主要目的即在提供一種製造金屬 凸塊之方法,以解決前述之問題。 為達上述目的,根據本發明之較佳實施例,本發明首 先提供一基底,且基底表面包含有一圖案化保護層暴露出 至少一個接合墊金屬之部分表面,接著形成一光阻層覆蓋 於基底表面,然後利用一光罩進行一黃光製程將光阻層圖 案化,以暴露出部分保護層與接合墊金屬,接著移除部分 保護層,使得覆蓋於接合墊金屬表面之保護層的厚度小於 覆蓋於基底表面之保護層的厚度,最後移除光阻層並利用 光罩進行一金屬凸塊化製程。 由於本發明可以有效改善金屬凸塊周緣之階梯高声, 經由本發明使得金屬凸塊周緣的階梯高度縮小,將更有利 1254396 純高金屬凸塊與料基板之間的接合效果,進而大糾 ,封裝的品質。另外,本發明於製程中,可以不需要〜 額外的光罩,因此亦不需要增加光罩的成本。 曰" 一為了使貴審查委員能更近一步瞭解本發明之特徵及 技術内容,請參閱以下有關本發明之詳細說明與附圖。然 而所附圖式僅供參考與辅助說明用,並非用來對本^明力口 以限制者〇 ’ ^ 口 【實施方式】 請參考第2圖至第7圖,第2圖至第7圖為根據本發 明第一實施例之製造金屬凸塊48的方法示意圖。如第2圖 所示,首先提供一基底30,基底30可為一完成内部元件 兵線路製作之晶圓或完成内部線路佈局之多層印刷電路板 專等。基底30表面包含有至少一接合墊金屬32、一氧化 層34以及一氮化矽36。其中,接合墊金屬32係為鋁 (aluminum)所構成,另外氧化層34與氮化矽36結合係構 成一圖案化保護層38,且保護層38覆蓋於部分接合墊金 屬32表面並暴露出接合墊金屬32之部分表面。氧化層34 與氮化矽36係分別藉由沉積製程同時形成於基底30與接 合墊金屬32表面。本實施例中,氧化層34與氮化矽36所 1254396 構成之保護層38於基底30與接合墊金屬32表面所形成的 厚度約略相同。 如第3圖所示,接著利用旋塗的方法於基底3〇表面塗 覆上一第一光阻層40,並使用一光罩(圖未示),經由曝光 與顯影等黃光製程將第一光阻層40圖案化,以暴露出部分 保護層38表面與接合墊金屬32表面。 隨後如第4圖所示,利用笛 ^ ΛίΛ ^ ^ 〜用弟一光阻層40作為一蝕刻^ 層進行一蝕刻製程,例如:馆紅+丨, t、… 濕蝕刻(wet etch)製程或乾蝕多 (dry etch)製程等,移除部分 保濩層38,如縱向移除部分: 氮化矽36,使得覆蓋於接合 oR ^ r ^ ^ 墊至屬32表面之部分保護層 %的厚度小於覆蓋於基底 又曰 低30表面之保護層38的厚度。, 後移除第一光阻層4〇。 予度^ 如第5圖所示,進杆—1254396 IX. Description of the Invention: [Technical Field of the Invention] The present invention relates to a method of manufacturing a metal bump, and more particularly to a method for improving the step height of a metal bump and increasing the package quality. [Prior Art] _ With the development of portable electronic devices, various light, thin, and short packages have been continuously developed. One example is a mp-chip ball grid array (BGA) package. . In flip-chip bga packages, • the die is no longer connected to the package substrate via wire bonding, but reversed through the metal bumps ( Gold bump or conductive polymer bumps (c〇n (juctive p〇iymer bump), etc., to be connected to the package substrate, so the flip-chip bga package can increase circuit density and improve electrical characteristics. The combination of area arrays can therefore be applied to extremely high-density structures. In simple terms, the concept of flip-chip bonding is to grow into metal bumps on the die-bonding pad metal. The metal bumps are adhered to the package substrate by using an anisotropic conductive film (ACF) or a silver paste, thereby completing the bonding of the die and the package substrate 1254396. This method can not only break through the traditional wire bonding technology. The number limit is suitable for multi-pin component packaging, and the electrical performance is greatly improved by having a short connection path. Please refer to Figure 1, which is a conventional metal bump 20 and Package substrate 22 As shown in Fig. 1, a die 1 〇 surface includes at least one bond pad metal 12, an oxide layer 14, and a nitride μμ. wherein the Φ oxide layer 14 and the mouse fossil eve 16 are one. The protective layer 18 is sequentially stacked on the surface of the die 10 and covers the surface of the partial bonding pad metal 12. In addition, a metal bump 2 is further disposed on the die 10, and the protective layer 18 is bonded to the pad. The metal 12 has a step height above the circumference of the metal 12, so that the metal bump 20 has a corresponding step height after the formation of the metal bump 20. Thus, when the metal bump 20 is bonded to a package substrate 22 At the time, it is very easy that the anisotropic conductive film 24 partially applied between the metal bump 20 and the interface of the package substrate 22 cannot surely protrude the metal due to the step height of the periphery of the metal bump 2〇. The block 2 is bonded to the package substrate 22. It can be seen from the above that if the step height of the periphery of the metal bump 20 is too large, the quality of the package may be seriously affected, but if there is no P-gate degree of the periphery of the metal bump 20 Conductive film without Properly gathered on the surface of the metal 1254396 bump 20. It is common in the industry to use two methods to improve this problem. The first method is to thin the thickness of the protective layer 18 deposition. However, this method will greatly reduce the reliability of the product. The second method is to reduce the bonding pad metal 12, but this method causes the area of the pressing to be reduced to cause the anisotropic conductive film 24 to be insufficiently uniform. [Invention] In view of the above, the present invention The main purpose is to provide a method of manufacturing metal bumps to solve the aforementioned problems. In order to achieve the above object, in accordance with a preferred embodiment of the present invention, the present invention first provides a substrate, and the surface of the substrate includes a patterned protective layer to expose a portion of the surface of the at least one bond pad metal, and then a photoresist layer is formed over the substrate. Surface, then using a mask to perform a yellow light process to pattern the photoresist layer to expose a portion of the protective layer and the bond pad metal, and then removing a portion of the protective layer such that the thickness of the protective layer overlying the metal surface of the bond pad is less than Covering the thickness of the protective layer on the surface of the substrate, finally removing the photoresist layer and performing a metal bumping process using the photomask. Since the invention can effectively improve the stepping sound of the periphery of the metal bump, the step height of the periphery of the metal bump is reduced by the invention, which is more advantageous for the joint effect between the 1254396 pure high metal bump and the material substrate, and thus greatly corrects. The quality of the package. In addition, the present invention does not require an additional mask in the process, and thus does not require an increase in the cost of the mask.为了" In order to enable the reviewing committee to further understand the features and technical contents of the present invention, please refer to the following detailed description of the invention and the accompanying drawings. However, the drawings are for reference and auxiliary explanation only, and are not intended to limit the number of the ports. [Implementation] Please refer to Figures 2 to 7, and Figures 2 to 7 are A schematic diagram of a method of manufacturing metal bumps 48 in accordance with a first embodiment of the present invention. As shown in Fig. 2, a substrate 30 is provided first. The substrate 30 can be a wafer for completing the internal component line or a multilayer printed circuit board for completing the internal wiring layout. The surface of the substrate 30 includes at least one bond pad metal 32, an oxide layer 34, and a tantalum nitride 36. Wherein, the bonding pad metal 32 is made of aluminum, and the oxide layer 34 is combined with the tantalum nitride 36 to form a patterned protective layer 38, and the protective layer 38 covers the surface of the partial bonding pad metal 32 and exposes the bonding. Part of the surface of the pad metal 32. The oxide layer 34 and the tantalum nitride 36 are simultaneously formed on the surface of the substrate 30 and the bonding pad metal 32 by a deposition process, respectively. In the present embodiment, the thickness of the protective layer 38 formed by the oxide layer 34 and the tantalum nitride 36 1254396 is approximately the same as the thickness of the substrate 30 and the surface of the bonding pad metal 32. As shown in FIG. 3, a first photoresist layer 40 is applied to the surface of the substrate 3 by spin coating, and a photomask (not shown) is used, and a yellow light process such as exposure and development is used. A photoresist layer 40 is patterned to expose a portion of the surface of the protective layer 38 and the surface of the bond pad metal 32. Then, as shown in FIG. 4, an etching process is performed by using a photo-resist layer 40 as an etch layer, for example, a red + 丨, t, ... wet etch process or A dry etch process or the like removes a portion of the protective layer 38, such as a longitudinally removed portion: tantalum nitride 36, such that the thickness of the portion of the protective layer covering the surface of the bond 32 is covered by the bond oR ^ r ^ ^ pad Less than the thickness of the protective layer 38 covering the substrate and lowering the surface 30. After removing the first photoresist layer 4〇. To the degree ^ as shown in Figure 5, into the rod -

保護層38與接合塾—凸塊底層金屬⑽M)製卷 層42與-金—金屬層44表:=一鈦鎮合金⑽ 非僅限制於上述之組人 七明之凸塊底層金J 為習知相關技藝者所:知其:可替換以其他材㈣ 30表面塗覆-第二光 此不多加贅述。接著, ^ ^亚利用先前所述之同_ Ϊ254396 然後如第6圖所示,利用第二光阻層4“ 一電鍍製程,以於未被篦仃 44 於禾被弟一先阻層46所覆蓋之金金屬層 ,, 乂成由金(Au)所構成之金屬凸塊48,因此金屬凸 ★係相對應、於接合塾金屬32的位置而設置於其上,接 、第光阻層46。值得注意的是,由於本發明係已先 P刀保護層38,所以金屬凸塊48周緣之階梯高度便 方麵製成之金屬凸塊周緣的階梯高度小,因此更 黑利於提高金屬凸塊48與封裝基板(圖未示)之間的接合效 果。 # 如第7圖所示,依序利用餘刻製程,移除未被金屬凸 逸/斤覆盘之鈦鶴合金金屬層42與金金屬層44,接著再 行—熱回火(thennal anneal)製程。完成本發明第一實施 例之製造金屬凸塊48的方法。 路Γ參考第8圖至第1〇圖,第8圖至第10圖為根據本 _第例之製造金屬凸塊的方法示意圖。本發明第 —實施例與上述第-實施例主要的不同之處是,在本發明 1254396 第二實施例中,移除部分保護層所使用之光罩不同於6屬 凸塊化製程所使用之光罩。此差異是因為本發明移除= 保護層的製程若是於一般晶圓廠被執行,晶圓廠需自行= 備此光罩,然而此光罩僅需較簡單的圖案,不似金屬凸塊 化製程所使用之光罩需對應每一金屬凸塊的位置而製備, 所以費用也較低,相較於其可改善金屬凸塊周緣階梯高度 的效果,是值得投資的。 如第8圖所示,首先提供一基底5〇,基底5〇可為一 完成内部元件與線路製作之晶圓或完成内部線路佈局之多 層印席i電路板等等。基底5〇表面包含有複數個接合塾金屬 52、54及56、—氧化層58以及一氮化矽60。其中,接合 墊金屬52、54及56係為鋁所構成,另外氧化層%與氮化 矽6〇結合係構成一圖案化保護層62,且保護層62覆蓋於 邡刀4 _墊i屬幻、54及56表面形成凸起之保護層62並 暴漆出妾曰藝金屬52、54及56之部分表面。氧化層58與 氮化石夕6〇係分別藉由沉積製程同時形成於基底50與接合 I、 及56表面。本實施例中,氧化層58與氮化 石夕 冓成之保護層62於基底50與接合墊金屬52、54 及56表Φ所形成的厚度約略相同。 12 1254396 接著如第9圖所示’利用旋塗的方法於基底5〇表面塗 覆上一光阻層64,並使用一第一光罩(圖未示),經由曝光 與顯影等黃光製程將光阻層64圖案化,以暴露出部分凸起 之保護層62表面與接合墊金屬52、54及56表面。 如第10圖所示,利用光阻層64作為一蝕刻擔層進行 一蝕刻製程,例如:濕蝕刻製程或乾蝕刻製程等,移除部 分保護層62 ’如縱向移除部分之氮化石夕60,以縮小覆蓋於 接合墊金屬52、54及56表面以及其間之保護層62的厚 度。然後移除光阻層64。接下來的製程除了金屬凸塊化窜 程所使用之第二光罩不同於第一光罩,其餘製程皆與第一 實施例相似,因此在此不多作贅述。 相較於習知技術,本發明可以有效改善金屬凸塊周緣 之階梯高度,經由本發明使得金屬凸塊周緣的階梯高度縮 小,將更有利於提高金屬凸塊與封裝基板之間的接合效 果,進而大幅增加封裝的品質。另外,本發明於製程中, 可以不需要增加額外的光罩,因此亦不需要增加光罩的成 本’或者彻—簡單且低成本之光料行移除部分保護層 的步驟,因此所增加之光罩成本亦不高。 13 1254396 以上所述僅為本發明之較佳實施例,凡依本發明申請 專利範圍所做之均等變化與修飾,皆應屬本發明之涵蓋範 圍0 【圖式簡單說明】 第1圖為習知金屬凸塊與封裝基板接合之示意圖。 第2圖至第7圖為根據本發明第一實施例之製造金屬凸塊 • 的方法示意圖。 第8圖至第10圖為根據本發明第二實施例之製造金屬凸塊 的方法示意圖。The protective layer 38 and the bonding 塾-bump underlayer metal (10)M) are formed into a roll layer 42 and a gold-metal layer 44. Table: = Titanium alloy (10) is not limited to the above-mentioned group of people. The relevant artisans: know it: can be replaced with other materials (four) 30 surface coating - the second light will not be repeated. Next, ^ ^ uses the same as previously described _ Ϊ 254396 and then as shown in Figure 6, using the second photoresist layer 4 "an electroplating process, so as not to be 篦仃 44 The gold metal layer covered is formed into a metal bump 48 made of gold (Au), so that the metal bumps are correspondingly disposed on the bonding metal 32, and the photoresist layer 46 is connected thereto. It should be noted that since the present invention has the P-cut protective layer 38 first, the step height of the periphery of the metal bump 48 is small, and the step height of the periphery of the metal bump is small, so that the metal bump 48 is more black. The bonding effect with the package substrate (not shown) # As shown in Fig. 7, the titanium alloy metal layer 42 and the gold metal which are not covered by the metal embossing/jin are removed in sequence using the residual etching process. Layer 44, followed by a further anneal process. The method of manufacturing metal bumps 48 of the first embodiment of the present invention is completed. The reference is made to Figs. 8 to 1 and Figs. 8 to 10. The figure is a schematic view of a method of manufacturing a metal bump according to the present invention. The first embodiment of the present invention is as described above. - The main difference of the embodiment is that in the second embodiment of the invention 1254396, the mask used to remove a portion of the protective layer is different from the mask used in the 6-gened bumping process. This difference is due to the present invention. If the process of removing = protective layer is performed at a general fab, the fab needs to prepare the reticle by itself. However, the reticle requires only a simple pattern, unlike the reticle used in the metal bumping process. It needs to be prepared corresponding to the position of each metal bump, so the cost is also low, which is worth investing compared to the effect of improving the step height of the periphery of the metal bump. As shown in Fig. 8, first, a substrate 5 is provided.基底, the substrate 5 〇 can be a wafer for completing internal components and lines or a multi-layer printed circuit board for completing internal circuit layout, etc. The surface of the substrate 5 includes a plurality of bonding bismuth metals 52, 54 and 56, The oxide layer 58 and the tantalum nitride 60. The bonding pad metals 52, 54 and 56 are made of aluminum, and the oxide layer % and the tantalum nitride layer 6 are combined to form a patterned protective layer 62, and the protective layer 62 Covered with trowel 4 _ pad i illusion, 54 and 5 6 a convex protective layer 62 is formed on the surface and a part of the surface of the metal 52, 54 and 56 is exposed. The oxide layer 58 and the nitride nitride layer are simultaneously formed on the substrate 50 and the bonding I by a deposition process, respectively. And the surface of the surface 56. In this embodiment, the thickness of the protective layer 62 of the oxide layer 58 and the nitride nitride is approximately the same as the thickness formed by the substrate 50 and the bonding pads 52, 54 and 56. 12 1254396 Next, as shown in FIG. The photoresist layer 64 is coated on the surface of the substrate 5 by a spin coating method, and the photoresist layer 64 is patterned by a yellow light process such as exposure and development using a first mask (not shown). To expose a portion of the surface of the raised protective layer 62 and the pads metal 52, 54 and 56. As shown in FIG. 10, an etching process is performed using the photoresist layer 64 as an etching layer, for example, a wet etching process or a dry etching process, etc., and a portion of the protective layer 62' is removed as a longitudinally removed portion of the nitride. To reduce the thickness of the protective layer 62 covering the surfaces of the bond pad metals 52, 54 and 56 and therebetween. The photoresist layer 64 is then removed. The following process is different from the first embodiment except that the second mask used in the metal bumping process is different from the first mask, and therefore will not be described here. Compared with the prior art, the present invention can effectively improve the step height of the periphery of the metal bump, and the step height of the periphery of the metal bump is reduced by the invention, which is more advantageous for improving the bonding effect between the metal bump and the package substrate. In turn, the quality of the package is greatly increased. In addition, the present invention can eliminate the need to add an additional mask in the process, and therefore does not need to increase the cost of the mask or a simple and low-cost step of removing a portion of the protective layer, thus increasing The cost of the mask is also not high. 13 1254396 The above description is only the preferred embodiment of the present invention, and all the equivalent changes and modifications made by the scope of the present invention should be within the scope of the present invention. 0 [Simple description of the drawing] FIG. A schematic diagram of bonding metal bumps to a package substrate. 2 to 7 are views showing a method of manufacturing a metal bump according to a first embodiment of the present invention. 8 to 10 are schematic views showing a method of manufacturing a metal bump according to a second embodiment of the present invention.

14 1254396 【主要元件符號說明】14 1254396 [Key component symbol description]

10 晶粒 14氧化層 18 保護層 22 封裝基板 30 基底 34 氧化層 38保護層 42 鈦鎢合金金屬層 46 第二光阻層 50 基底 54 接合墊金屬 58 氧化層 62 保護層 12 接合墊金屬 16 氮化矽 20 金屬凸塊 24 異方性導電膠膜 32 接合墊金屬 36 氮化矽 40 第一光阻層 44 金金屬層 48 金屬凸塊 52 接合墊金屬 56 接合墊金屬 60 氮化矽 64 光阻層10 die 14 oxide layer 18 protective layer 22 package substrate 30 substrate 34 oxide layer 38 protective layer 42 titanium tungsten alloy metal layer 46 second photoresist layer 50 substrate 54 bonding pad metal 58 oxide layer 62 protective layer 12 bonding pad metal 16 nitrogen矽20 metal bumps 24 anisotropic conductive film 32 bond pad metal 36 tantalum nitride 40 first photoresist layer 44 gold metal layer 48 metal bump 52 bond pad metal 56 bond pad metal 60 tantalum nitride 64 photoresist Floor

1515

Claims (1)

.1254396 十、申請專利範圍·· h種製造金屬凸塊之方法,該方法包含有下列步驟: 提供一基底,該基底表面包含有至少一個接合墊金 屬以及—圖案化之保護層覆蓋於該基底表面並暴露出該 接合墊金屬之部分表面; 形成一第一光阻層覆蓋於該基底表面; 利用一光罩進行一黃光製程圖案化該第一光阻層,以 暴露出部分之該保護層舆該接合墊金屬; . 移除部分之該保護層,使得覆蓋於該接合塾金屬表面 之該保護層的厚度小於覆蓋於該基絲蚊該㈣層的厚 度; 移除該第一光阻層;以及 利用該光罩進行一金屬凸塊化製程。 2·如專利㈣第丨項所述之方法,其巾該倾層係由一氧 化層與-氮切層所組成’且該氮切層係覆蓋於該氧 化層上方。 3.如2利關第1項所狀方法’在移除部分之該保護層 ,前’其巾該倾層覆蓋於該基絲面之厚度約略等於 該保護層覆蓋於該接合墊金屬表面之厚度。 16 1254396 4.如專利範圍第丨項所述之方法,其中該接合墊金屬係為 鋁(A1)。 .5·如專利範圍第丨項所述之方法,其中移除部分該保護層 的v驟係利用一濕|虫刻製程(wet etch pr〇cess)。 6·如專利範圍第丨項所述之方法,其中該移除部分該保護 _ 層的步驟係利用一乾蝕刻製程(dry etch process)。 7·如專利範圍第1項所述之方法,其中該金屬凸塊化製程 另包含有下列子步驟: 進行一凸塊底層金屬層(un(jer bump metajQurgy,ubm) 製私’以於該基底表面形成一金屬層; 形成一第二光阻層覆蓋於該基底表面; _ 利用該光罩進行-黃光製程,以圖案化該第二光阻層; 利用圖案化之該第二光阻層作遮罩,以於該基底表面 形成至少一個金屬凸塊(g〇ld bump),且該金屬凸塊係相對 應設置於該接合墊金屬之上; 移除該第二光阻層; 移除未被該金屬凸塊所覆蓋之該金屬層;以及 進行一熱回火(thermal anneal)製程。 17 1254396 8·如專利乾圍第7項所述之方法’其中該金屬層係由-鈦 鶴合金(TiW)金屬層與一金(Au)金屬層所組成。 9·如專利範圍第7項所述之方法,其中該金屬凸塊係由金 (Au)所構成。 Φ 種衣&金屬凸塊之方法,該方法包含有下列步驟: 提仏一基底,該基底表面包含有複數個接合墊金屬以 及一圖案化之保護層覆蓋於該基底與該等接合墊金屬表 面’且覆盖於該等接合塾金屬為一凸起之該保護層並暴露 出該等接合墊金屬之部分表面; ' 形成一第一光阻層覆蓋於該基底表面; 利用-第一光罩進行一黃光製程圖案化該第一光阻 鲁層,以暴露出部分該凸起之該保護層與該等接合塾金屬; 移除部分之該保護層,以縮小覆蓋於該等接合塾金屬 表面之該保護層的厚度; 移除該第一光阻層;以及 利用一第二光罩進行一金屬凸塊化製程。 11.如專鄉圍第10項所述之方法,其中該保護層係由一 氧化層與-氮切層所組成,且純切層係覆蓋於該 18 1254396 氧化層上方。 12.如專利範圍第10項所述之方法,其中該接合墊金屬係 I 為在呂。 13. 如專利範圍第10項所述之方法,其中移除部分該保護 層的步驟係利用一濕蝕刻製程。 14. 如專利範圍第10項所述之方法,其中該移除部分該保 護層的步驟係利用一乾蝕刻製程。 15. 如專利範圍第10項所述之方法,其中該金屬凸塊化製 程另包含有下列子步驟: 進行一凸塊底層金屬層製程,以於該基底表面形成一 •金屬層; 形成一第二光阻層覆蓋於該基底表面; 利用該第二光罩進行一黃光製程,以圖案化該第二光 阻層; 利用圖案化之該第二光阻層作遮罩,以於該基底表面 形成複數個金屬凸塊,且該等金屬凸塊係相對應設置於該 等接合墊金屬之上; 19 1254396 移除該第二光阻層; 移除未被該等金屬凸塊所覆蓋之該金屬層;以及 進行一熱回火製程。 16.如專利範圍第15項所述之方法,其中該金屬層係由一 欽嫣合金金屬層與一金金屬層所組成。 • 17.如專利範圍第15項所述之方法,其中該等金屬凸塊係 由金所構成。 十一、圖式: 20.1254396 X. Patent Application Scope · Method for manufacturing metal bumps, the method comprising the steps of: providing a substrate comprising at least one bonding pad metal and a patterned protective layer covering the substrate Forming and exposing a portion of the surface of the bonding pad metal; forming a first photoresist layer overlying the surface of the substrate; patterning the first photoresist layer by a yellow mask using a mask to expose a portion of the protection Laminating the bonding pad metal; removing a portion of the protective layer such that a thickness of the protective layer covering the bonding bead metal surface is less than a thickness covering the (4) layer of the silkworm; removing the first photoresist a layer; and performing a metal bumping process using the photomask. 2. The method according to the item (4), wherein the inclined layer is composed of an oxidized layer and a nitrogen-cut layer, and the nitrogen-cut layer covers the oxidized layer. 3. The method of claim 1, wherein the protective layer of the portion is removed, and the thickness of the front surface of the substrate is approximately equal to the thickness of the protective layer covering the metal surface of the bonding pad. thickness. The method of claim 2, wherein the bond pad metal is aluminum (A1). The method of claim 2, wherein the portion of the protective layer is removed using a wet etch pr〇cess. 6. The method of clause 203, wherein the step of removing a portion of the protective layer utilizes a dry etch process. The method of claim 1, wherein the metal bumping process further comprises the following sub-steps: performing a bump underlying metal layer (un(jer bump metajQurgy, ubm)) Forming a metal layer on the surface; forming a second photoresist layer covering the surface of the substrate; _ performing a yellow-light process using the photomask to pattern the second photoresist layer; using the patterned second photoresist layer Forming a mask to form at least one metal bump on the surface of the substrate, and the metal bump is correspondingly disposed on the bonding pad metal; removing the second photoresist layer; removing The metal layer not covered by the metal bump; and performing a thermal anneal process. 17 1254396 8 · The method of claim 7 wherein the metal layer is made of - titanium crane The alloy (TiW) metal layer is composed of a gold (Au) metal layer. The method of claim 7, wherein the metal bump is composed of gold (Au). Φ seed coating & metal a method of bumping, the method comprising the steps of: lifting a substrate, the method The surface of the substrate comprises a plurality of bonding pad metal and a patterned protective layer covering the substrate and the bonding pad metal surface ′ and covering the bonding bonding metal as a protrusion of the protective layer and exposing the bonding Part of the surface of the metal; forming a first photoresist layer overlying the surface of the substrate; performing a yellow process to pattern the first photoresist layer with a first mask to expose a portion of the bump a protective layer and the bonding metal; removing a portion of the protective layer to reduce a thickness of the protective layer overlying the bonding metal surface; removing the first photoresist layer; and utilizing a second mask 11. A metal bumping process. 11. The method of claim 10, wherein the protective layer is composed of an oxide layer and a nitrogen-cut layer, and the pure layer is covered by the 18 1254396 oxidation. The method of claim 10, wherein the method of claim 10, wherein the bonding pad metal system is the same as in the method of claim 10, wherein the step of removing a portion of the protective layer is Using a wet etch The method of claim 10, wherein the step of removing a portion of the protective layer is performed by a dry etching process. The method of claim 10, wherein the metal bumping The process further includes the following sub-steps: performing a bump underlayer metal layer process to form a metal layer on the surface of the substrate; forming a second photoresist layer overlying the surface of the substrate; using the second mask to perform a yellow a light process to pattern the second photoresist layer; using the patterned second photoresist layer as a mask to form a plurality of metal bumps on the surface of the substrate, and the metal bumps are correspondingly disposed on Above the bond pad metal; 19 1254396 removing the second photoresist layer; removing the metal layer not covered by the metal bumps; and performing a thermal tempering process. The method of claim 15, wherein the metal layer is composed of a metal alloy layer and a gold metal layer. 17. The method of claim 15 wherein the metal bumps are comprised of gold. XI. Schema: 20
TW094107830A 2005-03-15 2005-03-15 Method for manufacturing gold bumps TWI254396B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW094107830A TWI254396B (en) 2005-03-15 2005-03-15 Method for manufacturing gold bumps

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW094107830A TWI254396B (en) 2005-03-15 2005-03-15 Method for manufacturing gold bumps

Publications (2)

Publication Number Publication Date
TWI254396B true TWI254396B (en) 2006-05-01
TW200633093A TW200633093A (en) 2006-09-16

Family

ID=37587300

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094107830A TWI254396B (en) 2005-03-15 2005-03-15 Method for manufacturing gold bumps

Country Status (1)

Country Link
TW (1) TWI254396B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102556945A (en) * 2010-12-13 2012-07-11 台湾积体电路制造股份有限公司 Method for manufacturing microelectronic device and its integrated circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102556945A (en) * 2010-12-13 2012-07-11 台湾积体电路制造股份有限公司 Method for manufacturing microelectronic device and its integrated circuit
CN102556945B (en) * 2010-12-13 2015-01-28 台湾积体电路制造股份有限公司 Method for manufacturing microelectronic device and its integrated circuit

Also Published As

Publication number Publication date
TW200633093A (en) 2006-09-16

Similar Documents

Publication Publication Date Title
TWI305405B (en) Method for forming high reliability bump structure
US6479900B1 (en) Semiconductor device and method of manufacturing the same
CN100385642C (en) Pad redistribution layer and method for fabricating copper pad redistribution layer
TW579559B (en) Semiconductor device manufacturing method and semiconductor device
CN101211798B (en) Solder bump structure and manufacturing method thereof
US7501311B2 (en) Fabrication method of a wafer structure
US20040094841A1 (en) Wiring structure on semiconductor substrate and method of fabricating the same
US6258705B1 (en) Method of forming circuit probing contact points on fine pitch peripheral bond pads on flip chip
TW200828564A (en) Multi-chip package structure and method of forming the same
JP2005175317A (en) Semiconductor device and its manufacturing method
JP5474534B2 (en) Passivation and contact surrounded by polyimide and method of manufacturing the same
JP2005033153A (en) Multilayer fine wiring interposer and manufacturing method thereof
TW200917392A (en) Semiconductor device and method of bump formation
CN100382291C (en) Semiconductor device and method for fabricating the same
JP2006332694A (en) Method for forming metal bumps on semiconductor surface
JP3481899B2 (en) Method for manufacturing semiconductor device
TWI254396B (en) Method for manufacturing gold bumps
TWI423356B (en) Package method for quad flat no-lead package
JP2005109171A (en) Semiconductor device and manufacturing method thereof
CN100367464C (en) Method for manufacturing metal bump
JP3915670B2 (en) Semiconductor device and manufacturing method thereof
JP2003258014A (en) Method for forming metal bump on semiconductor surface
JP3323091B2 (en) Semiconductor integrated circuit device and method of manufacturing the same
TW200812027A (en) Flip-chip attach structure and method
TWI255561B (en) Manufacturing process for chip package without core

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees