JP3323091B2 - Semiconductor integrated circuit device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device and its manufacturing method, capable of reducing the cost of the flip chip connection between a bare chip and a wiring board, and capable of preventing the misconnection between the chip and the wiring board. SOLUTION: A first insulating film 13 is formed on an integrated circuit chip 11 where an I/O pad 12 has been formed, and a first opening 13A is formed above the I/O pad 12. On this first insulating film 13, a conductive layer 14 to be connected electrically with the I/O pad 12 through the first opening 13A, and a barrier metal layer 16 are lamination-formed. The conductive layer 14 and the barrier metal 16 are patterned with the same mask. On the whole surface a second insulating film 15 is formed, and a second opening 15A is formed at a position different from the first opening 13A. And a solder bump 17 or metal pad is formed on the barrier metal layer 16 inside the second opening 15A. And the position of the solder bump 17 or metal pad is regulated by the second opening 15A.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a so-called flip-chip connection type semiconductor integrated circuit device in which a semiconductor integrated circuit device is directly connected to a wiring board by bumps, and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, in order to cope with an increase in the number of I / Os and a tendency of miniaturization of a semiconductor integrated circuit device, an I / O of an integrated circuit chip is required.
A flip-chip mounting method is used in which the / O pad is directly connected to the corresponding pad of the wiring board directly as a bare chip. In the flip chip connection method,
First, solder projections (bumps) are formed on each I / O pad of the bare chip, and the bare chip is placed face down on the wiring board, and each solder bump and each pad of the wiring board are accurately aligned. Then, a chip is temporarily mounted on the wiring board by applying a load. After a while
The solder bump and the pad are directly connected to each other by reflowing the solder by exposing the solder bump to a temperature higher than the melting point of the solder bump. According to this method, the number of I / O pads can be increased, and the pitch between each I / O pad can be reduced. Further, since the connection distance between the integrated circuit chip and the wiring board is reduced, the integrated circuit can operate at high speed in the mounted state.

In adopting the flip-chip connection method, since the pitch of I / O pads of a semiconductor integrated circuit device is fine (150 μm or less), the pads on the wiring board side have the same pitch as the pads of the integrated circuit chip. It must be formed with sufficient accuracy. However, it is difficult to form the pads on the wiring board with high precision, and even if it is possible to produce a wiring board having such high-precision pads, the cost of the wiring board will increase significantly. . Moreover, the risk of short-circuiting between adjacent pads due to the fine pad pitch increases.

In order to address this problem, wiring is added to the upper layer of the integrated circuit chip so that the original I / O of the integrated circuit chip can be reduced.
By connecting the pads to the newly provided I / O pads in a one-to-one manner, the I / O pads for flip-chip connection are located at positions different from the I / O pads of the original integrated circuit chip.
A method of rearranging and providing O pads (solder bumps) has been proposed.

FIG. 17 shows a conventional flip-chip connection type semiconductor integrated circuit device in which I / O pads are rearranged.
FIG. 4 is a cross-sectional view extracting and showing a structure near a pad. I / O pad 2 and passivation film 3 on integrated circuit chip 1
A conductive layer 4, an insulating film 5, a solder ball position defining metal layer (BLM) or a barrier metal layer 6, a solder bump 7, and the like are formed thereon. I / O pad 2
The wiring is one-to-one connected to the solder bump 7 via the conductive layer 4 and the barrier metal layer 6.

However, the flip-chip connection type semiconductor integrated circuit device adopting such a configuration requires a step of separately forming the conductive layer 4, the insulating film 5, the barrier metal layer 6, and the solder bump 7, respectively. There is a problem that the manufacturing cost increases. When the solder bumps 7 are formed by electrolytic plating, the barrier metal layer 6 is formed on the entire surface of the insulating film 5 and used as a plating electrode. The method of removing by etching is often used. At this time, not only the barrier metal layer 6 but also the surface of the solder bump 7 is etched to hinder the connection, or the region of the barrier metal layer 6 below the solder bump 7 is side-etched to connect the solder bump 7 and the barrier metal layer 6. A problem occurs that the reliability of the device decreases.

[0007]

As described above, in the conventional flip-chip connection type semiconductor integrated circuit device and its manufacturing method, the manufacturing cost is increased due to the increase in the number of manufacturing steps, and the barrier exposed outside the lower part of the solder bumps is increased. When the metal layer is etched, there arises a problem that the surface of the solder bump is etched or a barrier metal layer under the solder bump is side-etched, thereby lowering reliability.

The present invention has been made in view of the above circumstances, and an object thereof is to realize flip-chip connection between a bare chip and a wiring board at low cost.
Another object of the present invention is to provide a flip-chip connection type semiconductor integrated circuit device capable of preventing a connection failure between a chip and a wiring board and a method of manufacturing the same.

[0009]

[0010]

[0011]

According to a first aspect of the present invention, there is provided:
The mounted semiconductor integrated circuit device includes an integrated circuit chip, I / O pads formed on the integrated circuit chip, and formed on the integrated circuit chip and the I / O pad, and on the I / O pad. A first insulating film having a first opening, and a conductive layer formed on the first insulating film and electrically connected to the I / O pad through the first opening. A solder ball position defining metal layer or a barrier metal layer formed on the conductive layer and having the same pattern as the conductive layer; and the conductive layer and the solder layer formed on the solder ball position defining metal layer or the barrier metal layer. A second pattern having the same pattern as the ball position defining metal layer or the barrier metal layer and having a second opening at a position different from the first opening on the solder ball position defining metal layer or the barrier metal layer; Comprising a Enmaku, and the second solder bumps or metal pads formed on the solder ball position defined metal layer or a barrier metal layer in the openings,
The position of the solder bump or the metal pad is defined by the second opening.

According to the above configuration, the I / O pads for flip chip connection are rearranged and provided at positions different from the I / O pads of the original integrated circuit chip, so that the connection pad pitch is increased. As a result, it is possible to prevent a short circuit of a bump between adjacent pads and to reduce the cost of the wiring board. Further, since the position of the solder bump or the metal pad is not defined by the solder ball position defining metal layer or the barrier metal but by the second opening formed in the second insulating film, the position can be set with high accuracy.

[0013]

[0014]

A semiconductor device according to a second aspect of the present invention.
A method of manufacturing a body integrated circuit device includes a step of forming an integrated circuit chip, a step of forming an I / O pad on the integrated circuit chip, and a step of forming a first on the integrated circuit chip and on the I / O pad. Forming an insulating film; forming a first opening on the I / O pad in the first insulating film; and forming a conductive layer on the first insulating film and in the opening. A step of forming a solder ball position defining metal layer or a barrier metal layer on the conductive layer, a step of forming a second insulating film on the solder ball position defining metal layer or the barrier metal layer, 2, insulating film,
Patterning the solder ball position defining metal layer or barrier metal layer and the conductive layer using the same mask, and forming a second opening in the second insulating film at a position different from the first opening. Forming and exposing the solder ball position defining metal layer or barrier metal layer; and forming a solder bump or metal pad on the solder ball position defining metal layer or barrier metal layer in the second opening. It is characterized by having.

According to the above manufacturing method, the second insulating film, the solder ball position defining metal layer or barrier metal layer, and the conductive layer are patterned using the same mask.
The cost can be reduced by reducing the number of PEP steps. Also, when etching the solder ball position defining metal layer or the barrier metal layer, no solder bumps or metal pads are formed, so that they are not etched and corroded, and the solder ball position defining metal layer or the barrier metal layer is not etched. The region under the solder bump or the metal pad of the layer is side-etched, so that the reliability of the connection does not decrease.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. FIGS. 1 to 3 are views for explaining a flip-chip connection type semiconductor integrated circuit device according to a first embodiment of the present invention. FIG. 1 is a plan view of a solder bump forming surface side of an integrated circuit chip. FIG. 2 is an enlarged plan view focusing on one solder bump portion, lead-out wiring portion, and I / O pad portion in FIG. 1, and FIG. 3 is a cross-sectional configuration view taken along line 4-4 in FIG. is there.

Various semiconductor elements are formed in the integrated circuit chip 11 shown in FIG. The peripheral solder bumps 17 are connected one-to-one with the I / O pads 12 via lead-out wires 21 formed on the upper layer of the integrated circuit chip 11, and the I / O pads of the original integrated circuit chip 11 are connected. I / O pads (solder bumps 17) for flip-chip connection are rearranged and provided at a different position from that of FIG. In the integrated circuit chip 11 under the solder bumps 17 in the peripheral portion, a circuit susceptible to α rays and α particles, for example, DR
A dynamic circuit such as a logic circuit having an AM memory cell portion and a floating node is provided. The solder bump 17 at the center is connected to a power supply terminal or a power supply line of the internal circuit.
Power supply noise is reduced by supplying power from a plurality of locations via the power supply 7.

Each of the solder bumps, the lead wirings, and the I / O pads are configured as shown in FIGS. The thickness of the integrated circuit chip 11 is 0.8 to 1
An I / O pad 12 made of a μm aluminum (Al) layer, an Al alloy layer, or the like is provided. On the integrated circuit chip 11 and the I / O pad 12, a passivation film 13 having a thickness of 1 to 2 μm formed of a silicon oxide film or a silicon nitride film is formed. An opening 13 </ b> A is formed in a portion corresponding to 12. The wiring 21 is formed on the I / O pad 12 and the passivation film 13. This wiring 21 is made of Al, Al alloy and copper (C
u), a conductive layer 14 having a thickness of 1 to 2 μm formed of a material containing at least one of chromium (Cr), C
u, formed of a material containing at least one of nickel (Ni) and titanium (Ti), for preventing generation of an intermetallic compound due to diffusion, improving adhesion strength, and obtaining a good electrical contact. A barrier metal layer 16 having a thickness of 0.5 to 1 μm is laminated. The conductive layer 1
4 and the barrier metal layer 16 are patterned by an etching process using the same pattern using a single mask,
It has an integral structure. The I / O pad 12 and the solder bump 17 are connected one to one via the wiring 21. An insulating film 15 having a thickness of several μm to 20 μm is formed on the wiring 21 and the passivation film 13. Examples of the material of the insulating film 15 include a silicon oxide film, a silicon nitride film, and a polyimide film. The insulating film 15 is the passivation film 1
3 has an opening 15A at a position different from the opening 13A,
A solder bump 17 having a diameter of about 50 to 100 μm is formed in contact with the barrier metal layer 16 exposed in the opening 15A. The planar position of the solder bump 17 is defined by the opening 15A of the insulating film 15.

According to such a configuration, the I / O pad (the solder bump 1) for flip chip connection is provided at a position different from the I / O pad 12 of the original integrated circuit chip 11.
Since (7) is rearranged and provided, the pitch between the solder bumps 17 can be increased to prevent short-circuiting of the adjacent bumps 17. Further, since the pitch of the pads on the wiring board side may be widened and high precision is not required, the cost of the wiring board can be reduced. Further, the solder bump 17
Since the position is defined by the opening 15A formed in the insulating film 15 instead of defining the position by the solder ball position defining metal layer or the barrier metal layer 16, highly accurate alignment is possible.

In the first embodiment, the case where the barrier metal layer 16 is a single layer has been described as an example. However, as shown in FIG. 4, at least one of Cr, Cu, Ni, and Ti is used. A metal layer 16-2 containing at least one material of platinum (Pt), Au and palladium (Pd) is laminated on a metal layer 16-1 containing one material.
A similar effect can be obtained even with a barrier metal layer having a layer structure. Further, a barrier metal layer having a structure of three or more layers obtained by combining the above materials may be used.

As shown in FIG. 5, a solder ball position defining metal layer (BLM) 2 is used instead of the barrier metal layer 16.
3 may be provided. The solder ball position defining metal layer 2
3 is a metal having high solder wettability, for example, Au or P
d and the like are preferred.

FIG. 6 is a view for explaining a flip-chip connection type semiconductor integrated circuit device according to a second embodiment of the present invention, and shows a metal pad portion, a lead wiring portion and an I / O pad portion. ing. The difference from the semiconductor integrated circuit device shown in FIG. 3 is that a metal pad 18 having a thickness of 10 to 20 μm formed by electrolytic plating is provided as an I / O pad for flip chip connection instead of the solder bump 17. Au, Ni is used as the metal pad 18.
And Cu can be adopted.

As described above, even if the metal pad 18 is provided instead of the solder bump 17, the same operation and effect as those of the first embodiment can be obtained. In the case where a metal pad 18 is provided instead of the solder bump 17, FIG.
As shown in FIG. 3, the barrier metal layer is formed of two metal layers 16-1,
16-2 (three or more layers may be used).
Of course, a metal pad position defining metal layer 23 'may be provided instead of the barrier metal layer as shown in FIG.

FIGS. 9A to 9C sequentially show the manufacturing steps of the flip-chip connection type semiconductor integrated circuit device shown in FIGS. 3 and 6, respectively. First, after various semiconductor elements and circuits (not shown) are formed in the integrated circuit chip 11 by a known manufacturing process, the I / O pads 12 are formed on the integrated circuit chip 11. Next, a passivation film 13 is formed on the integrated circuit chip 11 and the I / O pad 12 by a CVD method or the like, and a portion of the passivation film 13 corresponding to the I / O pad 12 is selectively wet-etched. Thus, the surface of the I / O pad 12 is exposed by forming the opening 13A.
Subsequently, a conductive layer 14 and a barrier metal layer 16 are sequentially formed on the I / O pad 12 and the passivation film 13 (FIG. 9A).

Thereafter, a photoresist 19 is applied on the barrier metal layer 16, and is exposed and developed to form a pattern of the photoresist 19. Using the photoresist 19 as a mask, the barrier metal layer 16 and the conductive layer 14 are used.
Of the integrated circuit chip 11 by etching
The wiring 21 for connecting the / O pad 12 and the solder bump 17 one-to-one is formed (FIG. 9B).

Next, the photoresist 19 is removed,
An insulating film 15 is formed on the entire surface of the wiring 21 and the passivation film 13 by using, for example, a CVD method. Then, in order to relocate and provide the I / O pads for flip chip connection, a photoresist 20 is applied on the insulating film 15 and exposed and developed to form a pattern of the photoresist 20. The insulating film 15 is wet-etched using the photoresist 20 as a mask, so that an opening 15A is formed at a position different from the opening 13A formed in the passivation film 13, and the surface of the barrier metal layer 16 is exposed. (FIG. 9 (c)).

After the photoresist 20 is removed, a solder bump 17 is formed on the exposed surface of the barrier metal layer 16 by a technique such as electrolytic plating and reflow, a solder ball transfer method or a screen printing method, as shown in FIG. The structure as shown can be formed.

On the other hand, on the exposed surface of the barrier metal layer 16,
When a metal pad 18 as an I / O pad for flip chip connection is formed by electrolytic plating, a structure as shown in FIG. 6 is obtained.

In the manufacturing method as described above, the barrier metal layer 16 and the conductive layer 14 can be patterned by the same pattern using a single mask.
The PEP process can be reduced from three times to two times as compared with the case where the configuration shown in FIG. 17 is manufactured, and the cost can be reduced. Moreover, since the solder bumps 17 and the metal pads 18 are not formed when the barrier metal layer 16 is etched, the solder bumps 17 and the metal pads 18 are etched and corroded, or the barrier metal under the solder bumps 17 or the metal pads 18 is not formed. The layer 16 is not side-etched to reduce the connection reliability.

When the structure shown in FIG. 4 or FIG. 7 is formed, the steps shown in FIG.
After forming the first-layer barrier metal layer 16-1, a second-layer barrier metal layer may be formed on the barrier metal layer 16-1. The subsequent steps are shown in FIG.
Substantially the same as (c). If the solder bump 17 is formed after the step of FIG. 9C, the structure shown in FIG. 4 is obtained, and if the metal pad 18 is formed, the structure shown in FIG. 7 is obtained. When the structure shown in FIG. 5 or FIG. 8 is formed, in the step shown in FIG.
In place of the barrier metal layer 16, a solder ball position defining metal layer (BLM) 23 or a metal pad position defining metal layer 23
'May be formed. The subsequent manufacturing steps are shown in FIG.
Same as (c). If the solder bumps 17 are formed after the step of FIG. 9C, the structure shown in FIG. 5 is obtained, and if the metal pads 18 are formed, the structure shown in FIG. 8 is obtained.

FIG. 10 is a view for explaining a flip-chip connection type semiconductor integrated circuit device according to a third embodiment of the present invention, and shows a solder bump portion, a lead-out wiring portion, and an I / O pad portion. I have. I / O pads 12 are formed on the integrated circuit chip 11. On the integrated circuit chip 11 and the I / O pad 12,
A passivation film 13 having an opening 13A is formed on a portion corresponding to the I / O pad 12. I above
On the / O pad 12 and the passivation film 13, a lead-out wiring part 21 'is formed. The wiring portion 21 ′ is formed by laminating the conductive layer 14, the barrier metal layer 16 and the insulating film 15 in this order. It is patterned to form an integral structure. The I / O pads 12 of the integrated circuit chip 11 and the solder bumps 17 are connected and connected one-to-one by the wiring part 21 ′.

Even with such a configuration, the first and second
Substantially the same functions and effects as those of the embodiment are obtained. Further, as shown in FIG. 4, the barrier metal layer may have a structure of two or more layers, or as shown in FIG. 5, a solder ball position defining metal layer (BLM) 23 may be provided instead of the barrier metal layer.

FIG. 11 is a view for explaining a flip-chip connection type semiconductor integrated circuit device according to a fourth embodiment of the present invention, and shows a metal pad portion, a lead wiring portion and an I / O pad portion. ing. The fourth embodiment is different from the third embodiment in that the solder bump 1
7, a metal pad 18 is provided. Other configurations are the same as those of the third embodiment shown in FIG.
Therefore, even with such a configuration, the above-described first to third embodiments
Substantially the same functions and effects as those of the embodiment are obtained. Further, as shown in FIG. 7, the barrier metal layer may have a structure of two or more layers, or as shown in FIG. 8, a metal pad position defining metal layer 23 'may be provided instead of the barrier metal layer.

FIGS. 12A to 12D are views for explaining the method of manufacturing the flip-chip connection type semiconductor integrated circuit device shown in FIG. 11, and show the manufacturing steps sequentially. First, after various semiconductor elements and circuits (not shown) are formed in the integrated circuit chip 11 by a well-known manufacturing process, I / O
The pad 12 is formed. The integrated circuit chips 11 and I
A passivation film 13 is formed on the / O pad 12 by a CVD method or the like, and an opening 13A is formed in a portion corresponding to the I / O pad 12. Next, the I / O pad 12
Then, a conductive layer 14, a barrier metal layer 16, and an insulating film 15 are sequentially formed on the passivation film 13 (FIG. 12A).

In order to relocate and provide I / O pads for flip chip connection, a photoresist 2 is formed by PEP.
0 is formed, the insulating film 15 is etched using the photoresist 20 as a mask, and the position of the metal pad for flip chip connection is defined at a position different from the opening 13A formed in the passivation film 13. The opening 15A is formed (FIG. 12B).

Thereafter, the photoresist 20 is removed, and a metal pad 18 is formed by electrolytic plating.
(C)). At this time, the conductive layer 14 and the barrier metal layer 16 are formed on the entire surface of the integrated circuit chip 11, and a laminated structure of the conductive layer 14 and the barrier metal layer 16 can be used for the electrode for electrolytic plating. Can be performed stably.

Subsequently, a photoresist 2 made of PEP
2 and etching using the photoresist 22 as a mask, the I / O of the integrated circuit chip 11 is reduced.
A wiring portion 21 'for forming a one-to-one connection between the pad 12 and the metal pad 18 is formed (FIG. 12D). Then, the structure shown in FIG. 11 is obtained by removing the photoresist 22.

In the step shown in FIG. 12C, if the solder bumps 17 are formed by electrolytic plating and reflow, solder ball transfer, or a screen printing method instead of the metal pads 18 for flip chip connection. The structure shown in FIG. 10 can be formed.

According to such a manufacturing method, since the number of PEP steps can be reduced from three times to two times in the conventional method, the steps are shorter than in the conventional manufacturing method, and the cost can be reduced.
Further, when the barrier metal layer 16 is etched, the solder bumps 17 or the metal pads 18 are etched and corroded.
There is no possibility that the lower portion of the barrier metal layer 8 is side-etched to lower the reliability. Furthermore, solder bump 17
Instead of defining the position with a solder ball position defining metal layer or a barrier metal layer as in the prior art, an insulating film 15 is used.
Since the position is defined by the opening 15A formed in the above, highly accurate positioning is possible.

Note that, in the configuration shown in FIG.
Similarly to the above, the barrier metal layer may be formed with two or more layers, and the solder ball position defining metal layer 23 may be provided instead of the barrier metal layer as shown in FIG. Similarly, in the configuration shown in FIG. 11, two or more barrier metal layers may be formed as in FIG.
As shown in FIG. 8, a metal pad position defining metal layer 23 'may be provided instead of the barrier metal layer.

FIGS. 13 to 16 each illustrate a flip-chip connection type semiconductor integrated circuit device according to a fifth embodiment of the present invention. FIG. 13 shows that the α-particles and α-rays in the solder bumps 17 are formed on the barrier metal layer 16 in FIG.
In this embodiment, a barrier metal layer 24 is provided for blocking the semiconductor element from reaching the inside. FIG.
Is provided with a barrier metal layer 24 for blocking α particles and α rays in the solder bumps 17 from reaching the semiconductor elements in the integrated circuit chip 11. FIG. 15 shows a configuration in which the barrier metal layer 24 in FIG. 13 is interposed between the conductive layer 14 and the barrier metal layer 16. Similarly, FIG. 16 shows a configuration in which the barrier metal layer 24 in FIG. 14 is interposed between the conductive layer 14 and the barrier metal layer 16.

The barrier metal layer 24 is preferably made of a heavy metal, for example, Au or Pt. According to such a configuration, the solder bump 1 is formed by the barrier metal layer 24.
7 can be prevented from reaching the semiconductor element in the integrated circuit chip 11, so that the .alpha.-rays and .alpha. Circuits, such as DRAM memory cell sections,
In addition, by providing a dynamic circuit such as a logic circuit having a floating node, the influence of α-rays and α-particles by the solder bumps 17 can be suppressed.

It should be noted that which of the structures shown in FIGS. 13 and 14 and the structures shown in FIGS.
The material may be selected in consideration of the materials of the barrier metal layers 16 and 24, the solder wettability of these materials, the adhesive strength to solder bumps, the electrical contact characteristics, and the like.

[0045]

As described above, according to the present invention, the flip-chip connection between the bare chip and the wiring board can be realized at low cost and the connection failure between the chip and the wiring board can be prevented. A semiconductor integrated circuit device and a method for manufacturing the same are obtained.

[Brief description of the drawings]

FIG. 1 is a plan view of a flip-chip connection type semiconductor integrated circuit device according to a first embodiment of the present invention, which is on a solder bump forming surface side of an integrated circuit chip.

FIG. 2 is an enlarged plan view showing one solder bump portion, a lead-out wiring portion, and an I / O pad portion in FIG. 1;

FIG. 3 is a sectional view taken along line 4-4 in FIG. 2;

FIG. 4 is a sectional view showing another configuration example along the line 4-4 in FIG. 2;

FIG. 5 is a sectional view showing still another configuration example along line 4-4 in FIG. 2;

FIG. 6 is a cross-sectional view of a flip-chip connection type semiconductor integrated circuit device according to a second embodiment of the present invention, showing a metal pad portion, a lead-out wiring portion, and an I / O pad portion.

FIG. 7 is a cross-sectional view showing another configuration example of FIG. 6;

FIG. 8 is a sectional view showing still another configuration example of FIG. 6;

FIG. 9 is a sectional view sequentially showing the manufacturing process of the flip-chip connection type semiconductor integrated circuit device shown in FIGS. 3 and 6;

FIG. 10 is a view for explaining a flip-chip connection type semiconductor integrated circuit device according to a third embodiment of the present invention.
Sectional drawing which shows an O pad part.

FIG. 11 is a view for explaining a flip-chip connection type semiconductor integrated circuit device according to a fourth embodiment of the present invention.
Sectional drawing which shows a pad part.

FIG. 12 is a cross-sectional view for explaining the manufacturing method of the flip-chip connection type semiconductor integrated circuit device shown in FIG. 11 and sequentially showing manufacturing steps;

FIG. 13 is a view for explaining a flip-chip connection type semiconductor integrated circuit device according to a fifth embodiment of the present invention.
Sectional drawing which shows the structural example of an O pad part.

FIG. 14 is for describing a flip-chip connection type semiconductor integrated circuit device according to a fifth embodiment of the present invention.
Sectional drawing which shows the other structural example of an O pad part.

FIG. 15 is for describing a flip-chip connection type semiconductor integrated circuit device according to a fifth embodiment of the present invention, and includes a solder bump portion, a lead-out wiring portion, and an I / O device.
Sectional drawing which shows the other example of a structure of an O pad part.

FIG. 16 is for describing a flip-chip connection type semiconductor integrated circuit device according to a fifth embodiment of the present invention, and includes a solder bump portion, a lead-out wiring portion, and an I / O device.
Sectional drawing which shows another example of a structure of the O pad part.

FIG. 17 is a cross-sectional view for explaining a conventional flip-chip connection type semiconductor integrated circuit device and a method of manufacturing the same, extracting and showing a structure near an I / O pad.

[Explanation of symbols]

11 integrated circuit chip, 12 I / O pad, 13 passivation film (first insulating film), 13A first opening, 14 conductive layer, 15 insulating film (second insulating film),
15A: second opening, 16: barrier metal layer, 16-
1, 16-2: metal layer, 17: solder bump, 18: metal pad, 19, 20, 22: photoresist, 21:
Wiring, 21 ': Wiring portion, 23: Solder ball position defining metal layer, 23': Metal pad position defining metal layer, 24: Barrier metal layer.

──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Hiroshi Tazawa 1 Toshiba-cho, Komukai, Koyuki-ku, Kawasaki-shi, Kanagawa Prefecture (72) Inventor Kazuhide Doi Toshiba Komukai, Kochi-ku, Kawasaki-shi, Kanagawa No. 1, Toshiba R & D Center Co., Ltd. (72) Inventor Naohiko Hirano No. 1, Komukai Toshiba Town, Yuki-ku, Kawasaki-shi, Kanagawa Prefecture Toshiba R & D Center Co., Ltd. No. 1 Toshiba-cho, Toshiba R & D Center Co., Ltd. (72) Inventor Eiichi Hosomi No. 1, Komukai Toshiba-cho, Yuki-ku, Kawasaki-shi, Kanagawa Pref. Toshiba R & D Center Co., Ltd. 25-1, Ekimae Honmachi, Kawasaki-ku Toshiba Microelectronics Corporation In-house (56) References JP-A-8-124930 JP, A) JP flat 4-278542 (JP, A) JP flat 8-250498 (JP, A) (58 ) investigated the field (Int.Cl. ^7, DB name) H01L 21/60

Claims (2)

(57) [Claims] 1. An integrated circuit chip, an I / O pad formed on the integrated circuit chip, and a first I / O pad formed on the integrated circuit chip and on the I / O pad. A first insulating film having an opening, and a first insulating film formed on the first insulating film and having the I through the first opening.
A conductive layer electrically connected to the / O pad; a solder ball position defining metal layer or a barrier metal layer formed on the conductive layer and having the same pattern as the conductive layer; It is formed on the barrier metal layer, has the same pattern as the conductive layer and the solder ball position defining metal layer or the barrier metal layer, and is different from the first opening on the solder ball position defining metal layer or the barrier metal layer. Second with a second opening in position
And a solder bump or a metal pad formed on the solder ball position defining metal layer or the barrier metal layer in the second opening, and the position of the solder bump or the metal pad is changed to the second opening. A semiconductor integrated circuit device defined by a section. 2. A process for forming an integrated circuit chip, a process for forming an I / O pad on the integrated circuit chip, and forming a first insulating film on the integrated circuit chip and on the I / O pad. Forming a first opening on the I / O pad in the first insulating film; forming a conductive layer on the first insulating film and in the opening; A step of forming a solder ball position defining metal layer or a barrier metal layer on the conductive layer, a step of forming a second insulating film on the solder ball position defining metal layer or the barrier metal layer, and a step of forming the second insulating film Patterning the solder ball position defining metal layer or the barrier metal layer and the conductive layer using the same mask, and forming a second insulating film at a position different from the first opening in the second insulating film.
Forming an opening of the solder ball position defining metal layer or barrier metal layer, and forming a solder bump or metal pad on the solder ball position defining metal layer or barrier metal layer in the second opening. And a method of manufacturing a semiconductor integrated circuit device.