TWI247158B - Liquid crystal display device and its manufacturing method - Google Patents

Abstract

To solve such a problem that in the conventional manufacturing method wherein the number of manufacturing steps is reduced, when a channel length is shortened, a manufacturing margin is small and a yield is lowered. A four sheet mask process and a three sheet mask process of TN type and IPS type liquid crystal display devices are constructed by combining technologies of a novel technology which first forms an etch stop layer and then rationalizes a scanning line forming step and a contact forming step by introducing a halftone exposure technology, a new technology which rationalizes a step for forming a protective layer of an electrode terminal by introducing a halftone exposure technology to an anodization step of a source/drain wiring which is a well-known technology, and a rationalization technology simultaneously forming a pixel electrode and a scanning line which is a well-known technology.

Description

1247158 (1) Mei, invention description [Technical Field] The present invention relates to a liquid crystal display device having a color image display function, and more particularly to an active liquid crystal display device. [Prior Art] With the advancement of meticulous processing technology, liquid crystal material technology and high-density mounting technology in recent years, liquid crystal display devices of 5 to 5 Ocm diagonal, television images or various image display systems are numerous due to commercial basis. provide. Further, by completing one of the two glass substrates of the liquid crystal substrate, the color display layer of RGB is formed in advance, so that the color display can be easily realized. In particular, the built-in switching element is provided on the so-called active type liquid crystal substrate of each pixel, and the contrast image having a small crosstalk level and a fast response speed is ensured. Such a liquid crystal display device (liquid crystal substrate) is generally formed by a matrix of 200 to 1 200 scanning lines and a matrix of signal lines of 300 to 1 600 degrees, but recently, an increase corresponding to the display capacity is simultaneously performed. Large screen and fine-tuned. FIG. 23 is a view showing a semiconductor integrated body to which a driving signal is supplied by forming a transparent insulating substrate on one side of the liquid crystal substrate 1 and forming an electrode terminal group 5 of a scanning line on the glass substrate 2, for example, in a state in which the liquid crystal substrate is mounted. The circuit chip 3 is connected by a COG (Chip_On-G1 as s) method using a conductive adhesive, or a copper-plated or solder-plated copper foil terminal (for example, based on a polyimide film). The TCP film 4 shown in the figure is a so-called TCP ( Tape-Carriei*·Package) method in which the electrode terminal group 6 of the signal line is pressed and fixed by a suitable adhesive containing a conductive medium to -4-(2) 1247158. An electrical signal is supplied to the image display unit, such as the mounting means. For convenience, both installation methods are illustrated, but in practice, any method can be appropriately selected. The pixel connecting the image display portion of the liquid crystal substrate 1 located at the center of the approximate center and the electrode terminals 5 and 6 of the scanning line and the signal line are 7 and 8, and are not necessarily the same as the electrode terminal groups 5 and 6. The conductive material is composed of. 9 is a counter-glass substrate or a color filter layer of another transparent insulating substrate having a counter electrode having a transparent conductivity common to all liquid crystal cells on the opposite surface. Fig. 24 is a view showing an equivalent circuit diagram of an active type liquid crystal display device in which an insulating gate type transistor 1 is disposed on each pixel as a switching element, and 1 1 (system 7 in Fig. 23) is a scanning line, 12 (in In Fig. 23, the system 8) is a signal line '1' is a liquid crystal cell, and the liquid crystal cell 13 is treated as a capacitor element electrically. The components depicted by the solid line are formed on the glass substrate 2 constituting one of the liquid crystal substrates, and the liquid crystal cells 13 are all shown by broken lines, and the common counter electrode 14 is formed in the opposite direction. The main surface of one of the glass substrates 9. In the case where the OFF resistance of the insulated gate type transistor 1 or the resistance of the liquid crystal cell 丨3 is low or the gray scale of the image is emphasized, it is used as a liquid crystal cell 13 for expansion. The time constant of the auxiliary storage capacitor 15 is applied to a circuit method such as the parallel liquid crystal cell 13. Further, 16 is a common bus of the storage capacitor 15. Η 25 is a key section of the liquid crystal display device image display unit -5-(3) 1247158, and two glass substrates 2, 9 which constitute the liquid crystal substrate 1, are formed of resinous fibers, beads or formed thereon. A spacer (not shown) such as a columnar spacer on the color filter layer 9 is formed at a specific distance of about μηι, and the gap is formed around the periphery of the glass substrate 9 to be organic. The sealing material and the sealing material (both not shown) formed of the resin are sealed in a sealed space, and the liquid crystal 17 is filled in the sealed space. In order to realize the color display, the dye is covered by the so-called colored layer 18 contained on the sealed space side of the glass substrate 9, or an organic film having a thickness of 1 to 2 μm of either or both of the pigments. In the case of the color display function, the glass substrate 9 is nicknamed a color filter layer (color filter, abbreviated as CF). Further, the polarizing plate 19 is attached to either the upper surface of the glass substrate 9 or the lower surface of the glass substrate 2 by the nature of the liquid crystal material 17, and the liquid crystal substrate 1 is functionalized by an electro-optical element. Now, on most liquid crystal substrates sold in the market, TN (Twisted and Phased) liquid crystals are used for the liquid crystal material, and the polarizing plate 19 usually requires two sheets. Although not shown, a back light source is disposed as a light source on a transmissive liquid crystal substrate, and white light is irradiated from below. The liquid crystal 17 is connected to the two glass substrates 2, 9, and the polyimine-based resin film 20 having a thickness of about 0.1 μm is an alignment film which is oriented in the direction of the liquid crystal molecules. 2 1 is a drain electrode (wiring) connecting the drain of the insulating gate type electric crystal 1 and the transparent conductive pixel 22, and is formed at the same time as the signal line (source line) 12. The semiconductor layer 23 is located between the signal line 12 and the drain electrode 2 1 and is described in detail later in -6 - (4) 1247158. The Cr thin film layer 24 formed on the color filter layer 9 so as to have a thickness of about 0.1 μm adjacent to the boundary of the colored layer 18 is attached to the semiconductor layer 23 and the scanning line 11 and the signal line 12 to prevent external light from entering. Shading member, this shaping technique is called Black Matrix (abbreviated as BM). Here, a description will be given of a configuration and a manufacturing method of an insulating gate type transistor as a switching element. There are two types of insulating gate type transistors which are currently used, one of which is called an etch-off type, which is introduced as a conventional example. With the introduction of dry etching technology, the mask that required 8 passes was now reduced to 5 channels and helped to significantly reduce the cost of the process. Fig. 26 is a plan view showing a unit pixel of an active substrate (semiconductor device for a display device) constituting a conventional liquid crystal substrate, and Fig. 27 shows A-A', B-B' and C-C' of Fig. 26(e). A cross-sectional view of the line, and a brief description of its manufacturing process. First, as shown in Fig. 26 (a) and Fig. 27 (a), heat resistance, chemical resistance and transparency are used as a highly insulating substrate, and a glass substrate 2 having a thickness of about 0.5 to 1.1 mm is used, for example, Corning Incorporated. On the main surface of one of the trade names 1737, a vacuum film forming apparatus such as SPT (sputtering) is used to cover the first metal layer having a thickness of 0.1 to 0.3 μm, and selective formation is also carried out by meticulous processing technology. It also serves as the scan line 1 1 of the gate electrode 1 1 和 and the storage capacitor line 16 . The material of the scanning line is selected in consideration of heat resistance and chemical resistance, and resistance to fluorine acidity and conductivity. However, generally, a heat-resistant metal or alloy such as cr, Ta or MoW alloy is used. In order to reduce the resistance of the scanning line in accordance with the large screen or high definition of the liquid crystal substrate, although it is reasonable to use A1 (aluminum) as the material of the scanning line (5) 1247158, A1 is The heat resistance is low. In the general technique, a metal ruthenium compound of the above-mentioned heat resistant metal such as Cr, Ta, or Mo is added, or an oxide layer (A 1 2 0 3 ) is added to the surface of the A1. That is, the scanning line 11 is composed of a single layer. Next, a PCVD (CVD) device is used in the entire glass substrate 2 to form a first SiNx (nitriding nitride) which is a gate insulating layer, and a first amorphous germanium which is an insulating gate type transistor which contains almost no impurity. The film layers of three types, such as the (a-Si) layer 31 and the second SiNx layer 32 of the insulating layer of the protection channel, are covered by a film thickness of 〇〇.〇5 μιη, 0·1 μηη, respectively. 20 (fc 27(b) shows that the second SiNx layer of the gate electrode 1 1 is selectively finer than the gate electrode 11A by the fine processing technique, and the first amorphous germanium layer 31 serves as the channel protective layer 32D. Secondly, after using the same PC VD device, the second amorphous germanium layer 33 containing, for example, ruthenium, is covered with a degree of, for example, 0.05 μm, as shown in Fig. 26 (c) and Fig. 27 (c). For the vacuum film forming apparatus, a heat-resistant metal 34 such as Ti, Cr, Mo or the like is used as a heat-resistant metal layer having a thickness of about 0.1 μm, and a film layer 35 having a film thickness of 0 deg 1 is used as a low-resistance wiring layer, and then covered with Ti. 36. As an intermediate conductive layer with a film thickness of about 0.1 μm, by selective techniques, the source is selectively formed. The laminate of these 34 3 Α, 35 Α and 36 配线 wirings produces the insulated gate-type electric 电极 electrode 2 1 and the source electrode, which also serves as the signal line 12 and is now used for layer oxidation. The channel of the plasma/political layer is formed by .3 μ m ' > ) and the film thickness of the impure film is exposed on the graph A. The signal line of the processed thin film crystal is treated with the SPT film layer 3 μιη film layer 3- (6) ) 1247158 1 2. The selective pattern formation is performed by using a photosensitive resin pattern formed on the source/drain wiring as a mask, and after etching the Ti film layer 3, the A1 film layer 35, and the Ti film layer 34, the source is removed. The second amorphous germanium layer 33 between the pole and the drain electrode 12, 21 exposes the second SiNx layer 32D, and in other fields, the first amorphous germanium layer 3 1 is removed to expose the gate insulating layer. 30 formed. Since the second SiNx layer 3 2D of the channel protective layer is thus formed, since the etching of the second amorphous germanium layer 33 is automatically completed, the method is called an etch-off method. The source gate electrode 12, 21 and the etch stop layer 32-portion (several μπι) are planarly overlapped so that the insulating gate type transistor does not have a variation. This overlap is an electrical function as a parasitic capacitance, so the smaller the better, but the precision of the exposure machine and the precision of the mask, the expansion factor of the glass substrate, and the glass substrate during exposure are determined, and the practicality is The number is up to 2 μπι. After the removal of the photosensitive resin pattern, the first SiNx layer 32D having a film thickness of about 3 μm is covered by a PCVD apparatus having the same transparency as the gate insulating layer as the transparent insulating layer. As a passivation insulating layer 3 7, as shown in FIG. 26(d) and FIG. 27(d), the passivation insulating layer 37 is selectively removed by a fine processing technique, and is opened on the drain electrode 2 1 The portion 63 and the region outside the image display portion and the position at which the scanning electrode 11 electrode terminal 5 is formed are formed at the position where the opening portion 63 and the electrode terminal 6 of the signal line 12 are formed, and the opening portion 64 is formed. A portion of the drain electrode 2 1 and the scanning line 11 and the signal line 12 is exposed. An opening (7) 1247158 portion 65 is formed on the storage capacitor line 16 (parallelly integrated into the electrode pattern) to expose a portion of the storage capacitor line 16. Finally, a vacuum film forming apparatus such as SPT is used as a transparent conductive layer having a thickness of 0.1 to 0.2 μm, such as ITO (Indium-Tin-Oxide) or IZO (Indium-Zinc-Oxide), as shown in Fig. 26 (e). And as shown in FIG. 27(e), the opening portion 62 is included by the detailed processing technique, and the pixel electrode 22 is selectively formed on the passivation insulating layer 37 to complete the active substrate 2. A part of the scanning line 11 exposed in the opening 63 may be used as the electrode terminal 5, and a part of the signal line 12 exposed in the opening 64 may be used as the electrode terminal 6, as shown in the figure, including the openings 63, 64. On the passivation insulating layer 37, the electrode terminals 5A, 6A formed of IT0 may be selectively formed, but generally, a short conductive line 40 connecting the transparent terminals between the electrode terminals 5A, 6A is formed at the same time. The reason for this is that the electric poles 5A and 6A (not shown) and the short-line 40 are formed in a stripe shape, and the electric resistance can be improved and the high electric resistance for countermeasures against static electricity can be obtained. The same opening portion 65 is included to form an electrode terminal to the storage capacitor line 16. When the wiring resistance of the signal line 12 is not a problem, it is not necessary to form the low-resistance wiring layer 35' by A1. In some cases, if a heat-resistant metal material such as Cr, Ta, Mo or the like is selected, the source can be single-layered. The bungee wiring is 1 2, 2 1 and simplified. Such a source/drain wiring is attached to the heat resistant metal layer, and it is important to ensure the connection between the second amorphous layer and the electrical connection. Further, the heat resistance of the insulated gate type transistor is described in detail in Japanese Laid-Open Patent Publication No. 7-7749. Further, in Fig. 27(c), the storage capacitor line 16 and the drain electrode 2 1 are formed by the gate insulating layer 30 overlap field 5 〇 (lower right oblique line portion), and the detailed description thereof will be omitted. -10- (8) 1247158 [Patent Document] Japanese Laid-Open Patent Publication No. Hei 7-743-68, omitting the details of the five-mask process described above, but the rationalization of the semiconductor layer islanding project and the contact formation process can be deleted. In the first place, there was a number of masks necessary to introduce 7 to 8 channels, that is, dry etching technology, which was reduced to 5 channels now, which helped to greatly reduce the process cost. In order to reduce the production cost of the liquid crystal display device, the known development goal is to effectively reduce the manufacturing process cost of the active substrate, or the component cost of the substrate assembly engineering and the module mounting engineering. In order to reduce the cost of the process, there are methods such as shortening the process of engineering and reducing the cost of development or replacement of the process. However, the four masks and processes for obtaining the active substrate with four masks are described as an example of engineering reduction. . The four masks and processes are introduced into the halftone exposure technique, and the photolithography process is deleted. Therefore, FIG. 28 is a plan view of the unit pixel corresponding to the active substrate of the four mask processes, and FIG. 29 shows FIG. (e) Sectional drawings of the Α·Α', B-B' and C-C' lines. As described above, there are two types of insulated gate type transistors, and a channel-etched type of insulated gate type transistor is used here. First, in the same manner as the five mask processes, the first metal layer of a film thickness of 0.1 to 〇·3 μm is covered on the main surface of one of the glass substrates 2 by a vacuum film forming apparatus such as SPT (sputtering), as shown in Fig. 28(a). As shown in Fig. 29(a), the scanning line 1 1 and the storage capacitor line 16 which also serve as the gate electrode 1 1 选择性 are selectively formed by a detailed processing technique. • Secondly, the PCVD device is used in the entire glass substrate 2, and the SiNx (nitride sand) layer 30 formed of the gate insulating layer is substantially not included, and the impurity is formed, and the first channel formed by the channel including the insulating gate type transistor is formed. Amorphous germanium-11 - (9) 1247158 (a - S i ) layer 3 1 and impurities, three types of thin film layers such as the second SiNx layer 33 formed by the source and the drain of the insulating gate type transistor, for example The film thickness of 0. 3 μιη, 〇.2 μιη, and 0·5 μπι, respectively, was covered. Next, using a vacuum film forming apparatus such as SPT, a Ti thin film layer 34 is formed as a heat resistant metal layer having a film thickness of about ΐμπι, and an A1 thin film layer 35 is used as a low resistance wiring layer having a thickness of about 0.3 μm, such as a Ti thin film layer 36. An intermediate conductive layer having a thickness of about 0.1 μm, that is, a source/drain wiring material, which is selectively covered, and a gate electrode 21 which selectively forms an insulated gate type transistor and also serves as a source electrode The signal line 12, but when the selective pattern is formed, by the halftone exposure technique, as shown in FIG. 28(b) and FIG. 29(b), the maximum characteristic is the channel formation between the source and the drain wiring. The film thickness of the field 80 Β (hatched portion) is, for example, 1·5 μm, forming a thinner photosensitive film than the source/drain wiring formation field of 80 A (1 2 ) and 80 A (2 1 ) film thickness of 3 μm Resin pattern 80 A, 80B. The photosensitive resin patterns 80A and 80B are produced in a substrate for a liquid crystal display device, and since a positive photosensitive resin is used, the source/drain wiring formation region 80A is black, that is, a Cr film is formed. It is gray, for example, a Cr pattern of a line width/line width (Line And Space) is formed, and other fields are white, that is, if a mask such as a Cr film is removed. In the gray field, the resolution of the exposure machine is insufficient, so the line/space line width (Line And Space) cannot be analyzed, and since the light from the light source of the bulb can be transmitted through only half of the light, the positive sensitivity can be obtained. Resin film characteristics, photosensitive resin pattern 80A '80B ° -12- (10) 1247158 having a cross-sectional shape as shown in Fig. 29 (b), the photosensitive resin patterns 80A, 80B are used as masks, as shown in the figure As shown in FIG. 29(b), the Ti thin film layer 316, the A1 thin film layer 35, the Ti thin film layer 34, the second amorphous germanium layer 33, and the first amorphous germanium layer 31 are exposed to the gate insulating. After the layer 30, as shown in Fig. 28 (c) and Fig. 29 (c), the film thickness of the photosensitive resin patterns 80A, 80B is reduced by, for example, from 3 μm by the ashing means of oxygen plasma or the like. When the thickness is 5 μm or more, the photosensitive resin pattern 80 Β disappears to expose the channel region, and 80 C ( 12 ) and 80 C ( 21 ) remain only in the field of source/drain wiring formation. Here, the photosensitive resin patterns 80C ( 12 ) and 80C ( 21 ) having a reduced film thickness are used as a mask, and the Ti thin film layer between the source and the drain wiring (channel formation region) and the 薄膜1 thin film layer are further etched. The Ti thin film layer, the second amorphous germanium layer 33, and the first amorphous germanium layer 3 1A, and the first amorphous germanium layer 3 1A are etched to a thickness of about 0.05 to 0.1 μm. After etching the metal layer on the source/drain wiring, the first amorphous germanium layer 31 is etched by leaving 0.05 to 0.1 μm, so that the insulating gate-type electro-crystal system is obtained by the method. Etching. Further, it is preferable to enhance the anisotropy in order to control the change in the size of the pattern in the above oxygen plasma treatment, the reason of which will be described later.

Further, after the above-mentioned photosensitive resin patterns 80C ( 12 ) and 80C (2 1 ) are removed, as shown in Fig. 28 (d) and Fig. 29 (d) which are the same as the five mask processes, the entire surface of the glass substrate 2 is obtained. As a transparent insulating layer, a SiNx layer having a film thickness of about 3 μm is applied as a passivation insulating layer 3, and further, electrode terminals of the gate electrode 21 and the scanning line 11 and the signal line 12 are formed. In the field, the respective opening portions 62, 63, 64 are formed, and the passivation insulating layer 37 and the gate insulating layer 3 0 and -13-(11) 1247158 in the opening portion 63 are removed to expose a portion of the scanning line, and the opening portion 62 is removed. 64 inner insulating layer 37 exposes a portion of the gate electrode 2 1 and the signal line. Finally, use a vacuum film making device such as SPT to make j 0. 1~0. A transparent conductive layer of about 2 μm is covered with, for example, ITO or as shown in FIG. 28 (e) and FIG. 28 (e), and the insulating layer 37 includes an opening portion 62 by selective processing, and selectively forms a transparent portion. The active electrode 22 is completed by the pixel electrode 22. The electrode terminals 5A, 6A which are formed of transparent conductivity are selectively formed on the passivation insulating layer 37 in the opening portions 63, 64. In the five mask processes and the four mask processes, the thickness and type of the insulating layer in the openings 62, 63 are passively insulated due to the formation of the contact between the pole 21 and the scanning line 11 . When the layer 3 7 is compared with the gate insulating layer 30, the film forming temperature is poor, and the etching is performed by the etching solution of the fluoric acid type, and the etching is several thousand A/min, and the number is 100 A/min, and the difference is 1 The number of bits, the cross-sectional shape of the opening portion 62 on the 汲2 1 is also due to the fact that the upper portion is excessively corroded to control the aperture, so dry etching using a fluorine gas is employed. Although the dry etching is used, the opening portion 62 of the drain electrode 2 1 is only the passivation insulating layer 3 7, so that the overetching cannot be avoided compared to the opening portion of the scanning line 1 1 , and the intermediate 3 6 A may be utilized depending on the material. The gas is etched to reduce the film. Further, the photosensitive resin pattern of each of the etched layers is removed, and the polymer of the fluorinated surface is first removed to be ashed. 1 ~ 〇. The degree of passivation of the surface of the photosensitive resin pattern is cut off to a degree of 2 μηι. Good film thickness ΙΖΟ, ,, 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电The lower and engraved speed electrode is engraved without the oxygen electricity after the 63-series conductive layer bundle, and the organic stripping solution after the 14-(12) 1247158 is generally used, such as the stripping 106 made by Tokyo Yinghua Co., Ltd. When the intermediate conductive layer 36A is exposed and the aluminum layer 35A of the substrate is exposed, the A12 03 of the insulator is formed on the surface of the aluminum layer 35A by the oxygen plasma ashing treatment, and the pixel is 22 Between, it becomes impossible to get ohmic contact. Therefore, in order to reduce the interlayer conductive layer 36A, the film thickness is set to be, for example, 0. 2 μιη thick, and this problem can be solved. Or, when the openings 62 to 65 are formed, the aluminum layer 35 A is removed from the thin film layer 34A of the heat resistant metal layer of the base, and then the method of avoiding the pixel 22 is formed. In this case, the whisker is electrically conductive from the beginning. The benefit of layer 36A. However, in the former countermeasures, when the in-plane uniformity of the film thickness of these films is not good, the blending does not necessarily have to be effective, and the in-plane uniformity of the etching rate is not good. In the latter case, although the intermediate conductive layer 36A is not required, the removal process of the aluminum layer 35A is increased, and when the profile control of the opening portion 62 is insufficient, the pixel electrode 22 can be broken. In addition, on the channel-etched insulating gate type transistor, the first amorphous germanium layer 3 1 which does not contain impurities in the channel region is not thick beforehand (usually 0. 2 μm or more of the ground cover has a great influence on the in-plane uniformity of the glass substrate, and in particular, the transistor characteristics are liable to generate non-identical OFF currents. It has a great influence on the working rate of PC VD and the occurrence of dust, and it is also very important from the concept of production. In addition, in the four-mask process, the channel forming engineering system is selected to remove the source and the drain of the source/drain wiring 1 2 ' 2 1 between the source and the drain. The work can include the semiconductor layer of this material (13) 1247158 and the impurity, so it is decided to greatly affect the channel length of the ON-type transistor of the insulated gate type transistor (4~6μπι in the current quantity). The change in the length of this channel is due to the large change in the ON current of the insulated gate transistor. Therefore, strict manufacturing management is required. However, the channel length, that is, the pattern size in the halftone exposure field is subject to the exposure amount (light source). Intensity and pattern precision of the mask, especially the line and space size) 'The coating of the photosensitive resin is thick, the development processing of the photosensitive resin, and the amount of the photosensitive resin of the photosensitive resin which is used in the smear process are many. In addition, these in-plane uniformities complement each other and may not guarantee high yield and stable production. Compared with traditional manufacturing management, there is a need for stricter manufacturing management. At this stage, it can not be said that the height has reached the height. The level of completion. In particular, when the channel length is 6 μm or less, the influence of the pattern 吋 is large as the film thickness of the photoresist pattern is reduced, and the tendency thereof is more remarkable. The present invention is based on the related state of the art, and not only avoids the flaws in the formation of contacts similar to the conventional five-mask process or four-mask process, but also achieves the reduction of manufacturing engineering by using a halftone exposure technique in the manufacturing area. In addition, it has been found that the realization of the low price of the liquid crystal substrate, in response to the increase in demand, has also necessarily pursued the necessity of further reduction of the number of manufacturing engineering, and by simplifying other major manufacturing processes or giving low cost technology. The price of the present invention will be further increased. SUMMARY OF THE INVENTION In the present invention, the formation of an etch stop layer is first performed, and the halftone exposure technique is firstly managed by pattern precision, which is suitable for easy scanning - 16 - (14) 1247158 line forming engineering and providing access The contact of the electrical connection of the scan line forms a project to achieve the deletion of the manufacturing process. Further, the source and the drain wiring are effectively passivated, and the process of forming an insulating layer by forming the insulating layer on the surface of the source/drain wiring formed by the aluminum disclosed in Japanese Laid-Open Patent Publication No. Hei No. 2-216129 And low temperature. Further, the formation process of the pixel electrode disclosed in Japanese Laid-Open Patent Publication No. Hei 8-13 695 No. 1 is applicable to the present invention. In addition, for the further reduction project, the formation of the anodized layer of the source and the drain wiring is also applicable to the halftone exposure technology, and the protective layer formation process can be rationalized. [Patent Document 2] Japanese Laid-Open Patent Publication No. Hei. No. Hei. No. Hei. No. Hei. a gate type transistor, and a scanning line which also serves as a gate electrode of the insulating gate type transistor, a signal line which also serves as a source wiring, and a unit pixel which is connected to a pixel electrode of a drain wiring or the like a first transparent insulating substrate arranged in a two-dimensional matrix, and a liquid crystal obtained by filling a liquid crystal between a second transparent insulating substrate or a color filter that faces the first transparent insulating substrate The display device is characterized in that at least one of the main surfaces of the first transparent insulating substrate is formed with a scanning line composed of one or more first metal layers and having an insulating layer on the side surface thereof; and one layer is formed on the scanning line. The above-mentioned gate insulating layer; on the gate insulating layer on the gate electrode, the first semiconductor layer not containing impurities is formed in an island shape; and a thinner protective insulating layer is formed on the first semiconductor layer than the gate electrode ; in the aforementioned protective insulation On the first semiconductor layer, a pair of second semiconductor layers including impurities are formed on the first semiconductor layer, and a gate insulating layer on the scanning line is formed in the collar -17-(15) 1247158 outside the image display portion. a part of the scanning line is exposed; a source (signal line) and a drain formed of the anodized metal layer including one or more layers of the heat-resistant metal layer on the first transparent insulating substrate and the first transparent insulating substrate The wiring and the electrode terminal including the scanning line having the same opening and the first and second semiconductor layers around the opening; forming a transparent conductivity on one of the drain wiring and the first transparent insulating substrate The pixel electrode forms a transparent conductive electrode terminal on the signal line outside the image display portion; the source electrode overlaps the pixel electrode of the drain wiring, and the source terminal region of the signal line is at the source An anodized layer is formed on the surface of the drain wiring. With this configuration, the gate insulating layer is formed to have the same pattern width as the scanning line, and the other side of the scanning line is provided with a different insulating layer from the gate insulating layer, so that the intersection of the scanning line and the signal line becomes possible. This is a structural feature common to the liquid crystal display device of the present invention. Furthermore, the transparent conductive pixel electrode is formed on the glass substrate, and a protective insulating layer is formed on the channel between the source and the drain, and the protective channel is formed simultaneously on the surface of the signal line and the drain wiring. Insulating anodized layer of pentoxide (Ta205) or alumina (A 1 203 ) to impart passivation function, so there is no need to cover the passivation insulating layer on the glass substrate, and there is no insulated gate type The heat resistance of the crystal. Further, a TN type liquid crystal display device having transparent electrode terminals can be obtained. The liquid crystal display device according to the second aspect of the invention is characterized in that at least one of the first metal layers is formed on one main surface of the first transparent insulating substrate, and an insulating layer is formed on the side surface thereof. Scanning -18- (16) 1247158 lines, and transparent conductive pixel electrodes and signal line electrode terminals; forming more than one gate insulating layer on the scan line; gate insulation on the gate electrode a first semiconductor layer containing no impurities is formed in an island shape on the layer; a protective insulating layer having a finer gate electrode is formed on the first semiconductor layer; and a portion of the protective insulating layer is on the first semiconductor layer Forming a pair of second semiconductor layers including impurities; forming an opening in the gate insulating layer on the scanning line in a region outside the image display portion, exposing one portion of the scanning line; and including the first portion of the opening portion and the periphery of the opening portion a second semiconductor layer is formed with a transparent conductive scan line electrode terminal; and a part of the electrode terminal of the signal line is formed on the second semiconductor layer and the first transparent insulating substrate a source (signal line) composed of one or more second metal layers is formed on the heat-resistant metal layer, and is formed on the second semiconductor layer and on the first transparent insulating substrate and on one of the pixel electrodes. A drain wiring is formed, and a photosensitive organic insulating layer is formed on the source/drain wiring. The pixel electrode having the transparent conductivity is formed on the glass substrate, and a protective insulating layer is formed on the channel between the source and the drain to protect the channel, and the surface of the source/drain wiring is formed. Since the photosensitive organic insulating layer imparts a passivation function, it is not necessary to cover the entire surface of the passivation insulating layer on the glass substrate, and does not contain the heat resistance problem of the insulating gate type transistor. Further, a TN type liquid crystal display device having transparent conductive electrode terminals can be obtained. A liquid crystal display device according to claim 3, characterized in that at least one of the first transparent insulating substrate is formed on the main surface of the first transparent insulating substrate, and the conductive layer and the first metal layer are formed through -19-(17) 1247158. Forming a layer, forming a scan line having an insulating layer and electrode terminals of a transparent conductive pixel electrode and a signal line on a side surface thereof; forming one or more gate insulating layers on the scan line; on the gate electrode a first semiconductor layer containing no impurities is formed in an island shape on the gate insulating layer; a protective insulating layer thinner than the gate electrode is formed on the first semiconductor layer; and the first portion is on the protective insulating layer a pair of second semiconductor layers including impurities are formed on the semiconductor layer; and the gate insulating layer and the first metal layer on the scanning line are removed from the field outside the image display portion, and the transparent conductive layer formed by the electrode terminals of the scanning lines is exposed. And a part of the electrode terminal of the signal line on the second semiconductor layer and the electrode terminal of the signal line, comprising a refractory metal layer and forming a second metal layer of one or more layers The source wiring (signal line) and the second semiconductor layer and the first transparent insulating substrate are formed on the first transparent electrode substrate in the same manner as the pixel electrode, and the source wiring is formed on the source/drain wiring. Organic insulation layer. With this configuration, the transparent conductive pixel electrode is automatically formed on the glass substrate because the scanning line is formed at the same time, and a protective insulating layer is formed on the channel between the source and the drain to protect the channel. The surface of the source/drain wiring forms a photosensitive organic insulating layer to impart a passivation function, so that it is not necessary to further cover the entire surface of the transparent insulating layer on the glass substrate, and the liquid crystal display as described in claim 2 can be obtained. The same effect of the device. A liquid crystal display device according to claim 4, characterized in that at least one of the transparent conductive layer and the first metal layer is formed on one side of the first transparent insulating substrate and is formed on the side surface of the first transparent insulating substrate. Insulating • 20 - (18) 1247158 layer of scanning lines and transparent conductive pixel electrodes; on the scan line, forming more than one layer of gate insulating layer; on the gate electrode on the gate insulating layer, not The first semiconductor layer containing the impurity is formed in an island shape; a protective insulating layer having a finer gate electrode is formed on the first semiconductor layer; and a pair of the first insulating layer is formed on the first semiconductor layer a second semiconductor layer of impurities; in the field outside the image display portion, the gate insulating layer and the first metal layer on the scanning line are removed to expose a portion of the transparent conductive layer of the scanning line; and the first semiconductor layer is transparent to the first semiconductor layer a source wiring (signal line) including a second metal layer of one or more layers on the insulating substrate and a part of the electrode terminal of the signal line including a heat resistant metal layer In the semiconductor layer and the first transparent insulating substrate, a portion of the pixel electrode and the scanning line are formed in the same manner, and the scanning line electrode terminal is formed in the same region as the image display portion. A signal line electrode terminal composed of one portion of the signal line; a photosensitive organic insulating layer is formed on the signal line except for the electrode terminal of the signal line. With this configuration, the transparent conductive pixel electrode is formed on the glass substrate automatically because it is formed simultaneously with the scanning line, and a protective insulating layer is formed on the channel between the source and the drain to protect the channel. The surface of the signal line (source wiring) is provided with a minimum of passivation function by forming a photosensitive organic insulating layer, and the same effect as that of the liquid crystal display device of the second aspect of the patent application can be obtained. Further, a TN type liquid crystal display device having the same metal electrode terminal as the signal line can be obtained. The liquid crystal display device according to claim 5, wherein the 21_(19) 1247158 feature is formed by laminating at least one of the first transparent insulating substrate and the first conductive layer and the first metal layer. a scanning line and a transparent conductive pixel electrode having an insulating layer on a side surface thereof; forming one or more gate insulating layers on the scanning line; and not containing impurities on the gate insulating layer on the gate electrode The first semiconductor layer is formed in an island shape; a protective insulating layer having a finer gate electrode is formed on the first semiconductor layer; and a pair of impurities is formed on the first semiconductor layer on one of the protective insulating layers. a second semiconductor layer; a region outside the image display portion that removes a gate insulating layer on the scanning line from the first metal layer to expose a portion of the transparent conductive layer of the scanning line; and is insulated from the first transparent layer on the second semiconductor layer a source wiring (signal line) composed of one or more layers of anodizable metal layers is formed on the substrate, and is formed on one of the protective insulating layers and the first On one side of the semiconductor layer and the first transparent insulating substrate and the pixel electrode, the electrode terminal of the scanning line is formed in the same manner as the scanning line, and the electrode terminal is formed in the field outside the image display portion. An electrode terminal of a signal line composed of one of the signal lines; an anode oxide layer is formed on the source/drain wiring except for the electrode terminal of the signal line. The pixel electrode having the transparent conductivity is formed on the glass substrate by the simultaneous formation of the scanning line and the scanning line, and a protective insulating layer is formed on the channel between the source and the drain to protect the channel. The surface of the wire and the drain wire is imparted with a passivation function by forming an insulating anodized layer of molybdenum pentoxide (Ta205) or aluminum oxide (Al2〇3), and can be obtained and as described in the first item of the patent application. The liquid crystal display device has the same effect of 22-(20) 1247158. Further, a TN type liquid crystal display device having the same metal electrode terminal as the signal line can be obtained. The liquid crystal display device as described in claim 6 is characterized in that it has at least an insulating gate type transistor on one main surface and a scanning line which also serves as a gate electrode of the insulating gate type transistor, and also serves as a scanning line a signal line of the source wiring, and a pixel electrode connected to the drain electrode of the insulating gate type transistor, and a unit pixel of a counter electrode formed by a specific distance from the pixel electrode, etc. a liquid crystal display device in which a first transparent insulating substrate of a two-dimensional matrix shape and a second transparent insulating substrate or a color filter that faces the first transparent insulating substrate are filled with liquid crystal; The present invention is characterized in that at least one of the first transparent layers of the first transparent insulating substrate is formed with a scanning line and a counter electrode which are composed of one or more first metal layers and have an insulating layer on the side surface thereof; One or more gate insulating layers are formed on the electrode; on the gate insulating layer on the gate electrode, the first semiconductor layer containing no impurities is formed in an island shape, and a gate is formed on the first semiconductor layer Finer electrode a protective insulating layer; a pair of second semiconductor layers including impurities are formed on one portion of the protective insulating layer and the first semiconductor layer; and an opening is formed in the gate insulating layer on the scanning line in a region outside the image display portion And exposing a portion of the scanning line; forming a source (signal line) composed of a second metal layer of one or more layers on the second transparent layer and the first transparent insulating substrate; a pole wiring (pixel electrode); an electrode terminal including the same scanning line formed by the opening and the first and second semiconductor layers around the opening, and is formed by one of the signal lines in a region outside the image display portion. 23 - (21) 1247158 Electrode terminal of the signal line formed; except for the electrode terminal of the signal line, a photosensitive organic insulating layer is formed on the signal line. Thus, the pixel electrode and the counter electrode are formed on the glass. And forming a protective insulating layer and a channel on the channel between the source and the drain, and forming a photosensitive organic insulating layer on the surface of the signal line and a minimum necessary Of function. Further, since the counter electrode is formed of the gate insulating layer, the same effect as that of the liquid crystal display device of the second aspect of the patent application can be obtained. Further, an IPS type liquid crystal display device having a metal electrode terminal connected to a signal line can be obtained. The liquid crystal display device according to claim 7 is characterized in that at least one of the first metal layers is formed on at least one main surface of the first transparent insulating substrate, and an insulating scan line and a pair are formed on the side surface thereof. a plurality of gate insulating layers on the scan line and the counter electrode; and a first semiconductor layer having no impurity in the gate insulating layer on the gate electrode is formed in an island shape; in the first body layer Forming a protective insulating layer thinner than the gate electrode; forming a pair of second semiconductor layers on the first semiconductor layer on one of the edge layers; and scanning the lines outside the image display portion The gate insulating layer forms an opening to expose one of the scanning lines, and the first transparent insulating substrate and the first transparent insulating substrate include a heat-resistant layer to form a wiring composed of one or more anodizable metal layers. (signal line) • drain wiring (pixel electrode); and electrode terminal including the first and second semiconductor layers around the front opening and the opening, and the outer side of the image display unit Formed by the substrate on the letter and formed by the same layer, which is formed by one layer, and the metal source on the semi-conductor is a part of the scan line -24-(22) 1247158 An electrode terminal of the signal line formed; an anode oxide layer is formed on the source/drain wiring except for the terminal of the signal line, whereby the pixel electrode and the counter electrode are formed on the glass substrate, And a protective insulating layer is formed on the channel between the source and the drain to ensure the channel, and at the same time, the surface of the signal line and the drain wiring is formed by an insulating anodized layer of pentoxide (Ta205) or aluminum oxide ( Al2〇3) imparts a passivation function and can obtain the same effect as the liquid crystal display device as recited in claim 1 of the patent application. Further, a TN type liquid crystal display device having a metal electrode terminal connected to a signal line can be obtained. Further, since the gate insulating layer is formed in the electrode layer, the same effect as the liquid crystal display device described in the first aspect of the invention can be obtained. Further, an IPS type liquid crystal display having the same metal electrode terminal as the signal line can be obtained. The liquid crystal image display device as described in claim 8 is the liquid crystal display as described in claim 1, item 1, item 2, item 4, item 5, item 6, item 6, or item 7. The device, wherein the insulating layer formed on the side of the scan line is an organic insulating layer. By this configuration, the material or structure of the scanning line is not limited, and the organic insulating layer can be formed by electroforming on the side of the scanning line, and the formation process of the scanning line can be continuously processed by one mask using the halftone exposure technique. And the formation of contact. The liquid crystal display device according to claim 9, wherein the first metal layer is provided by the liquid crystal display device according to the first, second, sixth or seventh aspect of the patent application. The anode oxy-electrode board is formed by the metal of the same type of metal--25- (23) 1247158, and the insulating layer formed on the side of the scanning line is an anodized layer. By forming the side of the scanning line by this, an anodic oxide layer can be formed by anodization. Once the halftone exposure technique is used, the formation process of the scanning line and the formation of the contact are continuously processed by one mask. The method of manufacturing a liquid crystal display device according to the first aspect of the invention is characterized in that the method for forming an etch-off layer, the formation of a scanning line, the formation of a contact, and the like are performed by halftone. The exposure technique uses the same mask for processing, forming the source and drain wiring, and forming a transparent conductive pixel electrode while anodizing the source and drain wiring. With this configuration, the necessary scanning line forming process and the contact forming process for the electrical connection to the scanning line can be processed by using one mask, thereby realizing the reduction of the number of photo etching processes. Moreover, the contact system itself integrally forms a scanning line, and the other side of the scanning line is imparted with another insulating layer different from the gate insulating layer, making it possible to cross the scanning line and the signal line. This is a feature common to the liquid crystal display device manufacturing method of the present invention, except for the fifteenth application patent and the sixth aspect of the patent application. In addition, a protective insulating layer is formed on the channel between the source and the drain to protect the channel, and at the same time, when the pixel electrode is formed, the source and the drain wiring are anodized, so that the unnecessary passivation insulation is also eliminated. The layer was formed and manufactured, and as a result, a TN type liquid crystal display device can be fabricated using four masks. The method of manufacturing a liquid crystal display device according to the second aspect of the invention is characterized in that: the process of forming an etch-off layer, the formation of a scan line and the formation of a contact by halftone exposure -26- (24) 1247158 Engineering of light technology using the same mask, engineering of forming a transparent pixel electrode, and engineering using a photosensitive organic insulating layer. By this configuration, the formation of the scanning line and the shape of the contact are reduced by the number of photo-etching processes processed using one mask. Further, a protective insulating channel is formed on the channel between the source and the drain, and at the same time, when the source/drain wiring is formed, the photosensitive organic insulating layer is selectively left only on the source wiring, so that the passive insulating layer is also required. The layer was formed and manufactured, and as a result, a TN type liquid crystal display device was produced. Patent Application No. 12 is a manufacturing method of a liquid crystal display device as described in the patent application scope, which has the following features: a process of a cut-off layer, which is formed and contacted by a scanning line of a transparent conductive layer and a layer of a first metal layer. The process of forming a photomask by a halftone exposure technique, the process of removing the contact with the inner layer during contact formation, and the process of forming the pole wiring using the photosensitive organic insulating layer. By this configuration, the engineering number of the photoreceptor electrode and the scanning line is cut by one photo-illumination, and the formation of the scanning line is engineered, and the photo-etching process which is processed by using one mask is simultaneously realized. Further, a protective and protective channel is formed on the channel between the source and the drain, and a photosensitive organic insulating layer is selectively left on the gate and drain wiring during the formation of the source/drain wiring. The formation of the insulating layer is the result of the manufacturing process. The result is a clear conductivity and a source-forming project. The solid layer and the protective pole and the bungee-cut are not required to be formed by the three masks. The source and the mask are processed and the contact number is reduced to protect the insulating layer. The source can be used only. The 27 (25) 1247158 3 mask can be used to fabricate the TN type liquid crystal display device. The method of manufacturing a liquid crystal display device according to claim 4, characterized in that the uranium engraved cut-off layer is formed by laminating a transparent conductive layer and a first metal layer. The formed scan line formation and contact formation are processed by the same mask by the halftone exposure technique, the process of removing the first metal layer in the contact during contact formation, and the formation using the photosensitive organic insulating layer. Source. 汲 Extreme wiring works. By structuring the photoreceptor electrode and the scanning line, the photo-etching process number processed by using one mask, and the formation of the scanning line and the formation of the contact, using a mask to process the photo The reduction of the number of etching projects is achieved at the same time. Further, a protective insulating layer is formed on the channel between the source and the drain to protect the channel, and at the same time, when the source/drain wiring is formed, halftone exposure technology is used and only on the signal line, by selective residual sensitivity The organic insulating layer makes it possible to eliminate the formation of an unnecessary passivation insulating layer. As a result of the manufacturing process, a TN type liquid crystal display device can be fabricated using three masks. The method for manufacturing a liquid crystal display device according to the fifth aspect of the invention is characterized in that: the method for forming a piercing cut-off layer, the layer of the transparent conductive layer and the first metal layer The formation of the scan line formed by the product and the formation of the contact are processed by the same mask using halftone exposure technology, the process of removing the first metal layer in contact during contact formation, and the use of halftone exposure technology. At the same time as the source/drain wiring is formed, only the source of the source and the drain wiring are anodized. -28- (26) 1247158 By the construction of the pixel electrode and the scanning line, the photo etching engineering number processed by using one mask, and the formation of the scanning line and the formation of the contact, use 1 The reduction of the number of photo-etching processes processed by the reticle is simultaneously achieved. Further, a protective insulating layer is formed on the channel between the source and the drain to protect the channel, and at the time of formation of the source/drain wiring, a half-tone exposure technique is used to selectively form an anode on the source/drain wiring. The oxide layer makes it possible to delete the formation process of the unnecessary passivation insulating layer. As a result, a TN type liquid crystal display device can be manufactured using three masks. Patent application No. 15 is as claimed in claim 6 A method of manufacturing a liquid crystal display device according to the invention, comprising the steps of forming an etch-off layer, forming a multilayer film pattern corresponding to a scan line and a counter electrode, forming a contact, and using a sensitization by a halftone exposure technique The organic insulating layer is formed to form a source/drain wiring while leaving only the photosensitive organic insulating layer on the signal line. A protective insulating layer is formed on the channel formed between the source and the drain, thereby protecting the channel, and at the same time, when the source/drain wiring is formed, the halftone exposure technique is used to selectively leave the photosensitive light only on the signal line. The organic insulating layer makes it possible to cut off the formation process of the unnecessary passivation insulating layer, and as a result, an ISP type liquid crystal display device can be fabricated using four masks. The method of manufacturing a liquid crystal display device according to claim 7 is characterized in that it has a process of forming an etch-off layer to form a multilayer film corresponding to the scanning line and the counter electrode - 29 - (27) 1247158, the project of forming contact" and the use of halftone exposure technology to form source-drain wiring and anodizing only source-drain wiring. The protective insulating layer is formed on the channel formed between the source and the drain to protect the channel, and the half-tone exposure technique is used for forming the source/drain wiring, and the source/drain wiring is selected. The formation of an anodized layer makes it possible to eliminate the formation of an unnecessary passivation insulating layer. As a result, an ISP type liquid crystal display device can be fabricated using four masks. The method of manufacturing a liquid crystal display device according to claim 6 is characterized in that it has a process of forming an etch-off layer, and the formation of the scanning line and the counter electrode and the formation of the contact are utilized. The same mask processing is used by the halftone exposure technique, and the photosensitive organic insulating layer is used by the halftone exposure technique to form the source/drain wiring while leaving the photosensitive organic insulating layer only on the signal line. By this configuration, the formation process of the scanning line and the counter electrode and the formation of the contact are performed by using one mask process, and the number of photo etching processes is reduced. Further, a protective insulating layer is formed on the channel between the source and the drain, and the protective channel is formed. At the same time, when the source/drain wiring is formed, the halftone exposure technique is used to selectively leave the photosensitive organic insulating only on the signal line. The layer allows the formation of an unnecessary passivation insulating layer to be formed, and as a result, an ISP type liquid crystal display device can be fabricated using three masks. The method of manufacturing a liquid crystal display device according to claim 7 is characterized in that the method of forming an etch-off layer is performed, and formation of a scan line and a counter electrode and formation of a contact are performed by • 30- (28) 1247158 Halftone exposure technology works with the same mask, and uses halftone exposure technology to form source and drain wiring while only anodizing the source and drain wiring. With this configuration, the formation process of the scanning line and the counter electrode and the formation of the contact can be performed by using one mask processing, and the number of photo etching processes can be reduced. Further, a protective insulating layer is formed on the channel between the source and the drain to protect the channel, and at the time of formation of the source/drain wiring, a half-tone exposure technique is used to selectively form an anode on the source/drain wiring. The oxide layer makes it possible to cut off the formation process of the unnecessary passivation insulating layer, and as a result, an ISP type liquid crystal display device can be fabricated using three masks. The scope of application for patents is 19th, 11th, 12th, 13th, 14th, 15th, 16th, 17th or 18th. In the method of manufacturing a liquid crystal display device described above, the insulating layer formed on the side surface of the scanning line is an organic insulating layer, and is formed by electricity. By this configuration, it is not limited to the material or structure of the scanning line, and the organic insulating layer can be formed by electroforming on the side of the scanning line, and the scanning line can be continuously processed by one mask using the halftone exposure technique. Formation engineering and contact formation engineering. The ninth aspect of the patent application scope is the manufacturing method of the liquid crystal display device as described in claim 10, the first claim, the first, the fifth, the sixth, the seventh or the eighth, wherein The first metal layer is formed of an anodizable metal layer, and the insulating layer formed on the side of the scanning line is formed by anodization. By this configuration, the anodized layer can be formed by anodization on the side of the scanning line, and the formation process and contact formation of the scanning line can be continuously processed by the 1 -31·(29) 1247158 reticle using the halftone exposure technique. engineering. [Effects of the Invention] In the liquid crystal display device of the present invention, since the insulating gate type electric crystal system has a protective insulating layer on the channel, it is only on the source/drain wiring in the image display portion, or only a photosensitive organic insulating layer is selectively formed on the signal line, or a source/drain wiring formed by anodization is formed by anodizing the source/drain wiring material, and an insulating layer is formed on the surface thereof. The active substrate is given a passivation function. Therefore, in the production of the active substrate constituting the liquid crystal display device, the insulating gate type transistor in which the amorphous germanium layer is formed as a semiconductor layer is not required to have a special heat treatment, and excessive heat resistance is not required. In other words, in the case of passivation formation, there is no effect of causing deterioration in electrical properties. Further, when the source/drain wiring is anodized, the halftone exposure technique is introduced to selectively protect the electrode terminals of the scanning line or the signal line, thereby obtaining an effect of preventing an increase in the number of photo etching processes. The main point of the present invention is to initially form an etch-off layer, and secondly to form a contact line between the formation process of the scan line and the electrical connection to the scan line, and introduce a halftone exposure technique to make the project cut by one mask. And by forming an organic insulating layer or anodizing on the side of the exposed scan line, a structural feature of the intersection of the scan line and the signal line can be produced. In addition, by introducing a pseudo-pixel electrode, the rationalization and complementation of the pixel electrode and the scanning line are processed by one mask, and the photo-etching engineering number can be further deleted by using the conventional 5 channels, and 4 or 3 can be used. The photomask is used to fabricate a liquid crystal display device, and from the viewpoint of cost reduction of the liquid crystal display device, the industrial price is also extremely high. At the same time, the precision of the pattern of these projects is not so high, so it has little effect on yield or quality and is easy to produce and manage. Further, in the IPS type liquid crystal display device of the sixth embodiment and the seventh embodiment, the electric field generated between the counter electrode and the pixel electrode is applied only to the gate insulating layer and the liquid crystal layer on the counter electrode, and the embodiment is applied. 8 and the IPS type liquid crystal display device of the ninth embodiment, since the gate insulating layer on the same counter electrode and the anodized layer of the liquid crystal layer and the pixel electrode are applied, it does not intervene any conventional disadvantages. The passivation of the insulating layer also has the advantage of avoiding burnt afterimages. The reason is that the anode oxide layer of the drain wiring (pixel electrode) is functionalized as a high resistance layer compared to the insulating layer, and no charge is accumulated. Furthermore, the focus of the present invention is to first form an etch-off layer when the active substrate is fabricated, and secondly to form a projecting and contact formation of the scan lines (and the counter electrode) by introducing a halftone exposure. The technique makes it possible to cut off the work of one mask processing while exposing the side of the scanning line (and the counter electrode) to form an organic insulating layer or an anodized layer of the insulating layer, and with respect to the other structure, the pixel is The difference in the material of the electrode, the gate insulating layer, or the like, the film thickness of the display device, or the manufacturing method thereof is of course within the scope of the present invention, and even in the case of a liquid crystal display device or a reflection type using a liquid crystal of a vertical alignment. The liquid crystal display device has the same usefulness as the present invention, and is not limited to the semiconductor layer or the amorphous germanium of the insulating gate type transistor. [Embodiment] -33- (31) 1247158 [Best Mode for Carrying Out the Invention] An embodiment of the present invention will be described with reference to Figs. 1 to 22 . 1 is a plan view showing a semiconductor device (active substrate) for a display device according to Embodiment 1 of the present invention, and FIG. 2 shows a line A-A' of FIG. 1, and a line B-B' and C-C'. A cross-sectional view of the manufacturing process. Similarly, Embodiment 2 is shown in FIG. 3 and FIG. 4, Embodiment 3 is FIG. 5 and FIG. 6, Embodiment 4 is FIG. 7 and FIG. 8, Embodiment 5 is FIG. 9 and FIG. 10, and Embodiment 6 is FIG. 12, the embodiment 7 is FIG. 13 and FIG. 14, the embodiment 8 is FIG. 15 and FIG. 16, and the embodiment 9 is FIG. 17 and FIG. 18, and the plan view of the active substrate and the cross-sectional view of the manufacturing process are shown. In the same manner, the same portions are denoted by the same reference numerals, and the detailed description is omitted. [Example 1] On the first embodiment of the glass substrate 2, a vacuum film forming apparatus such as SPT was used to cover the main surface of the glass substrate 2, such as Cr, Ta, Mo, or the like, or Metal ruthenium compound as a film thickness of 0. 1~0. The first metal layer of 3 μm. Although it is explicitly described below, in the present invention, in the case where the insulating layer is formed on the side of the scanning line, the organic insulating layer is selected, and there is almost no limitation of the scanning line material, but the insulating layer formed on the side of the scanning line is anodized. In the case of a layer, the anodized layer is required to have insulating properties, and in the case where the Ta monomer is high in resistance and the A1 monomer is inferior in heat resistance, the low resistance of the scanning line can be selected, and heat resistance can be selected. Single layer structure of A1 (Zr, Ta, Nd) alloy or the like, or single layer structure of Al/Ta, Ta/Al/Ta, Al/Al (Ta, Zr, Nd) alloy, etc. -34- (32) 1247158 The construction of the scan line. Further, Ta, Zr or Nd having a coefficient of A1 (Ta, Zr, Nd) or less means an A1 alloy having a high heat resistance to be added. Next, in the entire glass substrate 2, the first SiN layer 30 serving as a gate insulating layer and the first amorphous germanium layer 3 serving as a channel of the insulating gate type transistor using almost no impurity are used in the PC VD device. 1 and 3 layers of the second SiNx layer 32 formed by the insulating layer of the protection channel are respectively 0. 3μιη, 0. 05μιη, Ο. The film thickness of ίμιη is covered by the thickness. Further, as shown in FIG. 1(a) and FIG. 2(a), the second SiNx layer 32 of the uppermost layer is selectively etched by a fine processing technique to form a protective insulating layer of the insulating gate type transistor (or The second SiNx layer 32D is formed by etching the cut-off layer or the channel protective layer. The first amorphous germanium layer 3 1 is exposed, and the PC VD device is used. The second amorphous germanium layer 33 is used as an impurity, such as 0. After the film thickness of the film of 05 μιη is covered, as shown in Fig. 1 (b) and Fig. 2 (b), the opening portion 63 of the contact forming region 81 is formed, and the film thickness of 65 系 is corresponding to the scanning line 1 1 and the accumulation by Ιμπι The film thickness of the capacitor line 16 is 8 μm, and the thin photosensitive resin patterns 81A, 81B are formed by a halftone exposure technique, and the photosensitive resin patterns 8 1 A, 8 1 Β are used as a mask. The cover selectively removes the second amorphous germanium layer 3 3 , the first amorphous germanium layer 3 1 , the gate insulating layer 30 , and the first metal layer to expose the glass substrate 2 . Since the size of the contact is usually larger than 1 〇 μτη, it is also easy to fabricate a mask of 8 1 Β (intermediate adjustment) and to perform precision management of the completed dimensions. -35 - (33) 1247158 Next, when the photosensitive resin pattern 8 1 A, 8 1 B is reduced by 1 μm or more by means of ashing means such as oxygen plasma, as shown in Fig. 1 (c) and Fig. 2 ( As shown in c), the photosensitive resin pattern 8 1 Β disappears, and the second amorphous germanium layer 33 Α, 33 Α in the opening 63 Α, 65 露出 is exposed, and the scanning line 1 1 and the storage capacitor line 16 can be reduced as they are. The photosensitive resin pattern of the film was 8 1 C. The photosensitive resin pattern 8 1 C (black field), that is, the pattern width of the gate electrode UA is added to the size of the protective insulating layer to add the precision of the mask, so the protective insulating layer is 1 12 12 μπι, with precision When it is made of ±3μπι, it is 16~18 μm even if it is the smallest, and the dimensional precision is not high. Further, the relationship between the scanning line 1 1 and the counter electrode 16 width from the resistance 通常 is usually set to ΙΟμηη or more. However, on the basis of the present invention, as in the conventional example, the semiconductor layer is formed without a semiconductor layer, and the semiconductor layer is formed to have the same width as the gate electrode, and if it is changed by the photoresist pattern 81A to 81C, the photoresist pattern is formed. When the film is reduced by 1 μπι, the size is reduced by 2 μm, and the subsequent mask and precision of the source and drain wiring are reduced by 1 μπι and ±2 μπι, which is more severe than the former. Therefore, it is preferable to enhance the anisotropy for controlling the change in the pattern size in the above oxygen plasma treatment. Specifically, it is preferable to have a RIE (Reactive Ion Etching) method, and a high-density plasma source ICP (Inductive Coupled Plasama) method or a TCP (Transfer Coupled PIasama) method. Alternatively, it is preferable to predict the dimensional change of the photoresist pattern, and the pattern size of the photoresist pattern 81A is preliminarily designed to seek a corresponding treatment on the process. Thereafter, as shown in Fig. 2(c), an insulating layer 76 is formed on the side surface of the gate electrode 1 1 A - 36 - (34) 1247158. For this reason, as shown in FIG. 19, the wiring 7 7 and the peripheral portion of the gas substrate 2 are stacked in parallel with the scanning line 1 1 (the storage capacitor line 16 is also the same, but not shown here), in the plating or the anode. When oxidizing, it is necessary to give the connection pattern 78 of the potential, and more suitably use the amorphous ruthenium layer 31, 33 of the plasma CVD and the appropriate mask means of the tantalum nitride layers 30, 32, and the film formation field is used by The connection pattern 798 is defined on the inner side, and at least the necessity of exposing the connection pattern 78 is required. The connection pattern 7 8 is used to connect the photosensitive resin pattern 81C (78) on the connection pattern 78 by using a connection means such as a crocodile clip having a sharp end, and a plus potential is applied to the scanning line 11, and ethylene glycol is used as In the reaction liquid of the main component, when the glass substrate 2 is immersed in the anodic oxidation, if the scanning line 11 is an alloy of the A1 type, alumina (A1203) having a film thickness of 0·3 μm such as a reaction voltage of 200 V is formed. In the case of electroplating, as shown in the literature, the monthly publication "Polymer Processing", January 2001, the pentacarboxy-containing polyimine coating solution forms a film thickness of 〇·3μιη with a plating voltage number ν. A layer of quinone imine resin. When the insulating layer is formed on the side of the exposed scanning line 1 1 and the storage capacitor line 16 , the precaution is that the parallel alignment of the scanning lines 1 1 must be released during the subsequent manufacturing process. Otherwise, not only the electrical inspection of the active substrate 2 but also the electrical inspection is performed. Of course, there are obstacles to the actual operation of the liquid crystal display device. The simple method is to use evapotranspiration or mechanical ablation by irradiation of laser light as a means of releasing, but the detailed description is omitted. [Non-Patent Document 1] Monthly publication "Polymer Processing" After forming the insulating layer 76 in January, 2002, as shown in Fig. 1 (d) and Fig. 2 (d), the photosensitive resin pattern 8 1 C which is reduced in film is formed. As a mask 'selectively etched opening-37-(35) 1247158 part 63A, 65A of the second amorphous germanium layer 33A, 33B 矽 layer 31 A, 31B and gate insulating layer 30A, 30B A portion 73 and a portion 75 of the storage capacitor line 16. After the photosensitive resin pattern 80C is removed, a vacuum film forming apparatus such as SPT is used for the formation of the source line, and the film layer 34 of Ta or the like is used as a film thickness of 0. 1 μπι of the positive thermal metal layer, and the Α1 thin film layer 35 as the film thickness 0. 3μηη an anodizable low-resistance wiring layer, and then sequentially coating the film layer 36 as a film thickness of 0. The same conductive layer of 1 μπι. Further, the source material produced by the three-layer film and the second amorphous germanium layer 3 3 and the first amorphous germanium layer 3 1A, 3 are processed in such a manner that the photosensitive resin pattern is used to follow the gate insulating layer. 30A, 30B, as shown in Fig. 1 (e) and Fig. 2 (e is a stack of 3 4 A, 3 5 A and 3 6 A, a gate electrode 2 1 which selectively forms an insulator, and a signal line which also serves as a source electrode The drain wirings 1 2, 2 1 are offset, and in order not to be partially overlapped with the channel protective layer 32, the side effects of the battery are avoided, and the source electrodes 12, 21 are included in one part of the scanning line. 73, also the electrode terminal 5 at the same time, but since the electrode terminal 5 is not required, the transparent electrode terminal 5 is directly formed by engineering. If it is limited, it is reasonable to simplify the formation of a Ta single layer, and further in the A1 alloy. In the above case, since the chemical potential is lowered and the chemical corrosion reaction is controlled by I TO, in this case, it is not necessary to match the first amorphous line and the drain electrode with the electrode such as Ti, and the degree of resistance of the extreme oxidation is The same cover Ta and other thin pole oxidation • Bungee wiring 1 B, by fine etching Is exposed), the crystal by the gate 12 is electrically type. Source · Action, reason. Usually, the scan line is formed by the drain wiring, and the intermediate conductive-38- (36) 1247158 layer 36 can be used in the subsequent alkaline solution of the Nb-added resistor and the source/drain wiring 12, 21 can be used. The layered structure is constructed, and the source is simplified. The structure of the bungee wiring 1 2, 2 1 . The ITO of the conductive layer is also the same as IZO. After the source/drain wirings 12 and 21 are formed, the vacuum film forming apparatus 'such as SPT is used as a transparent conductive layer of a film thickness ,·ι' degree to cover the entire surface of the glass, and is covered by, for example, 1το ' as shown in Fig. 1 2 (f) As shown, the electrode 22 is selectively formed on the glass substrate 2 by a fine processing technique. At this time, in the field outside the image display portion, the electrode terminal 6 on the scanning terminal 5 and a part of the signal line is also patterned in a conductive layer to form a transparent conductive electrode terminal 5'6. As described above, the electrode terminal 5 is not formed, and at this time, the opening portion 6 3 A is formed to form the direct electrode terminal 5 Α. Further, in the conventional example, the transparent conductive wire 40 is provided on the periphery of the active substrate 2, and the electrode terminals 5A, 6A and the short-line 40 are stripe-shaped, so that the resistance can be increased and the static electricity can be prevented. Next, as shown in Fig. 1 (g) and Fig. 2 (g), the photosensitive resin pattern 83 A of the pattern-forming pixel electrode 22 is irradiated with light while anodizing the source/drain wiring 1 2 ' 2 1 An oxide layer is formed on the surface. At this time, the electrode terminals 5A, 6A are protected by the resin patterns 8 3 B, 8 3 C. Although it is Ta on the source and the ruthenium; but on the side of one side of the channel side, Ta, Al, Ti and the second amorphous ruthenium layer 33A are laminated, and two layers of the transparent substrate are changed. The 0. 2 μm process (f) and the electrode of the pixel electrode of the i-electrode 21 can form a transparent electrode terminal, and the short electrode can be used as a mask for high-power selectivity. On the other side of the other side opposite to the channel -39-(37) 1247158, the surface of the photosensitive line 12, 21 is exposed to the lamination of Ta, A1 and Ti, and by anodization, the second non- The germanium layer 33A is each modified into a cerium oxide layer (SiO 2 ) 66 (not shown) containing impurities, Ti is a semiconductor titanium oxide (Ti02 ) 68 , and A1 is an insulating layer of aluminum oxide (Al 2 〇 3 ) 69 . And Ta is made into an insulating layer of pentoxide (Ta2〇5) 7〇. The Oxide 68 is not an insulating layer, but the film thickness is small and the exposed area is small, so there is no problem in passivation, but it is preferable that the heat-resistant metal film layer 34A also selects Ta in advance. However, it is necessary for the Ta system to pay attention to the fact that unlike the Ti, the surface oxide layer of the base is absorbed and it is not easy to make the function of the ohmic contact. It is also disclosed in the prior art that an anodized layer of a good film quality is formed on the drain wiring 2, and anodization is performed while irradiating light to become an important point of the anode oxidation process. Specifically, if a sufficiently strong light of 10,000 lux is applied, and the leakage current of the insulated gate type transistor exceeds μΑ, anodization is performed at an area of 10 mA/cm 2 from the area of the gate electrode 21 The current density for obtaining a good film quality can be obtained. However, even if the film quality of the anodized layer 70 of the drain wiring 21 is insufficient, the reason why sufficient reliability is generally obtained is that the driving signal applied to the liquid crystal cell is substantially AC, and is formed in the opposite direction of the color filter. The DC voltage component is reduced between the counter electrode 14 and the pixel electrode 22 (the drain electrode 2 1 ) on the surface, and the voltage of the counter electrode 14 is adjusted during the image inspection (flicker reduction adjustment) Therefore, in the basic principle, the insulating layer can be formed only on the signal line 12 by not flowing a DC component. The thickness of each oxide layer of ruthenium pentoxide 70, alumina 69, titanium oxide 68, and ruthenium oxide layer 66 formed by anodization is 〇1~〇·2μπ1 degree -40-(38) 1247158 is sufficient, and B is used. The reaction liquid such as a diol or the like is applied with a voltage of more than 100 V to achieve passivation wiring. When the source/drain wirings 12 and 21 are anodized, the precautions are not shown, but all of the signal lines 12 need to be electrically connected in parallel or in series, and somewhere in the subsequent manufacturing process, if not When the series/parallel is released, not only the electrical inspection of the active substrate 2 is problematic, but also the actual operation of the liquid crystal display device is also hindered. The simple method is to use the evapotranspiration by laser irradiation or mechanical resection as a means of release, but the detailed description is omitted. The surface of the pixel electrode 22 is not covered by the photosensitive resin pattern 83A in advance, and it is not necessary to pass through the anodized electrode 22, and it is not necessary to pass through the insulating gate type transistor to ensure a reaction current flowing through the drain electrode 21 to a certain extent or more. Finally, the photosensitive resin patterns 83 A to 83D are removed, and as shown in Fig. 1 (h) and Fig. 2 (h), the active substrate 2 (semiconductor for a display device) is completed. In this manner, the active substrate 2 and the color filter obtained by bonding are bonded to each other to form a liquid crystal substrate, and the first embodiment of the present invention is completed. As shown in FIG. 1( h ), the storage capacitor line 16 and the pixel electrode 22 pass through the gate insulating layer 30B and are planarly overlapped (the right lower oblique line portion 5 1 ), but the accumulation is made. The configuration of the capacitor 15 is not limited thereto, and it is also possible to transmit the insulating layer including the insulating layer 30A between the halogen electrode 22 and the scanning line 1 1 of the front stage. Further, other configurations may be employed, but detailed descriptions thereof will be omitted. Similarly, since the contact (opening) forming process to the scanning line 11 is performed, it is easy to perform static electricity countermeasures by using a conductive material other than the transparent conductive layer or a semiconductor. -41 - (39) 1247158 In the first embodiment, 'the insulating insulating layer of the insulating gate type transistor is formed first, and the second is formed by the formation of the scanning line and the contact (opening) of the electrical connection to the scanning line. The lower level layer is applied to the halftone exposure technology to reduce the number of photo-etching engineering. The transparent conductive pixel electrode is simultaneously anodized to the source and drain wiring, and the surface is provided with an insulating layer. The active substrate is formed by the four mask processes for passivation formation. However, the active substrate can be fabricated by other passivation forming methods. Therefore, the first embodiment will be described. In the second embodiment, as shown in FIG. 3(d) and FIG. 4(d), the selective uranium engraved contact forming process, that is, the second amorphous germanium layer 3 3 A, 3 3 B in the openings 63A, 65A And the first amorphous germanium layer 3 1 A, 3 1 B and the gate insulating layers 30A, 30B are exposed to a portion 73 of each of the scanning lines 11 and a portion 75 of the storage capacitor line 16 in the same manner as in the first embodiment. Manufacturing engineering is carried out. Next, in the entire glass substrate 2, a vacuum film forming apparatus such as SPT is used as the film thickness of 0. 1~0. A transparent conductive layer of about 2 μm is coated, for example, as shown in Fig. 3 (e) and Fig. 4 (e), and the pixel electrode 22 is selectively formed on the glass substrate 2 by a detailed processing technique. At this time, the electrode terminal 5 and the signal line electrode terminal 6 of the scanning line are simultaneously formed in a region outside the image display portion including one portion of the scanning line 73. In the same manner as the conventional example, the short conductive wire 40 of transparent conductivity is provided, and the electrode terminals 5A, 6A and the short-line 40 are formed in an elongated stripe shape, so that the resistance can be increased and the high resistance for static electricity can be obtained. Next, a 42-(40) 1247158 vacuum film forming apparatus such as SPT or the like is used for the formation of the source/drain wiring, and the film layer 34 such as Ti, Ta or the like is used as the film thickness. a heat-resistant metal layer of 1 μπι, and sequentially covering the A1 film layer 35 as a film thickness of 0. Low resistance wiring layer of 3 μm. Further, the source/drain wiring material and the second amorphous germanium layer 3 3 A, 3 3 Β and the first amorphous germanium layer 3 1 A, 3 1 B produced by the two-layer thin film are finely processed. The technique of exposing the gate insulating layer 3 0 A ' 30B by using the photosensitive resin pattern 85, as shown in FIGS. 3(f) and 3(f), includes a part of the pixel electrode 22, and The signal line 12 which also has the source electrode is selectively formed by the layered product of 3 4A and 35A including a portion of the gate electrode 2 1 of the generated insulated gate type transistor and the electrode terminal 6 of the signal line. . The electrode terminal 5A of the scanning line and the electrode terminal 6A of the signal line are source and drain. When the uranium engraving of the wiring 1 2, 2 1 is completed, it can be understood that the glass substrate 2 is exposed. Further, if the resistance is limited, the structure of the source/drain wirings 12, 21 can be simplified, and a single layer of Ta, Cr, MoW or the like can be used. Thus, the active substrate 2 and the color filter obtained by bonding are bonded and liquid-crystallized, and the second embodiment of the present invention is completed. In the second embodiment, since the photosensitive resin pattern 85 is in contact with the liquid crystal, the photosensitive resin pattern 85 does not use a usual photosensitive resin which is a main component of the phenolic hydrogen system, and the transparent component is used as a main component having a high purity. a photosensitive organic insulating layer having a high heat resistance of a resin or a polyimide resin, and may be formed by heating the material to be fluidized, and covering the side surfaces of the source/drain wirings 1 2, 2 1 . In this case, a portion of the liquid crystal substrate is improved with reliability. As for the configuration of the storage capacitor 15, as shown in Fig. 3 (f), the pixel electrode 22 and the storage capacitor line 16 pass through the gate insulating layer 30B and the first amorphous layer. 3 (41) 1247158 3 1 B (not shown) and the second amorphous germanium layer 3 3 B are planarly overlapped (the lower right oblique line portion 5 1 ), but the configuration of the storage capacitor 15 is not limited to this. Alternatively, as in the subsequent embodiment 3, the insulating layer including the gate insulating layer 30A is formed between the scanning line 1A of the preceding stage and the pixel electrode 22. The static electricity countermeasure wire 40 is formed of a transparent conductive layer that is connected to the electrode terminals 5A and 6A. However, since the opening portion to the gate insulating layers 30 A and 30B is formed, other static electricity countermeasures can be taken. On the first embodiment and the second embodiment, the independent transparent conductive pixel electrode is formed, and the active substrate is fabricated by using four masks, but the pixel electrode and the scanning line are formed by processing with one mask. Further, the project is deleted, and since the active substrate can be fabricated by one mask, this will be described as the third embodiment. In the third embodiment, first, on the main surface of the glass substrate 2, a vacuum film forming apparatus such as SPT is used to cover, for example, ITO and a film thickness of 0. 1~0. The first metal layer 92 of a degree of 3 μm is used as a film thickness of 0. 1~0. Transparent conductive layer of 2 μηι 9 1 . Although it is explicitly described below, in the third to fifth embodiments, the scanning line is formed by laminating a transparent conductive layer and a metal layer, and it is impossible to form an insulating layer on the side surface of the scanning line during anodization. The insulating layer is formed by electroplating to form an organic insulating layer, such as a high melting point metal such as Cr, Ta, Mo or the like or an alloy or a metal ruthenium compound as the first metal which does not generate a transparent conductive layer ITO and a battery reaction. The layer acts as a scan line material. If A1 is used for low resistance, a single layer of heat-resistant Al(Nd) alloy or the like is the simplest layer, and secondly, the layering and structure of Ta/Al (Zr, Hf), Ta, Al/Ta are further improved. To be complicated. -44 - (42) 1247158 Next, in the entire glass substrate 2, the first siN layer 30 which becomes the gate insulating layer and the channel which becomes an insulating gate type transistor with almost no impurity are used by the PCVD apparatus. 1 of the amorphous layer 3 1 and the insulating layer of the protective channel formed by the third SiNx layer 32 of the three types of film layers, respectively. 3μτη, 〇. 〇5μπι,Ο. The film thickness of ΐμπι is covered by the thickness. Further, as shown in FIG. 5(a) and FIG. 6(a), the second SiNx layer 32 of the uppermost layer is selectively etched by a fine processing technique to form a protective insulating layer of the insulating gate type transistor (or The second SiNx layer 3 2D formed by etching the cut-off layer or the channel protective layer) exposes the first amorphous germanium layer 31. Further, the PC VD device is used to cover the entire surface of the glass substrate 2 with impurities. The second amorphous layer 33 of the crucible is, for example, 0. After the film thickness of 05 μιη is covered, as shown in Fig. 5 (b) and Fig. 6 (b), the film thickness of the field 82A which also serves as the scanning electrode 1 1 of the gate electrode 1 1 A is compared with the corresponding thickness of 2 μm The pseudo-pixel electrode 93 and the (formed by the lamination of the transparent conductive layer 91A and the first metal layer 92A) are pseudo-electrode terminals 94 and (transparent conductive layer) (formed by lamination of the transparent conductive layer 91A and the first metal layer 92A) The film thickness of the photosensitive resin pattern 82B of the pseudo electrode terminal 95 is formed by laminating the 91C and the first metal layer 92C. The thick photosensitive resin patterns 82A, 82 are formed by a halftone exposure technique, and the photosensitive resin pattern is formed. 82 A and 82B are used as a photomask, and the second amorphous germanium layer 33, the first amorphous germanium layer 3 1, the gate insulating layer 30 and the first metal layer 92 are applied, and the transparent conductive layer 91 is sequentially removed. The glass substrate 2 is exposed. Thus, after obtaining a multilayer film pattern corresponding to the scan line which also serves as the gate electrode 11A and the -45-(43) 1247158 pseudo-pixel electrode 93 and the pseudo-electrode terminals 94, 95, then, if by oxygen plasma When the photosensitive resin patterns 82A and 82B are reduced by Ιμπι or more, as shown in FIGS. 5( c ) and 6 ( c ), the photosensitive resin pattern 82 Β disappears, and the second amorphous layer is exposed. At the same time as the Α3 to 3C, the photosensitive resin pattern 82C of the film can be left as it is. As described above, it is preferable to control the pattern size change, or to predict the resist pattern, in order to improve the anisotropy without reducing the precision of the mask of the source/drain wiring formation, and to improve the anisotropy. The amount of dimensional change is large, and the pattern size of the pre-resist pattern 82A is vigorously designed. Thereafter, as shown in Fig. 6 (c), an insulating layer 76 is formed on the side surface of the gate electrode 1 1 A. For this reason, as shown in FIG. 20, the connection pattern 78 is used to connect the photosensitive resin pattern 82C (78) on the connection pattern 78 by using a connection means such as an alligator clip having a sharp end, and the positive line is given to the scanning line 11. The plus) potential, depending on the composition of the plating solution, can also be given a negative (minus) potential. For example, the plating voltage V is formed to have a value of 0. A 3 μm thick film of polyimine resin layer is used as an organic insulating layer. Since the pseudo-pixel electrode 93 is electrically isolated, the organic insulating layer 76 is not formed around the pseudo-pixel electrode 93. Next, as shown in FIG. 5(d) and FIG. 6(d), the photosensitive resin pattern 82C which is reduced in film is used as a mask, and the second amorphous germanium layer 33A to 33C and the first amorphous layer are sequentially removed. 92A, 92B, and the transparent conductive layers of the transparent conductive layers 91 A to 91C are exposed, and the electrode terminals 5A of the generated scanning lines and the electrode terminals 6A of the pixel electrodes and the signal lines can be obtained. -46 - (44) 1247158 After removing the photosensitive resin pattern 8 2 C, a vacuum film forming apparatus such as SPT is used for forming the source/drain wiring, and a film layer 34 such as Ti or Ta is used as a film. a layer of heat-resistant metal having a thickness of about 1 μm, and a film layer 35 of Α1 is sequentially coated as a film thickness of 0. Low resistance wiring layer with a degree of 3 μχη. Further, the source/drain wiring material and the second amorphous germanium layer 3 3 Α and the first amorphous germanium layer 3 1 A produced by the two-layer thin film are subjected to a fine processing technique to use a photosensitive resin pattern. 8 5 and exposing the gate insulating layer 3 0 A, as shown in FIG. 5(e) and FIG. 6(e), including a part of the pixel electrode 22, and by laminating 34A and 35A, including The gate electrode 2 1 of the insulated gate type transistor and the electrode terminal 6 A of the signal line are formed, and the signal line of the source electrode is selectively formed. When the electrode terminal 5A of the scanning line and the electrode terminal 6A of the signal line are formed by the etching of the source/drain wiring 1 2, 2 1 , it can be understood that the glass substrate 2 is exposed. If the relaxation resistance is limited, the source. The structure of the drain wiring 1 2, 2 1 can be simplified, and can be made into a single layer of Ta, Cr, MoW or the like. Thus, the obtained active substrate 2 and color filter were bonded and the liquid crystal was plated, and the third embodiment of the present invention was completed. In the third embodiment, since the photosensitive resin pattern 85 is in contact with the liquid crystal, the photosensitive resin pattern 85 is connected to the liquid crystal, so that the photosensitive resin pattern 85 does not use the usual sensitivity of the main component of the acetal oxime system. The resin is used as a main component having a high purity, and a photosensitive organic insulating layer having a high heat resistance of a transparent resin or a polyimide resin is used. As for the configuration of the storage capacitor 15 as shown in FIG. 5( e ), the source/drain wirings 1 2 and 2 1 simultaneously include a portion of the pixel electrode 2 2 , and are scanned through the storage electrode 72 and the front portion. The protrusions -47-(45) 1247158 of the line 11 are planarly overlapped by the gate insulating layer 3 Ο A and the first amorphous germanium layer 3 1 A and the second amorphous germanium layer 3 3 B, so that In the example of the configuration (the lower right oblique line portion 5 2 ), the configuration of the storage capacitor 15 is not limited to this, and even between the storage capacitor line 16 and the pixel electrode 21 which are formed at the same time as in the first embodiment, It is formed by an insulating layer including a gate insulating layer 3 OB. The electrostatic countermeasure line 40 is the same as that of the first embodiment and the second embodiment. In the first to third embodiments, the electrode terminal of the scanning line and the electrode terminal of the signal line have the same restriction device structure in which the transparent conductive layer is not formed, but there is also a device capable of releasing the limitation. Description will be made as Embodiment 4 and Embodiment 5. In the fourth embodiment, as shown in FIG. 7(d) and FIG. 7(d), the photosensitive resin pattern 82C which is reduced in film is used as a mask, and the second amorphous germanium layer 33 A to 33C and the first are sequentially removed. The amorphous germanium layers 31 A to 3 1C and the gate insulating layers 30A to 30C and the first metals 92A to 92C expose the transparent conductive layers 91 A to 91C to obtain a portion of the formed scan lines by the respective transparent conductive layers. 5A and the pixel electrode 22 and the signal line electrode terminal 6A are carried out in substantially the same manufacturing process as in the third embodiment. However, it is not necessary to simulate the electrode terminal 95 for the reason described below. Next, in the formation of the source/drain wiring, a vacuum film forming apparatus such as SPT is used, and a film layer 34 such as Ti, Ta or the like is used as the film thickness. a heat-resistant metal layer of 1 μηη, and sequentially covering the A1 film layer 35 as a film thickness of 0. Low resistance wiring layer of 3 μm. Further, the source/drain wiring material and the second amorphous germanium layer 33 and the first amorphous germanium layer 3 1 A produced by the two-layer thin film are made of a photosensitive resin-48- by a detailed processing technique. (46) 1247158 Pattern 8 6 and etch-exposed to expose the gate insulating layer 3 Ο, as shown in FIGS. 7( e ) and 8 ( e ), including a portion of the pixel electrode 22, and by 34A and 3 5 The layer A of the gate electrode selectively forms the gate electrode 2 1 of the insulated gate type transistor and the signal line 12 which also serves as the source electrode, while being formed by the source and drain wirings 1 2, 2 1 simultaneously One portion 5A of the exposed scan line is included, and the formed electrode terminal 6A is simultaneously formed by the scan line electrode terminal 5 and one of the signal lines. That is, it is not necessary to have the electrode terminal 95 as in the third embodiment. The important feature of Embodiment 4 is that the film thickness of the field 86A (black field) on the scanning line 12 at this time is compared with, for example, 3 μm and the gate electrode 21 and the electrode terminals 5, 6 and the field on the storage electrode 72. The photosensitive resin patterns 86A, 86A having a relatively thick film thickness (intermediate adjustment field) are formed in advance by a halftone exposure technique. The minimum size of 86B corresponding to the electrode terminals 5, 6 is a larger number of 10 μm, and it is also extremely easy to manufacture the mask or the precision management of the finished size, but the minimum size of the field corresponding to the scanning line 12 is 86. Since the comparative precision of 4 to 8 μm is high, it is necessary to use a fine pattern as a black field. However, as described in the conventional example, the source/drain wirings 1 2, 21 of the present invention are compared by the one-time exposure processing and the two-etching processing and the formed source/drain wirings 1 2, 2 1 . One-time exposure processing and one-time etching processing are formed, and the variation of the pattern width is less. The size management of the source/drain wirings 12, 21 is also the source/drain wiring 1 2, 2 1 , that is, the channel length Size management is also easy to manage with pattern accuracy by traditional halftone exposure technology. Furthermore, when the size of the channel protective insulating layer 32D is compared with the channel-etched insulating gate type transistor, the ON current of the etch-off type insulated gate type electric type -49 - (47) 1247158 crystal is determined and understood. Due to the source bungee wiring 12, 2 1 inch, process management is more tolerant. 1. After the source/drain wiring is formed, after 1 2, 2 1 , the photosensitive resin pattern 86A ’ 86B is removed by a ashing means such as plasma. When 5 μm or more, as shown in FIG. 7(f) and FIG. 8(f), and when the electrode 21 and the electrode terminals 5, 6 and the storage electrode 72 are overlapped, only the line 1 2 is drawn, and the photosensitive resin pattern can be selectively formed. 86C 'But' In the oxygen plasma treatment described above, when the pattern of the photosensitive resin pattern 86C is thin, the reliability is lowered by exposing the scanning line 12, so that the change in pattern size is controlled. Further, when the limit of the relaxation resistance is used as the structure of the source/drain wirings 1, 2, 21, it can be simplified, and a single layer of Ta, Cr, Mo or the like can be used. Thus, the active substrate 2 and the color filter obtained by bonding are crystallized, and the embodiment 4 of the present invention is terminated. The electrode terminal 5 is made of the same metal material as the scanning line 12, but like the electrode terminal 95 of the embodiment 3, and the photosensitive resin pattern 86 (5), (6), the scanning line 12 contains the pseudo electrode terminal. One of the 95 parts is also easy to have the transparent conductive electrode terminals 5A, 6A. In the case of Example 4, the photosensitive resin pattern 86C is in contact with the liquid crystal. Therefore, the resin pattern 86C is mainly made up of a non-alloy oxime system as a main photosensitive resin, and is used as a main component having a high purity. A photosensitive resin layer having a high heat resistance of a transparent resin or a polyimide resin. Although the structure of the storage capacitor 15 and the phase of the embodiment 3 are connected to each other, the one portion of the scanning line 5A and the signal line 12 are separated by an oxygen-reducing film. The 6 Series introduces the 86B fractal to make the actual sensitization use the same. Transparent-50- (48) 1247158 Conductive pattern 6A (91C) and the transparent conductive layer pattern of the short-line 40 are formed into a slender line shape, so that it can be made into a high-resistance wiring for electrostatic countermeasures, but of course Static countermeasures for other conductive members can be used. In the fourth embodiment of the present invention, the organic insulating layer is formed only on the scanning line 12, and the drain wiring 2 is exposed to retain the conductivity as it is, but the reason for obtaining sufficient reliability here is the driving signal applied to the liquid crystal cell. For basic communication, the DC voltage component is reduced between the counter electrode 14 and the pixel electrode 22 formed on the opposite surface of the color filter, and the voltage of the counter electrode 14 is applied to the image inspection. Since the adjustment (flashing and subtraction adjustment) is performed only on the scanning line 12, an insulating layer can be formed in advance if the DC component is not flowing. Even from the viewpoint of reliability, even if the organic insulating layer is formed on the drain electrode 2 1 as in the third embodiment, there is no problem in forming the organic insulating layer. However, in the TN liquid crystal display device, it is preferable to avoid the gate electrode 21 The non-alignment caused by the height difference is to increase the aperture ratio. In the second embodiment of the present invention, the third embodiment and the fourth embodiment, although the organic insulating layer is selectively formed only on each of the source, drain and signal lines, the manufacturing process is reduced, but the organic insulating layer is Since the thickness system is usually 1 μηι or more, on a high-definition substrate, a honing cloth is used in a small pixel condition, and an alignment treatment is performed on the alignment film, and the height difference causes a non-aligned state. Or the assurance of the precision of the gap of the liquid crystal cell may be hindered. Here, in the fifth embodiment of the present invention, a passivation technique of forming an organic insulating layer is provided with a minimum number of engineering numbers. In the fifth embodiment, as shown in FIG. 9(d) and FIG. 10(d), the photosensitive resin pattern 82C of the minus film-51-(49) 1247158 is used as a mask, and the second amorphous 3 3 is sequentially removed. A to 3 3C and the first amorphous germanium layers 31A to 31C and the gate electrodes 30A to 30C and the first metal 92A to 92C, and the transparent guides 91 A to 91C are exposed, and the transparent conductive layers are obtained to form a scan. The line portion 5A and the pixel electrode 22 and the electrostatic countermeasure line 40 (91C) are carried out in substantially the same manufacturing process as in the fourth embodiment. Thereafter, a vacuum film forming apparatus is used for forming the source/drain wiring, and a thin film layer 34 such as Ti, Ta or the like is used as 0. An anodized heat-resistant metal layer of about 1 μm, and sequentially coated: film layer 35 as a film thickness of 0. An anodized resistor wiring layer of the same degree of 3 μm. Further, the source/germanium wire and the second amorphous germanium layer 3 3 Α and the first amorphous germanium layer 3 1A produced by the two-layer film are processed by the technique, so that the photosensitive resin pattern 8 7 is used. The uranium exposes the gate insulating layer 30, as shown in Fig. 9(e) and Fig. 10(e), which includes a portion of the pixel electrode 22, and the insulating gate formed by the layered formation of 34A and 35A is selectively formed. The drain electrode 2 1 of the polar transistor has a signal line 12 of the source electrode, and the source/drain electrodes 1 2 and 2 1 simultaneously include the exposed scan electrode terminal 5 and the signal line. The formed electrode terminal 6 is formed. The importance of the embodiment 5 is that the field 86A (black field) on the electrode terminals 5, 6 at this time is compared with, for example, 3 μm and the gate electrode 21 and the accumulation electrode 72 in the field 87 Β (mid-tone field) film thickness 1 A photosensitive film pattern 87A, 87, which is thicker than 5 μτη, is formed in advance by a halftone exposure technique. After the source/drain wiring I 2, 2 1 is formed, If one of the electrical layers of the oxygen barrier layer and the low SPT film thickness of 1 A1 are finely engraved, the package • BB , ^ and also a characteristic film thickness of the tree-plasma-52 - (50) 1247158 and other ashing means, the photosensitive resin patterns 87A, 87B are reduced by 1 .  When the photosensitive resin pattern 8 7B disappears, the source/drain wirings 12 and 21 and the storage electrode 72 are exposed, and the photosensitive resin pattern 87C remains as it is only for the electrode terminals 5 and 6. This specially written feature is based on the oxygen plasma treatment described above, and even if the pattern width of the photosensitive resin pattern 87C is thinner, only an anodized layer is formed around the electrode terminals 5, 6 having a large pattern size. The electrical characteristics, yield and quality of the liquid crystal display device are hardly affected. Further, while the photosensitive resin pattern 87C is irradiated with light as a mask, as shown in Fig. 9 (f) and Fig. 10 (f), the source/drain wirings 12, 21 are anodized to form oxide layers 68, 69. After the anodization is completed, after the photosensitive resin pattern 87C is removed, as shown in FIG. 9(g) and FIG. 10(g), the low-resistance film layer 35A of the anodized layer is formed on the side surface thereof to expose the exposed portion. The electrode terminals 5, 6 are formed. On the side of the electrode terminal 5 of the scanning line, it is understood that the high-resistance short-line 40 (9 1 C) for countermeasures against static electricity is flow-anodized, so that it is formed on the side of the anode when compared with the electrode terminal 6 of the signal line. The thickness of the oxide layer is relatively thin. Further, when the structure of the source/drain wirings 1 2, 2 1 is limited by the relaxation resistor 値, the structure can be simplified, and the Ta single layer can be anodized. Thus, the active substrate 2 and the color filter obtained by bonding were bonded to each other to form a liquid crystal substrate, and the fifth embodiment of the present invention was completed. The configuration of the storage capacitor 15 is the same as that of the third embodiment and the fourth embodiment. In the fifth embodiment, when the source/drain wirings 1 2, 21 and the second amorphous germanium layer 3 3 A are anodized, the pixel electrodes 22 which are electrically connected to the drain electrode 2 1 are also exposed. The pixel electrode 22 is also anodized at the same time -53 - (51) 1247158 and is very different from Example 1. Therefore, by forming the film quality of the transparent conductive layer of the pixel electrode 22, the resistance 値 of the anodization is also increased, and in the case where the film formation conditions of the transparent conductive layer are appropriately changed, it is necessary to use the film as an oxygen deficiency in advance. However, the transparency of the transparent conductive layer is not reduced by anodization. Further, the currents for the anodized electrode electrode 21 and the pixel electrode 22 and the accumulation electrode 72 are also supplied through the channel of the insulating gate type transistor, but the area of the pixel electrode 22 is too large, and the current is large. Or it is necessary to make a long time, even if the light is very strong, the resistance of the channel portion becomes an obstacle, and on the drain electrode 2 1 and the accumulation electrode 72, the film quality is the same as that on the signal line 12 The anodized layer 69 of the film thickness not only lengthens the formation time but also corresponds to difficulty. However, even if the anodized layer 69 formed on the gate wiring 2 1 is somewhat incomplete, practically, many obstacles are obtained. The reason is that, as described above, only the signal line 12, the insulating layer can be formed in advance without flowing a direct current component. The liquid crystal display device of the type described above uses a TN type liquid crystal cell, but the pixel electrodes are formed at a certain distance from each other to form a counter electrode and a pixel electrode, even if the ISP (In-Plain) controls the lateral electric field. The liquid crystal display device of the -Swticing type is also useful in the engineering deletion of the proposal of the present invention, and is described in the following examples. In the same manner as in the first embodiment, as in the first embodiment, as shown in FIG. 11 (a) and FIG. 12 (a), the second SiNx layer 32 of the uppermost layer is selectively etched by a detailed processing technique. The first amorphous germanium layer 31 is exposed while forming the second SiNx layer 3 2D formed by the protective insulating layer (or the etch stop layer or the via protective layer) of the insulating gate type transistor. -54- (52) 1247158 Next, using a PC VD device, the entire package of the glass substrate 2, such as the second amorphous layer 3 3 of tantalum, such as 0. After thick coverage of 0 5 μm, as shown in Fig. 11(b) and Fig. i2(1d), the processing is performed to selectively remove the counter electrode 16' which has both the scanning line 11 and the storage capacitor line. The second amorphous germanium layer 3 3 , the first amorphous 31 'the gate insulating layer 30 and the first metal layer 92 are exposed to the glass substrate, and then, as shown in FIG. 12 (b), at the gate electrode 丨丨a An insulating layer 71 is formed on the side of the counter electrode 16. Therefore, as shown in FIG. 21, the wiring 77 of the column-concentrated scanning line 1 1 (the counter electrode 16 is also the same, but shown here) and the peripheral portion of the gas substrate 2 are necessary for electrowinning or polar oxidation. The connection pattern 78 of the potential is applied, and the amorphous germanium layers 31, 33 and the tantalum nitride layers 30, 32 of the plasma CVD are further used as a mask means, and the film formation area 79 is internally connected by the connection pattern 78. And at least there is a need to expose the connection pattern 78. In the connection 78, a connection means having a sharp end of an alligator clip or the like is used, and the connection is applied to the scanning line 11 by electroplating or an anodic oxygen is formed on the insulating layer 76 to form an organic insulating layer or an anodized layer. Next, as shown in FIG. 1 1 (c) and FIG. 12 (c), an opening portion is selectively formed on the scanning line 1 1 and the counter electrode 16 in the field outside the image display portion by a fine technique. 63 A, 65A, etching the second amorphous germanium layer 33A, 33B and the first germanium layers 31A, 31B and the gate insulating layers 30A, 30B in the above portions 63A, 65A to expose a portion 73 of each line 11 and A portion 75 of the counter electrode 16 is provided. Second, in the source. The formation of the bungee wiring is used in engineering

The film that is not covered is finely oriented to the electric sand layer. The electro-optical and stencil is a suitable pattern for the anode, and the vacuum-filming device such as Ti, Ta, etc. is applied to the amorphous opening SPT-55-(53) 1247158. The heat-resistant metal layer having a thickness of about 0.1 μm and the A1 film layer 35 are sequentially coated as a low-resistance wiring layer having a thickness of about 0.3 μm. Further, the source/drain wiring material and the second amorphous germanium layer 3 3 产生 and the first amorphous germanium layer 3 1 A, 3 1 B produced by the two-layer thin film are used by fine processing techniques. The photosensitive resin pattern 86 is etched to expose the gate insulating layers 30 A, 30B, as shown in FIGS. 11(d) and 12(e), including one portion of 22, and by lamination of 34A and 35A, Selectively forming a drain electrode 2 1 of an insulated gate type transistor which also has a generated pixel electrode, and a signal line 12 which also has a source wiring, and includes and forms a source/drain wiring 1 2, A portion 73 of the scanning line which is simultaneously exposed is simultaneously formed by the scanning line electrode terminal 5 and a portion of the signal line. The important feature of the implementation example 6 is that the film thickness of the field 86A on the signal line 12 at this time is thicker than the film thickness of 1.5 μm in the field 86 such as 3 μm and the gate electrode 21 and the electrode terminal 5, 6 The photosensitive resin pattern 86Α' 8 6Β was formed in advance by a halftone exposure technique. After forming the source and the drain wiring 1 2 ' 2 1 , when the photosensitive resin pattern 86A ' 86 is reduced by 1.5 μm or more by the ashing means such as oxygen plasma, the photosensitive resin pattern 86 Β ' is removed. 11(e) and 12(e), while the drain electrode 21 and the electrode terminals 5, 6 are exposed, the photosensitive resin pattern 8 6 C may remain as it is only for the scanning line 1 2 ', but As described in the foregoing embodiment 4, it is preferable that the above-described oxygen plasma treatment is performed, and when the pattern width of the photosensitive resin pattern 86C is thin, the reliability is lowered by exposing the signal line 12, so that the anisotropy is enhanced and the control is controlled. : (54) 1247158 Change in pattern size. Further, the structure of the source/drain wiring 1 2, 2 1 can be simplified by the limitation of the relaxation resistance ,, and it can be simplified as a single layer such as Ta, Cr or MoW. Thus, the active substrate 2 and the color filter obtained by bonding are bonded to the liquid crystal substrate, and the embodiment 6 of the present invention is terminated. On the IPS type liquid crystal display device, it is also apparent from the above description that the active substrate is formed, the transparent conductive pixel electrode 22 is not required, and the transparent conductive layer is not required on the opposite surface of the color filter. The counter electrode 14 is. Therefore, do not use the intermediate conductive layer of the source/drain wiring 1 2, 2 1 . In the case of the example 6, the photosensitive resin pattern 86C is connected to the liquid crystal. Therefore, the photosensitive resin pattern 86 is important as a normal photosensitive resin which does not contain an aldehyde-based system as a main component, and a highly pure main component is used. A photosensitive organic insulating layer containing a transparent resin or a polyimide resin having high heat resistance is used. The structure of the storage capacitor 15 is as shown in Fig. 1 1 (e), and a portion of the pixel electrode (drain wiring) 2 1 also has a counter electrode 16 through the gate insulating layer 30B and the first The amorphous germanium layer 31B and the second amorphous germanium layer 33B are planarly overlapped, and an example of the configuration (lower right oblique line portion 51) is given. In addition, the description of the countermeasure against static electricity is omitted. However, since the opening 63A is provided with a part of the scanning line 1 1 which is exposed, the electrostatic countermeasure is easy. Even in the sixth embodiment, although the organic insulating layer is formed only on the signal line, the manufacturing process is reduced. However, the thickness of the organic insulating layer is usually 1 μm or more, so that the pixel is small on a high-definition substrate. Using a honing cloth, the alignment of the alignment film is caused by a non-alignment 57 (55) 1247158 state. Or the clearance precision of the liquid crystal cell may be impeded. Here, in the seventh embodiment of the present invention, a passivation technique in place of the organic insulating layer is provided with a minimum number of engineering numbers. On the seventh embodiment, as shown in FIG. 13 (c) and FIG. 14 (c), the scan line 1 1 and the counter electrode 16 are selected in the field outside the image display portion by a detailed processing technique. The opening portions 63 A, 65A are formed to etch the second amorphous germanium layer 33 A, 3 3 B and the first amorphous germanium layer 3 1 A, 3 1 B and the gate in the openings 63 A, 65A, respectively. The pole insulating layers 30 A, 30B are exposed to a portion of each of the scanning lines 11 and a portion 75 of the counter electrode 16 in substantially the same manufacturing process as in the sixth embodiment. Next, in the formation of the source/drain wiring, a vacuum film forming apparatus such as SPT is used, and a thin film layer 34 such as Ti or Ta is used as an anodizable heat-resistant metal layer having a thickness of about 0.1 μm, and The A1 film layer 35 is covered as an anodizable low resistance wiring layer having a film thickness of about 0.3 μm. Further, the source/drain wiring material and the second amorphous germanium layer 3 3 A, 3 3 Β and the first amorphous germanium layer 3 1 A, 3 1 B produced by the two-layer thin film are finely processed. The technique is to expose the gate insulating layer 3 0 A, 3 0B by using the photosensitive resin pattern 87, as shown in FIG. 13 (d) and FIG. 13 (d), by the layers of 34A and 35A. a gate electrode 2 1 for selectively forming an insulating gate type transistor of the generated pixel electrode and a signal line 12 also having a source wiring, including and forming the source/drain wiring 12, 21 at the same time A portion 73 of the exposed scan line is formed by the scanning line electrode terminal 5 and a portion of the signal line. The important feature of the implementation example 7 is that the film thickness of the field -58-(56) 1247158 87A on the electrode terminals 5, 6 at this time is compared with the film thickness of 1.5 μm on the wiring of the source and drain electrodes, for example, 3 μm. The thick photosensitive resin pattern 8 7 Α, 87 Β was formed in advance by a halftone exposure technique. When the source/drain wirings 1 2 and 2 1 are formed, when the photosensitive resin pattern 87 Α, 87 Β is reduced by 1.5 μm or more by the ashing means such as oxygen plasma, the photosensitive resin pattern 87 Β disappears and is exposed. At the same time as the source and the drain wiring 1 2, 2 1 , the photosensitive resin pattern 87C can be left as it is only for the electrode terminals 5 and 6. Here, the photosensitive resin pattern 87C is irradiated with light as a mask, and as shown in FIGS. 13(e) and 14(e), the source/drain wirings 1 2, 2 1 are anodized to form an oxide layer 68. After the anodic oxidation is completed, after removing the photosensitive resin pattern 8 7C, as shown in FIGS. 13 (f) and 14 (f), the electrode terminals 5, 6 having the low-resistance film layer 35A are exposed on the side surfaces thereof. . However, in both figures, the electrode terminal 5 connected to the scanning line by the high-resistance member and the electrode terminal 6 of the signal line are not shown in the drawing, so that no anodized layer is formed on the side surface of the electrode terminal 5 of the scanning line. However, the opening portion 63 3 A is easy to provide an electrostatic countermeasure to the portion 7 3 of the scanning line 1 1 that is exposed. Further, the structure of the source/drain wiring 1 2, 2 1 can be simplified by the relaxation of the resistor 値, and it can be used as an anodizable T a single layer. Thus, the active substrate 2 and the color filter obtained by bonding are bonded to the liquid crystal substrate, and the embodiment 7 of the present invention is completed. The configuration of the storage capacitor 15 is the same as that of the embodiment. In the embodiment 6 and the embodiment 7 of the present invention, although the independent scanning is performed, the forming process and the contact forming process of the counter electrode are used to fabricate the active substrate, but the embodiment 1 to the embodiment are implemented. Example 5 The same halftone exposure technique was used to rationalize the contact formation process of the scanning line and the electrical connection of the wires, so that three channels of light were used as the active substrate, and this was exemplified as Example 8 and Example 9. In the sixth embodiment and the seventh embodiment of the present invention, although the active substrate is formed using the cover and the contact forming process, the halftone exposure technique is the same as that of the first embodiment to the fifth embodiment. The contact forming process of rationalizing the formation of the scanning line and the electrical connection of the wire makes it possible to use three channels of light as the active substrate, and this will be described as an embodiment 8 as an example. Even in the eighth embodiment, as in the other embodiments, first, as shown in FIG. 16(a) and FIG. 16(a), the second S iNx layer 3 2 of the uppermost layer is selected by an elaborate processing technique to form an insulating gate. The first amorphous germanium layer 31 is exposed while the second SiNx layer 32D is formed by the electrode type insulating insulating layer (or the etch stop layer or the channel protective layer). Next, using a PCVD apparatus, the second amorphous germanium layer 3 of the glass substrate 2 is, for example, covered with a degree of 0.0 5 μm, as shown in Fig. 15 (b) and Fig. 16 (b). It is to be noted that the film thickness of the opening portions 63A, 65A of the contact region 8 4B is, for example, Ιμπι, which is thicker than the film thickness of the opposite electrode field 84 亦 which corresponds to both the scanning line 11 and the storage capacitor line. Resin pattern 84Α, 4 channels of light can be used to scan the cover. It can be said to sweep the light independently. The scanning cover can be used to make the mouth. Figure 15 The formation of the selective body is formed by the impure film thickness. 16BB, -60-(58) 1247158 is formed by a halftone exposure technique, and the photosensitive resin patterns 84, 824 are used as a mask to sequentially remove the second amorphous germanium layer 3 3, the first amorphous germanium. When the layer 31, the gate insulating layer 30 and the first metal layer 92 are exposed to the glass substrate 2°, when the photosensitive resin patterns 84A and 84B are reduced by 1·5 μm or more by ashing means such as oxygen plasma, As shown in FIG. 15(c) and FIG. 16(c), the photosensitive resin pattern 87Β disappears and is opened at the opening. 63 A exposes the second amorphous germanium layer 33A, and the second amorphous germanium layer 3 3 B is exposed in the opening 65A, and the scanning line 1 1 and the counter electrode 16 6 remain as they are. Photosensitive resin pattern 84 C. Next, as shown in Fig. 16 (c), an insulating layer 76 is formed on the side faces of the gate electrode 1 1 A and the counter electrode 16. Therefore, as shown in FIG. 22, the wiring 77 and the peripheral portion of the gas substrate 2 in which the scanning lines 1 1 (the counter electrodes 16 are the same, but are not shown here) are stacked in parallel, during plating or anodization, It is necessary to give the connection pattern 78 of the potential, and more suitably use the mask layer of the amorphous germanium layer 31, 33 and the tantalum nitride layer 30, 32 by the plasma CVD, and the film formation field 79 is connected by the pattern. 78 is limited to the inner side and at least has to expose the connection pattern 78. The connection pattern 78 is formed by using a connecting means such as an alligator clip having a sharp end, breaking through the photosensitive resin pattern 84C (78) transmitted through the connection pattern 78, applying a potential to the scanning line 11 for electroplating or anodizing, and insulating layer 7 The 6 series forms an organic insulating layer or a layer of an anodized layer. Further, as shown in Fig. 15 (d) and Fig. 16 (d), the film-reducing photosensitive resin pattern 84C is used as a mask, and the opening portion 63A, 65A is -62 - (59) 1247158 2 Amorphous germanium layer 3 3 A, 3 3 B and first amorphous germanium layer 3 1 A ' 3 1 B insulating layers 30A, 30B, and a portion 75 of one of the electrodes 16 of each of the scanning lines 11 is exposed. After the photosensitive resin pattern 8 4 C is removed, a vacuum film forming apparatus such as SPT is used for the formation of the source and the line, and the thin film layer 34 such as i Ta is used as the film thickness of the film thickness ί. The film layer 35 is covered as a low-line layer having a film thickness of about 0.3 μm. Moreover, the source and the drain generated by the two-layer thin film are provided with the second amorphous germanium layer 3 3 A, 8 3 Β and the first amorphous germanium layer 3 1 A, 3 1 Β The resin pattern 8 6 is exposed to the gate insulating layers 30A, 30B, as shown in FIG. 15 (e) and FIG. 16, the layer of the 34A and 35A is laminated to selectively form the generated insulating gate. The drain electrode 2 1 of the type transistor also has a source signal line 12, and includes a portion 73 of the scan line which is formed with the source/drain wiring 1 2, 2 1 by the scan line electrode terminal 5 and the letter A part of the formed electrode terminal 6 is also formed at the same time. Embodiment 8 The film thickness of the field 86A characterized by the signal line 1 at this time is, for example, 3 μm and the electrode surface of the electrode 2, and the electrode film of the electrode terminal 5, 6 is thicker than the film thickness of 1. 5 μm. The resin pattern 86 Α, 86 Β, the hue exposure technique was formed in advance. After the source/drain wiring 1 2, 2 1 is formed, when the photosensitive resin pattern 86 is Α, 86 Β 1.5 μm or more by the ashing means such as oxygen, the photosensitive resin pattern 86 Β disappears, as shown in FIG. 15 and 16(f), the exposed drain electrode 21 and the electrode terminal and the gate and the opposite drain, such as a Ti layer, and the resistance wiring material are exposed by etching (e) the pixel wiring The importance of the line is the same as that of the 86B by the semi-electrical plasma film 丨(f) 5,6 -62- (60) 1247158 at the same time 'only for the scanning line 1 2, the photosensitive resin pattern can be left as it is. 8 6C, but as described above, preferably above the oxygen plasma treatment, when the pattern width of the photosensitive resin pattern 86C is thin, the reliability is lowered by exposing the signal line 12, thereby enhancing the anisotropy and controlling the pattern size. Change. Further, if the relaxation resistance is limited, the structure of the source/drain wirings 12, 21 can be simplified, and it can be used as a single layer of Ta, Cr, MoW or the like. Thus, the active substrate 2 and the color filter obtained by bonding are bonded and liquid crystal substrated, and the eighth embodiment of the present invention is completed. In the eighth embodiment, the photosensitive resin pattern 86C is connected to the liquid crystal. Therefore, the photosensitive resin pattern 86C is mainly made of a general photosensitive resin which does not use an essential component of an aldehyde oxime-based main component, and is mainly composed of a highly pure main component. A photosensitive organic insulating layer having high heat resistance of a transparent resin or a polyimide resin. The structure of the storage capacitor 15 is as shown in Fig. 15 (f), and a portion of the pixel electrode (drain wiring) 21 also serves as a storage capacitor line transmission gate insulating layer 3 0B and a first amorphous layer. 3 1 B and the second amorphous germanium layer 3 3 B are planarly overlapped, and an example of the configuration (lower right oblique line portion 51) is given. Further, the description of the countermeasure against static electricity is omitted, but the opening 63A is a project for exposing a part 73 of the scanning line 1 1 which is exposed, so that the countermeasure against static electricity is easy. With Embodiment 6 and Embodiment 8, there is almost no structural difference in the obtained active substrate 2, and the number of necessary masks is four lanes and three lanes, so it can be predicted compared with the comparative example. 6 The manufacturing method of Example 8 is relatively advanced. Even in the eighth embodiment, although only the signal line is formed by the formation of the organic insulating layer, the thickness of the organic insulating layer is -63 - (61) 1247158, which is usually 1 μm or more, so that the substrate is on a high-definition substrate. In the case of a small picture, the honing cloth is used, and the alignment treatment of the alignment film is performed, and the height difference causes a non-matching state. Or the guarantee of the gap precision of the liquid crystal cell may be hindered. Here, in the ninth embodiment of the present invention, a passivation technique in place of the organic insulating layer is provided with a minimum number of engineering. As shown in FIG. 17 (d) and FIG. 18 (d), the film-reducing photosensitive resin pattern 84C is used as a mask to etch the openings 6 3 A, 6 5 A. 2 an amorphous germanium layer 3 3 A, 3 3 B and first amorphous sand 31A, 31B and gate insulating layers 30A, 30B, exposed to one of the scanning lines and a portion 75 of the counter electrode 16 The manufacturing process was carried out in slightly the same manner as in Example 8. Thereafter, an SPT vacuum film forming apparatus is used in the formation of the source and drain wiring, and a thin film layer 34 such as Ti, Ta or the like is used as a film Ο. μμιι to an anodized heat-resistant metal layer, and The order cover film layer 35 is an anodically anisotropic resistance wiring layer having a film thickness of about 0.3 μm. Further, the source/drain wire and the second amorphous layer 3 3 A, 3 3 Β and the first amorphous layer 3 Μ 3 1 产生 produced by the two-layer film are made by fine processing technology. Exposing the gate insulating layer 3 0 A, 3 0 使用 using the photosensitive resin pattern 8 7 as shown in FIGS. 17( e ) and 18 ( e ), by laminating 3 4 A and 3 5 A a gate electrode 2 1 of an insulating gate type transistor selectively forming a pixel electrode and a signal line 12 also serving as a source wiring, including and forming a source/drain wiring 1 2 while being exposed One portion of the scanning line 73, the electrode terminal 6 is also formed at the same time by a portion of the signal line of the scanning line electrode terminal 5. Embodiment 9 re-directs the barrier layer 11 to an equal thickness A1, and the pattern 2 1 and the -64-(62) 1247158 are characterized by the field 87 A of the electrode terminals 5, 6 at this time. The film thickness is formed in advance by a halftone exposure technique as compared with a photosensitive resin pattern 87 A, 87 which is thicker than a film thickness of 1.5 μm on the source/drain wiring. When the source/drain wirings 1 2 and 2 1 are formed, when the photosensitive resin patterns 87A and 87B are reduced by 1.5 μm or more by ashing means such as oxygen plasma, the photosensitive resin pattern 87 Β disappears and is exposed. At the same time as the source and drain electrodes 1 2 and 2 1 , the photosensitive resin pattern 87C can be left as it is only for the electrode terminals 5 and 6. When the photosensitive resin pattern 87C is irradiated with light as a mask, as shown in FIG. 17 (f) and FIG. 18 (f), the source and drain wirings 12, 21 are anodized to form an oxide layer 68, 69. . After the anodization is completed, after the photosensitive resin pattern 87C is removed, as shown in Fig. 17 (g) and Fig. 18 (g), the electrode terminals 5, 6 having the low-resistance film layer 35A are exposed on the side surfaces thereof. However, in both figures, the electrode terminal 5 connected to the scanning line by the high-resistance member and the electrode terminal 6 of the signal line are not shown in the drawing, so that no anodized layer is formed on the side surface of the electrode terminal 5 of the scanning line. However, the opening 63A is easy to apply to the portion 73 of the scanning line 11 which is exposed. Further, the structure of the source/drain wiring 1 2, 21 can be simplified by the relaxation of the resistor 値, and a single layer of Ta, Cr Å Mo or the like can be used. Thus, the active substrate 2 and the color filter obtained by bonding were bonded to each other to form a liquid crystal substrate, and the seventh embodiment of the present invention was completed. The configuration of the storage capacitor 15 is the same as that of the embodiment. By the embodiment 7 and the embodiment 9', the active substrate 2 - 65 - (63) 1247158 obtained is almost no structural difference, and the number of necessary masks is 4, 3, respectively. The prediction is more advanced than the manufacturing method of Example 9 of Comparative Example 7. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a plan view showing a semiconductor device for a display device according to a first embodiment of the present invention. Fig. 2 is a cross-sectional view showing the manufacturing process of the semiconductor device for a display device according to the first embodiment of the present invention. Fig. 3 is a plan view showing a semiconductor device for a display device according to a second embodiment of the present invention. Fig. 4 is a cross-sectional view showing the manufacturing process of a semiconductor device for a display device according to a second embodiment of the present invention. Fig. 5 is a plan view showing a semiconductor device for a display device according to a third embodiment of the present invention. Fig. 6 is a cross-sectional view showing the manufacturing process of a semiconductor device for a display device according to a third embodiment of the present invention. Fig. 7 is a plan view showing a semiconductor device for a display device according to a fourth embodiment of the present invention. Figure 8 is a cross-sectional view showing the manufacturing process of a semiconductor device for a display device according to a fourth embodiment of the present invention. Figure 9 is a plan view showing a semiconductor device for a display device according to a fifth embodiment of the present invention. Figure 10 is a cross-sectional view showing the manufacturing process of a semiconductor device -66-(64) 1247158 for a display device according to a fifth embodiment of the present invention. Figure 11 is a plan view showing a semiconductor device for a display device according to a sixth embodiment of the present invention. Figure 12 is a cross-sectional view showing the manufacturing process of a semiconductor device for a display device according to a sixth embodiment of the present invention. Figure 13 is a plan view showing a semiconductor device for a display device of Embodiment 7 of the present invention. Figure 14 is a cross-sectional view showing the manufacturing process of a semiconductor device for a display device according to a seventh embodiment of the present invention. Figure 15 is a plan view showing a semiconductor device for a display device according to Embodiment 8 of the present invention. Figure 16 is a cross-sectional view showing the manufacturing process of a semiconductor device for a display device according to Embodiment 8 of the present invention. Figure 17 is a plan view showing a semiconductor device for a display device according to a ninth embodiment of the present invention. Figure 18 is a cross-sectional view showing the manufacturing process of a semiconductor device for a display device according to a ninth embodiment of the present invention. Fig. 19 is a layout view showing a connection pattern formed in the insulating layers of the first embodiment and the second embodiment. Fig. 20 is a layout view showing a connection pattern formed by the insulating layers of the third embodiment, the fourth embodiment, and the fifth embodiment. Fig. 21 is a layout view showing a connection pattern formed in the insulating layers of the sixth embodiment and the seventh embodiment. Fig. 22 is a layout view showing a pattern of connection of -67-(65) 1247158 formed in the insulating layers of Example 8 and Example 9. Figure 23 is a perspective view showing a mounted state of a liquid crystal substrate. Fig. 24 is an equivalent circuit diagram showing a liquid crystal substrate. Fig. 25 is a key sectional view showing a liquid crystal substrate. Figure 26 is a cross-sectional view showing a conventional substrate of a conventional example. Figure 27 is a cross-sectional view showing the manufacturing process of a conventional substrate of a conventional example. Figure 28 is a cross-sectional view showing the rationalized active substrate. Figure 29 is a cross-sectional view showing the manufacturing process of a rationalized active substrate. DESCRIPTION OF REFERENCE NUMERALS 1 liquid crystal substrate 2·active substrate (glass substrate) 3 semiconductor integrated circuit wafer 4...TCP film 5··. electrode terminal of scanning line, part of scanning line 6 ··.The electrode terminal of the signal line, one part of the signal line 9...Color filter (opposite glass substrate)...Insulated gate type transistor 1 1...Scanning line (gate electrode) nA···( Gate wiring, gate electrode) 1 2... Signal line (source wiring, source electrode) 16... Common capacitance line (for the opposite electrode among IPS type electrodes) 1 7... Liquid crystal 1 9... Polarizer-68 - (66) (66) 1247158 20.. . Alignment film 21..... 汲 electrode (for PIC type electrode as a pixel electrode) 22··· (transparent conductivity) pixel electrode 3 0, 3 0A, 3 0B, 3 0C··. Gate insulating layer (1st SiNx layer) 3 1,3 1 A,3 1 B, 3 1C·.· (excluding impurities) 2nd amorphous germanium layer 32 , 32A, 32B, 32C··· 2nd SiNx layer 32D... channel protection insulating layer (etching cut-off layer) 3 3, 3 3 A, 33 B, 3 3 C.·. (including impurities) 2nd non- Crystalline layer 34, 34A···(anodable) heat resistant metal Layer 34, 34A.. (anodable) low-resistance metal layer (A1) 3 6, 3 6A... (anodable) intermediate conductive layer 3 7...passivation insulating layer 50, 51, 52 ...the storage area 62·.· (on the drain electrode) the opening 63, 63A... (on the scanning line) the opening 6 4, 64 A... (on the signal line) the opening 65, 6 5 A.·· (on the counter electrode) the opening portion 6 6...the yttrium oxide layer containing the impurity 6 8...the anodized layer (titanium oxide, 1^02) 69··. the anodized layer (alumina , Al2〇3) 7 0... anodized layer (pentaoxide giant, Ta205) 72.. . accumulation electrode 73... one part of the scanning line 7 4 ... one part of the signal line -69- (67) 1247158 7 6 ...the insulating layers 81A, 81B, 82A, 82B, 84A, 84B, 87A, 87B formed on the side of the scanning line (formed by halftone exposure) photosensitive resin patterns 8 3 A... a photosensitive resin pattern formed by a plain electrode 8 5... photosensitive organic insulating layer 8 6 A, 8 6 B... (formed by halftone exposure) photosensitive organic insulating layer 91.. transparent conductive layer 92. .1st metal layer

Claims (1)

(1) 1247158 Pickup, Patent Application No. 1 · A liquid crystal display device is a main gate type transistor, and also serves as a scanning line of the insulating gate pole and a pixel electrode which also serves as a signal wiring of the source wiring And the unit pixel is configured to be a transparent insulating substrate, and a liquid crystal display device formed by color filtering of the second transparent insulating substrate facing the plate; the feature is at least the first transparency. The insulating base is composed of one or more first metal layers and is formed on the scan line; on the scan line, one layer is formed on the gate insulating layer on the gate electrode, and no layer is formed as an island; a protective insulating layer on the first semiconductor layer; a pair of regions outside the second display portion including the impurity on the conductor layer of the protective insulating layer; and a gate on the scan line to expose a portion of the scan line; a source formed by a metal layer having a oxidized metal layer and containing a refractory metal layer on the second half of the insulating substrate (the signal line includes the first and the same scanning line around the opening and the opening) a terminal; forming a transistor on the signal line on the surface of the drain 1 transparent insulating substrate; forming a transparent conductive image display portion; and having at least an insulating transistor on a surface overlapping the pixel electrode of the drain wiring a gate electric wire, and a first transparent insulating substrate connected to the matrix of the two-dimensional matrix of the drain, filling one main surface of the liquid crystal panel to form a gate insulating layer having an insulating layer on the side; The first semiconductor is formed on the upper portion of the gate electrode and the first semi-semiconductor layer; in the image edge layer, the first conductor layer is formed on the opening conductor layer and the first layer is permeable to the first layer, and the second layer is provided. The semiconductor layer forms part of the wiring and the first pixel electrode, in the field of the electrode end where the conductivity is drawn, and the electrode terminal area of the signal line -71 - (2) (2) 1247158, at the source 汲On the surface of the pole wiring, an anodized layer is formed. The liquid crystal display device is a scanning line having at least an insulating gate type transistor and a gate electrode of the insulating gate type transistor, and also serves as a signal for the source wiring. a line, a unit pixel of a pixel electrode connected to the drain wiring, and the like, a first transparent insulating substrate arranged in a two-dimensional matrix, and a second transparent surface opposite to the first transparent insulating substrate A liquid crystal display device in which a liquid crystal is filled between a transparent insulating substrate or a color filter; and the first metal layer is formed of one or more layers on at least one main surface of the first transparent insulating substrate. a scanning line having an insulating layer on a side surface thereof, and an electrode terminal of a transparent conductive pixel electrode and a signal line; forming one or more gate insulating layers on the scanning line; and a gate electrode on the gate electrode a first semiconductor layer containing no impurities is formed in an island shape on the insulating layer; a protective insulating layer thinner than the gate electrode is formed on the first semiconductor layer; and a portion of the protective insulating layer is on the first semiconductor layer ,shape a pair of second semiconductor layers including impurities; in the region outside the image display portion, an opening portion is formed in the gate insulating layer on the scanning line to expose a portion of the scanning line; and the first and the third portions including the opening portion and the opening portion are included (2) The semiconductor layer forms a transparent conductive scan line electrode terminal; and the first transparent insulating substrate and the electrode terminal of the signal line include a heat resistant metal layer on the second semiconductor layer to form one or more layers. The source (signal line) formed by the second metal layer is formed on the second semiconductor layer and on the first transparent insulating substrate, and is formed on the -72-(3) 1247158 portion of the pixel electrode. Polar wiring; a photosensitive organic insulating layer is formed on the source/drain wiring. 3 - A liquid crystal display device having at least an insulating gate type transistor on a main surface, and a scanning line which also serves as a gate electrode of the insulating gate type transistor, and also serves as a signal line of the source wiring And the first transparent insulating substrate in which the unit pixels connected to the pixel electrodes of the drain wiring and the like are arranged in a two-dimensional matrix, and the second transparency opposite to the first transparent insulating substrate a liquid crystal display device in which a liquid crystal is filled between an insulating substrate or a color filter; and is characterized in that a layer of a transparent conductive layer and a first metal layer is formed on at least one main surface of the first transparent insulating substrate a scanning line composed of an insulating layer and an electrode terminal of a transparent conductive pixel and a signal line on the side surface thereof; one or more gate insulating layers are formed on the scanning line; and a gate electrode is formed on the gate electrode a first semiconductor layer containing no impurities on the pole insulating layer is formed in an island shape; a protective insulating layer thinner than the gate electrode is formed on the first semiconductor layer; and a first semiconductor layer is formed on a portion of the protective insulating layer Forming a pair of second semiconductor layers containing impurities; removing the gate insulating layer and the first metal layer on the scanning line in a field outside the image display portion, and exposing the transparent conductive layer formed by the electrode terminals of the scanning lines; On the second semiconductor layer and the first transparent insulating substrate, a part of the electrode terminal of the signal line includes a source line (signal line) including a refractory metal layer and a second metal layer of ±1. In the second year: on the conductor layer and on the first transparent insulating substrate, a drain wiring is formed on the portion of the pixel electrode, and -73-(4) 1247158 is formed on the source/drain wiring. Photosensitive organic insulating layer. 4. A liquid crystal display device having at least an insulating gate type transistor on a main surface, and a scanning line which also serves as a gate electrode of the insulating gate type transistor, and a signal line which also serves as a source wiring. a first transparent insulating substrate in which a unit pixel connected to a pixel electrode of a drain wiring or the like is arranged in a two-dimensional matrix, and a second transparent insulating substrate facing the first transparent insulating substrate Or a liquid crystal display device in which a liquid crystal is filled between color filters; characterized in that at least one of the transparent surfaces of the first transparent insulating substrate is formed by laminating a transparent conductive layer and a first metal layer. a scanning line and a transparent conductive pixel electrode having an insulating layer on a side surface thereof; forming one or more gate insulating layers on the scanning line; and not containing impurities on the gate insulating layer on the gate electrode The first semiconductor layer is formed in an island shape; a protective insulating layer having a finer gate electrode is formed on the first semiconductor layer; and a pair of impurities is formed on the first semiconductor layer on a portion of the protective insulating layer a second semiconductor layer; a transparent conductive layer that removes a part of the scanning line from the gate insulating layer and the first metal layer in the field outside the image display portion; and the first transparency on the second semiconductor layer a source wiring (signal line) including a second metal layer including one or more refractory metal layers on the insulating substrate, and a portion of the electrode terminal of the signal line, and the first transparent layer on the second semiconductor layer On the insulating substrate, a portion of the pixel electrode and the scanning line are similarly formed to form the same scanning line electrode terminal, and the field outside the image display portion is formed by a part of the signal line. Signal line -74- (5) 1247158 Electrode terminal; a photosensitive organic insulating layer is formed on the signal line except for the electrode terminal of the signal line. 5.  A liquid crystal display device having at least an insulating gate type transistor on a main surface, and a scanning line which also serves as a gate electrode of the insulating gate type transistor, and a signal line which also serves as a source wiring, and a connection The first transparent insulating substrate in which the unit pixel of the pixel electrode or the like of the drain wiring is arranged in a two-dimensional matrix, and the second transparent insulating substrate facing the first transparent insulating substrate or a liquid crystal display device in which a liquid crystal is filled between color filters; and is characterized in that at least one main surface of the first transparent insulating substrate is formed by laminating a transparent conductive layer and a first metal layer. a scan line having an insulating layer on the side thereof and a transparent conductive pixel electrode; forming one or more gate insulating layers on the scan line; and not containing impurities on the gate insulating layer on the gate electrode a semiconductor layer is formed in an island shape; a protective insulating layer having a finer gate electrode is formed on the first semiconductor layer; and a pair of impurities is formed on a portion of the protective insulating layer and the first semiconductor layer a semiconductor layer; in a field outside the image display portion, a gate insulating layer and a first metal layer on the scanning line are removed to expose a portion of the transparent conductive layer of the scanning line; and the first transparent insulating substrate is formed on the second semiconductor layer a source wiring (signal line) composed of one or more layers of anodizable metal layers, and a portion of the protective insulating layer and the first transparent layer are insulated from the first transparent layer On the substrate and a portion of the pixel electrode, the same electrode wiring and one of the scanning lines are formed to form the electrode terminal of the scanning line, and the field is -75-(6) (6)1247158 outside the display portion. An electrode terminal for forming a signal line composed of one portion of the signal line; and an anode oxide layer formed on the source/drain wiring except for the electrode terminal of the signal line. 6.  A liquid crystal display device having at least an insulating gate type transistor on a main surface, and a scanning line which also serves as a gate electrode of the insulating gate type transistor, and a signal line which also has a source wiring, and a pixel element connected to the drain electrode of the insulating gate type transistor, and a unit pixel of a counter electrode formed by a specific distance from the pixel electrode, and the first pixel is arranged in a two-dimensional matrix. a liquid crystal display device in which a liquid crystal display device is filled between a second insulating insulating substrate or a color filter that faces the first transparent insulating substrate, and is characterized by at least a first transparency. One main surface of the insulating substrate is formed with a scanning line and a counter electrode which are composed of one or more first metal layers and have an insulating layer on the side surface thereof; one or more layers are formed on the scanning line and the counter electrode. a gate insulating layer; the first semiconductor layer containing no impurities is formed in an island shape on the gate insulating layer on the gate electrode; and a thinner protective insulating layer is formed on the first semiconductor layer; The aforementioned protection a pair of insulating layers are formed on the first semiconductor layer to form a pair of second semiconductor layers containing impurities; and in the field outside the image display portion, an opening is formed in the gate insulating layer on the scanning line to expose a portion of the scanning line; a source (signal line) and a drain line (pixel electrode) formed of a second metal layer of one or more layers on the second transparent layer and the first transparent insulating substrate; The electrode-76-(7)(7)1247158 terminal including the scanning line and the first and second semiconductor layers around the opening is formed in the field outside the image display portion, and is formed by a part of the signal line. An electrode terminal of the signal line formed; a photosensitive organic insulating layer is formed on the signal line except for the electrode terminal of the signal line. 7.  a liquid crystal display device having at least an insulating gate type transistor on a main surface, and a scanning line which also serves as a gate electrode of the insulating gate type transistor, and a signal line which also serves as a source wiring. And a pixel element connected to the drain electrode of the insulating gate type transistor, and a unit pixel of a counter electrode formed by a specific distance from the pixel electrode, and the like, are arranged in a two-dimensional matrix. a liquid crystal display device in which a transparent insulating substrate and a second transparent insulating substrate or a color filter opposed to the first transparent insulating substrate are filled with a liquid crystal; the feature is at least first transparent One of the main surfaces of the insulating substrate is formed of a scanning line and a counter electrode which are composed of one or more first metal layers and have an insulating layer on the side surface thereof; one or more layers are formed on the scanning line and the counter electrode. a gate insulating layer; the first semiconductor layer containing no impurities is formed in an island shape on the gate insulating layer on the gate electrode; and a protective insulating layer thinner than the gate electrode is formed on the first semiconductor layer; In the foregoing a pair of insulating layers are formed on the first semiconductor layer to form a pair of second semiconductor layers containing impurities; in the field outside the image display portion, an opening portion is formed on the gate insulating layer on the scanning line to expose a portion of the scanning line; A source wiring (signal line) and a drain wiring (pixels) formed of one or more layers of anodizable metal layers are formed on the second transparent layer and the first transparent insulating substrate. And an electrode terminal including the -77-(8) (8) I247158 scanning line in the same manner as the first and second semiconductor layers including the opening and the periphery of the opening, and a signal is formed in a field outside the image display portion An electrode terminal of a signal line formed by one of the wires; an anodized layer is formed on the source/drain wiring except for the electrode terminal of the signal line. 8.  The liquid crystal display device according to the first aspect of the invention, wherein the insulating layer formed on the side of the scanning line is the liquid crystal display device according to the first aspect, the second item, the third item, the fourth item, the fifth item, the sixth item or the seventh item Organic insulation layer. 9.  The liquid crystal display device according to the first aspect, wherein the first metal layer is formed of an anodizable metal and is formed on the side of the scanning line. The layer is an anodized layer. 10.  A method of manufacturing a liquid crystal display device is characterized in that a main surface has a scan line having at least an insulating gate type transistor and also serving as a gate electrode of the insulating gate type transistor, and also serves as a source wiring. a signal line, a first transparent insulating substrate in which a unit pixel connected to a pixel electrode of the drain wiring or the like is arranged in a two-dimensional matrix, and a second transparency opposite to the first transparent insulating substrate A method of manufacturing a liquid crystal display device in which a liquid crystal is filled between an insulating substrate or a color filter, characterized in that it is at least one of the main surfaces of the first transparent insulating substrate, and has one or more layers in sequence. a first metal layer and a gate insulating layer of 1 or more layers and a first amorphous germanium layer and a protective insulating layer containing no impurities; and a protective insulating layer selectively forming a channel protective layer of the insulating gate type transistor 'The work of exposing the first amorphous germanium layer; and the work of covering the second amorphous sand layer containing impurities; and the field corresponding to the scanning line, which is shown in the image-78-(9) (9)1247158 Forming a scan line Forming a photosensitive resin pattern having a thinner film thickness in the field than other fields; and sequentially etching the second amorphous germanium layer and the first amorphous germanium layer by using the photosensitive resin pattern as a mask Engineering of the gate insulating layer and the first metal layer; and engineering for reducing the film thickness of the photosensitive resin pattern to expose the second amorphous germanium layer in the field of contact formation; and engineering for forming an insulating layer on the side of the scanning line And a process of etching the photosensitive resin pattern having the film thickness as a mask, etching the second amorphous germanium layer and the first amorphous germanium layer and the gate insulating layer in the contact region to expose a portion of the scan line; After the refractory metal layer is covered and covers one or more layers of the anodizable metal layer, a source (signal line) and a drain are formed to overlap the portion of the protective insulating layer, and a scan line electrode including a portion of the scan line is formed. a process of forming a terminal; and forming a transparent conductive pixel electrode on a portion of the first transparent insulating substrate and the drain wiring, forming a signal line on a signal line outside the image display portion a conductive terminal for forming a transparent conductive electrode terminal on an electrode terminal of the scanning line; and a photosensitive resin pattern for forming a selective pattern of the pixel electrode and the electrode terminal as a mask The transparent conductive electrode and the transparent conductive electrode terminal are simultaneously protected from the source and the drain wiring. 11.  A method of manufacturing a liquid crystal display device, comprising: at least an insulating gate type transistor on a main surface, and a scanning line which also serves as a gate electrode of the insulating gate type transistor, and also serves as a signal line of the source wiring And the unit pixel of the pixel electrode connected to the drain wiring is arranged in a two-dimensional matrix of the first transparent insulating substrate, and the first transparent insulating material - 79-(10) (10) 1247158 a method for manufacturing a liquid crystal display device in which a liquid crystal display device is filled between a second transparent insulating substrate or a color filter of a substrate, and is characterized in that it is at least one main surface of the first transparent insulating substrate and has The process of covering the first metal layer of one or more layers and the gate insulating layer of one or more layers and the first amorphous sand layer and the protective insulating layer containing no impurities; and selectively forming channel protection as an insulating gate type transistor a protective insulating layer of the layer to expose the first amorphous germanium layer; and a second amorphous germanium layer covering the impurity; and a contact formation field in which a scan line is formed in a field outside the image display portion corresponding to the scanning line Upper film a project of a photosensitive resin pattern which is thinner than other fields; and the urethane engraving of the second amorphous sand layer and the first amorphous sand layer and the gate insulating layer and the first metal by using the photosensitive resin pattern as a mask Engineering of the layer; and reducing the film thickness of the photosensitive resin pattern to expose the second amorphous germanium layer in the field of contact formation; and the process of forming an insulating layer on the side of the scanning line; and reducing the film thickness The photosensitive resin pattern serves as a mask for etching a portion of the scanning line by etching the second amorphous germanium layer and the first amorphous germanium layer and the gate insulating layer in the contact region; and the first transparent insulating substrate a process of forming a transparent conductive pixel electrode and an electrode terminal of a signal line and a scanning line electrode terminal including a portion of the scanning line; and a second metal layer including a heat resistant metal layer and covering one or more layers a portion of the electrode terminal of the signal line is included in a manner partially overlapping the protective insulating layer, and a source wiring (signal line) having a photosensitive organic insulating layer is formed on the surface thereof. Works with a drain wiring that also includes a portion of a pixel electrode and a photosensitive organic insulating layer on its surface. -80- (11) 1247158 1 2 - A method of manufacturing a liquid crystal display device having at least an insulating gate type transistor on a main surface and a gate electrode also serving as the insulating gate type transistor a line, a signal line that also serves as a source line, and a first transparent insulating substrate in which a unit pixel such as a pixel electrode connected to the drain wiring is arranged in a two-dimensional matrix, and A method for manufacturing a liquid crystal display device in which a liquid crystal display device is filled between a second transparent insulating substrate or a color filter of a transparent insulating substrate, and is characterized in that it is at least one main surface of the first transparent insulating substrate And having: sequentially covering the transparent conductive layer and the first metal layer and one or more gate insulating layers and the first amorphous germanium layer and the protective insulating layer containing no impurities; and selectively forming as an insulating gate type a protective layer of a channel protective layer of the transistor to expose the first amorphous germanium layer; and a process of covering the second amorphous germanium layer containing the impurity; and corresponding to the scan line and the pixel electrode and the scan line Electrode end of signal line In the field of the pixel electrode and the outside of the image display portion, a process of forming a photosensitive resin pattern having a thinner film thickness in the field of forming the electrode terminal of the scanning line and the signal line than in other fields; and using the photosensitive resin pattern as the a mask, and sequentially engraving the second amorphous germanium layer and the first amorphous germanium layer and the gate insulating layer, and the first metal layer and the transparent conductive layer; and reducing the film thickness of the photosensitive resin pattern, And exposing the second amorphous germanium layer on the surface of the pixel electrode and the electrode terminal of the scan line and the signal line; and forming an insulating layer on the side of the scan line; and the photosensitive resin which reduces the film thickness The pattern is used as a mask to form a second amorphous germanium layer and a first amorphous germanium layer and a gate insulating layer and a first metal layer on the pixel electrode and the electrode terminals of the scan line and the signal line. (12) (12) 1247158, the project of exposing the transparent conductive pixel electrode and the electrode terminal of the scanning line and the electrode terminal of the signal line; and the second metal layer including the heat resistant metal layer and covering one or more layers, and The aforementioned protection The edge layer partially overlaps to form a portion of the electrode terminal including the signal line, and the source wiring (signal line) having the photosensitive organic insulating layer on the surface thereof, and the portion including the pixel electrode, and the surface thereof Engineering of a drain wiring having a photosensitive organic insulating layer. 13.  A method of manufacturing a liquid crystal display device having a gate electrode having at least an insulating gate type on a main surface and a gate electrode of the insulated gate type transistor, and a signal also serving as a source wiring a line, a first transparent insulating substrate in which a unit pixel connected to a pixel electrode of a drain wiring or the like is arranged in a two-dimensional matrix, and a second transparency opposite to the first transparent insulating substrate A method for manufacturing a liquid crystal display device in which a liquid crystal is filled between an insulating substrate or a color filter, characterized in that it is at least one main surface of the first transparent insulating substrate, and has a step of sequentially covering the transparent conductive layer and a first metal layer and a gate insulating layer of 1 or more layers and a first amorphous germanium layer and a protective insulating layer containing no impurities; and a protective insulating layer selectively forming a channel protective layer of the insulating gate type transistor And exposing the first amorphous germanium layer; and covering the second amorphous germanium layer containing the impurity; and the electrode terminals corresponding to the scan line and the pixel electrode and the scan line and the signal line on the pixel electrode And painting In the field outside the display portion, a process of forming a photosensitive resin pattern having a film thickness thinner than other fields in the field of forming an electrode terminal of a scanning line; and reducing a film thickness of the photosensitive resin pattern to expose a pixel electrode and scanning Electrode end of the wire • 82- (13) (13) 1247158 Engineering of the second amorphous germanium layer in the sub-formation field, and the formation of an insulating layer on the side of the scanning line; and the sensitivity of reducing the film thickness The resin pattern serves as a mask to etch the second amorphous germanium layer and the first amorphous germanium layer and the gate insulating layer and the first metal layer on the pixel electrode and the electrode terminal of the scanning line, thereby exposing the transparent conductivity a part of the pixel electrode and the scanning line; and a second metal layer including the heat resistant metal layer and covering one or more layers, and partially overlapping the protective insulating layer, corresponding to the source wiring (handle line) 'A sample including a drain wiring of one of the pixel electrodes* and an electrode terminal including a scanning line of a portion of the scanning line, and a portion of the signal line formed outside the image display portion The electrode terminal of the signal line forms a pattern of a photosensitive organic insulating layer pattern having a thicker thickness on the signal line than other fields; and selectively removing the second metal layer by using the photosensitive organic insulating layer pattern as a mask 2 an amorphous germanium layer and a first amorphous germanium layer, forming a source/drain wiring and an electrode terminal of the scanning line and the signal line; and reducing a film thickness of the photosensitive organic insulating layer pattern to expose a bungee Engineering of wiring and electrode terminals of scanning lines and signal lines. 14.  A method of manufacturing a liquid crystal display device, comprising: at least an insulating gate type transistor on a main surface, and a scanning line which also serves as a gate electrode of the insulating gate type transistor, and also serves as a signal line of the source wiring And a first transparent insulating substrate in which a unit pixel connected to a pixel electrode of the drain wiring or the like is arranged in a two-dimensional matrix, and a second transparent insulating substrate facing the first transparent insulating substrate Or a method of manufacturing a liquid crystal display device in which a liquid crystal is filled between liquid filters, -83-(14) 1247158 is characterized in that it is at least one main surface of the first transparent insulating substrate, and has: Covering the transparent conductive layer and the first metal layer and the gate insulating layer of one or more layers and the first amorphous germanium layer and the protective insulating layer containing no impurities; and selectively forming the channel protection of the insulating gate type transistor a protective insulating layer of the layer to expose the first amorphous germanium layer; and a process of covering the second amorphous germanium layer containing the impurity; and an electrode terminal corresponding to the scan line and the pixel electrode and the scan line, in the pixel On the electrode In the field outside the image display portion, a process of forming a photosensitive resin pattern having a thinner film thickness in the field of electrode terminal formation of the scanning line than in other fields is formed; and the photosensitive resin pattern is used as a mask, and the foregoing is sequentially engraved 2 an amorphous germanium layer and a first amorphous germanium layer and a gate insulating layer and a first metal layer and a transparent conductive layer; and reducing a film thickness of the photosensitive resin pattern to expose a pixel electrode and a scan line The electrode terminal is formed in the field of the second amorphous germanium layer; and the insulating layer is formed on the side of the scan line; and the photosensitive resin pattern having the reduced film thickness is used as a mask to etch the pixel electrode and the scan line The second amorphous germanium layer and the first amorphous germanium layer and the gate insulating layer and the first metal layer in the field of forming the electrode terminal, and exposing a portion of the transparent conductive pixel electrode and the scanning line; and After the refractory metal layer covers one or more layers of the anodizable metal layer, it partially overlaps the protective insulating layer, and corresponds to the source wiring (signal line)' and the pixel-containing pixel electrode a portion of the drain wiring, the electrode terminal including the scanning line of one of the scanning lines, and the signal line electrode terminal formed by a portion of the signal line outside the image display portion, forming electrodes of the scanning line and the signal line Projection of a photosensitive resin pattern having a thicker film thickness on the terminal than other fields; -84- (15) (15) 1247158 and selectively removing the anodizable metal layer by using the photosensitive resin pattern as a mask The second amorphous germanium layer and the first amorphous germanium layer form a source/drain wiring and an electrode terminal of the scanning line and the signal line; and the film thickness of the photosensitive resin pattern is reduced to expose the source. Engineering of electrode wiring of the drain wiring and the scanning line and the signal line; and engineering for protecting the source electrode and the drain wiring at the same time as the electrode terminal. 15.  A method of manufacturing a liquid crystal display device having at least an insulating gate type transistor on a main surface, and a scanning line which also serves as a gate electrode of the insulating gate type transistor, and also serves as a source wiring signal a line, and a pixel electrode connected to the drain electrode of the insulating gate type transistor, and a unit pixel of a counter electrode formed by a specific distance from the pixel electrode, etc., are arranged in a two-dimensional matrix a method for manufacturing a liquid crystal display device in which a transparent insulating substrate and a second transparent insulating substrate or a color filter opposed to the first transparent insulating substrate are filled with liquid crystal are characterized by at least On one main surface of the first transparent insulating substrate, the first metal layer and one or more gate insulating layers and the first amorphous germanium layer and the protective insulating layer containing no impurities are sequentially covered. And a process of selectively forming a protective insulating layer of the channel protective layer of the insulating gate type transistor, exposing the first amorphous germanium layer; and covering the second amorphous germanium layer containing the impurity; and corresponding Sweep Selective etching of the second amorphous germanium layer and the first amorphous germanium layer and the gate insulating layer and the first metal layer by the line and the counter electrode; and forming an insulating layer on the side of the scan line and the opposite electrode The second amorphous germanium layer and the first amorphous germanium layer and the gate insulating-85-(16) (16) 1247158 layer in the field of contact with the uranium engraved scanning line in the field outside the image display portion, And a process of selectively exposing a portion of the scanning line; and after covering the first metal layer including the heat resistant metal layer and covering one or more layers, corresponding to the source wiring (signal line) in a manner partially overlapping the protective insulating layer The electrode wiring (pixel electrode) forms a film thickness ratio on the signal line with an electrode terminal including a signal line formed by an electrode terminal of a scanning line which is a part of the scanning line in a region outside the image display portion. a thicker photosensitive organic insulating layer pattern in other fields; and selectively removing the second metal layer and the second amorphous germanium layer and the first amorphous germanium layer by using the photosensitive organic insulating layer pattern as a mask And form the source • Electrode wiring, the electrode terminals of the scanning lines and the construction of the signal line; and a reduced thickness of the organic insulating layer of the photosensitive pattern, the exposed electrode terminals project drain wirings of the scan lines and signal lines. 1 6.  A method of manufacturing a liquid crystal display device having at least an insulating gate type transistor on a main surface, and a scanning line which also serves as a gate electrode of the insulating gate type transistor, and also serves as a source wiring signal a line, and a pixel electrode connected to the drain electrode of the insulating gate type transistor, and a unit pixel of a counter electrode formed by a specific distance from the pixel electrode, and the like, are arranged in a two-dimensional matrix. a liquid crystal display device in which a liquid crystal display device is filled between a first transparent insulating substrate and a second transparent insulating substrate or a color filter that faces the first transparent insulating substrate; A main surface of one of the transparent insulating substrates includes: a first insulating layer covering one or more layers, a gate insulating layer of one or more layers, and a first amorphous germanium layer and a protective insulating layer containing no impurities. And selectively forming a channel protection layer for the insulated gate type transistor -86- (17) (17) 1247158 insulating layer to expose the first amorphous germanium layer; and covering the second non-defective Crystalline layer engineering; Corresponding to the scanning line and the counter electrode, selectively etching the second amorphous germanium layer and the first amorphous germanium layer and the gate insulating layer and the first metal layer; and on the side of the scan line and the counter electrode a process of forming an insulating layer; and etching a second amorphous germanium layer and a first amorphous germanium layer and a gate insulating layer in a contact area of the scan line in a field outside the image display portion, and selectively exposing a portion of the scan line After the oxidized metal layer is covered and covered with one or more layers of the anodizable metal layer, the source wiring (signal line) and the drain wiring (pixel electrode) are overlapped with a part of the protective insulating layer. And a scanning line electrode terminal including a part of the scanning line and a signal line electrode terminal including a part of the signal line, forming a photosensitive resin pattern having a thickness larger than that of other fields; and the aforementioned sensitivity The resin pattern serves as a mask to selectively remove the anodizable metal layer and the second amorphous germanium layer and the first amorphous germanium layer to form source/drain wiring, and scan lines and signals The electrode of the wire is used for the work of the terminal; and the film thickness of the photosensitive resin pattern is reduced to expose the source/drain wiring; and the process of protecting the source electrode terminal and the anode source and the drain electrode. 17.  A method of manufacturing a liquid crystal display device, which is based on a main surface of a scan line having at least an insulating gate type transistor and a gate electrode which also serves as the insulating gate type transistor, and also serves as a source wiring a signal line, and a pixel element connected to the drain electrode of the insulating gate type transistor, and a counter pixel formed by a specific distance from the pixel electrode, and the like, are arranged in a two-dimensional matrix. The first transparent insulating substrate and the pair of -87-(18) (18) 1247158 are formed between the second transparent insulating substrate or the color filter of the first transparent insulating substrate, and are filled with liquid crystal. The method for manufacturing a liquid crystal display device is characterized in that at least one of the first transparent layers of the first transparent insulating substrate is provided with one or more first metal layers and one or more gate insulating layers. Engineering of the first amorphous germanium layer and the protective insulating layer of the impurity; and selectively forming the protective insulating layer of the channel protective layer of the insulating gate type transistor to expose the first amorphous germanium layer; and covering the impurity containing the impurity Second amorphous a project of a layer; and a project corresponding to the scanning line and the counter electrode in the field outside the image display portion, forming a photosensitive resin pattern having a thinner film thickness in the field of contact formation of the scanning line than in other fields; The resin pattern is used as a mask to sequentially etch the second amorphous germanium layer and the first amorphous germanium layer and the gate insulating layer and the first metal layer; and to reduce the film thickness of the photosensitive resin pattern. Exposing the second amorphous germanium layer in the field of contact formation; and forming an insulating layer on the side of the scanning line and the counter electrode; and using a photosensitive resin pattern having a reduced film thickness as a mask, uranium engraving Contacting the second amorphous germanium layer in the field of formation with the first amorphous chopped layer and the gate insulating layer to expose a portion of the scan line; and after including the heat resistant metal layer and covering the second metal layer of one or more layers A method of partially overlapping the protective insulating layer corresponds to a source wiring (signal line), a drain wiring (pixel electrode), and an electrode terminal including a part of the scanning line and an image terminal and an image display on the scanning line. The external field 'the signal line electrode terminal composed of one part of the signal line forms the project of the photosensitive organic insulating layer pattern with a thicker film thickness on the 丨s line than other fields; and will be -88- (19) 1247158 The photosensitive organic insulating layer pattern is used as a mask to selectively remove the second metal layer and the second amorphous germanium layer and the first amorphous germanium layer to form a source/drain wiring, and a scan line and a signal line. The work of the electrode terminal; and the process of reducing the film thickness of the photosensitive organic insulating layer pattern to expose the electrode terminals of the drain wiring and the scanning line and the signal line. 18.  A method of manufacturing a liquid crystal display device having at least an insulating gate type transistor on a main surface, and a scanning line which also serves as a gate electrode of the insulating gate type transistor, and also serves as a source wiring signal a line, and a pixel element connected to the drain electrode of the insulating gate type transistor, and a counter pixel formed by a specific distance from the pixel electrode, and the like, are arranged in a two-dimensional matrix. A method of manufacturing a liquid crystal display device in which a liquid crystal display device is filled between a first transparent insulating substrate and a second transparent insulating substrate or a color filter that faces the first transparent insulating substrate, and is characterized by At least one of the main surfaces of the first transparent insulating substrate includes: a first metal layer of one or more layers, a gate insulating layer of one or more layers, and a first amorphous layer and a protective insulating layer containing no impurities. Engineering of the layer; and a process of selectively forming a protective insulating layer of the channel protective layer of the insulating gate type transistor, exposing the first amorphous germanium layer; and covering the second amorphous germanium layer containing the impurity; Corresponding to In the field outside the image display portion, the scanning line and the counter electrode form a photosensitive resin pattern having a thinner film thickness in the field of contact formation of the scanning line than in other fields; and the photosensitive resin pattern is used as a mask. And sequentially etching the second amorphous germanium layer and the first amorphous germanium layer and the gate insulating layer and the first metal layer; and reducing the thickness of the photosensitive resin pattern of -89-(20) 1247158, and Exposing a contact to form a 2 amorphous layer; and engineering the insulating layer between the scan line and the counter electrode; and a photosensitive tree mask which reduces the film thickness to etch the second amorphous layer in the contact formation field The bismuth layer and the gate insulating layer are exposed to the refractory layer containing one portion of the scanning line and covered with one or more layers, and are anodized to partially overlap the protective insulating layer (signal line) • drain wiring (pixel element) and a portion of the scanning line electrode terminal and a signal electrode including one electrode terminal, forming a film thickness of the electrode terminal compared to other light-receiving resin patterns; a resin cover for selectively removing the anodizable metal layer and the second first amorphous germanium layer to form a source/drain wiring, and an electrode terminal of the wire; and reducing the photosensitive tree thickness Excavation of source and bungee wiring; and protection of the front and the simultaneous anodization of source and drain wiring. 19.  The manufacturing method of a liquid crystal display device as described in claim 10, the first aspect, the third item, the fourth item, the item For the organic insulating layer, by electroforming 20.  The liquid crystal display device of claim 11, wherein the first metal layer is formed on the scan line by an anodizable metal layer. The insulating layer on the side is formed on the first side in the field of anodization, forming a grease pattern as a thicker pattern with the first amorphous project; and a metal layer of the package on the signal line of the source line. As the film electrode terminal 12, which blocks the amorphous germanium layer and the trace line and the signal grease pattern, 7 or 18 is formed by scanning. 1 5, the 1st 6 manufacturing method, formed, formed. -90-