JP2002185003A - Liquid crystal image display device and method of manufacturing semiconductor device for image display device - Google Patents

Abstract

(57) [Problem] To provide a conventional TFT irrespective of a channel-etch type or an etch-stop type, a positional relationship between a gate and a source / drain is determined by mask alignment at the time of exposure and is not a self-aligned type. There is a drawback that the overlapping capacity is large and the in-plane variation occurs, and this is a cause of flicker and crosstalk in a large-screen high-definition device. SOLUTION: In addition to a gate metal, a gate insulating layer, and a semiconductor layer, a lift-off layer is also formed by collective etching, an organic insulating layer is formed on a side surface of a gate, and a resist pattern is receded to form a source / drain region. Self-aligned T forming
Based on FT, a low-temperature technology that eliminates the need for a passivation insulating layer by anodizing source / drain wiring, forming a source / drain electrode, and forming an opening in the insulating layer requires an organic insulating layer on the exposed scanning line. The technology can be streamlined by introducing the technology to form the process, and the process can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display having a color image display function, and more particularly to an active liquid crystal display.

[0002]

2. Description of the Related Art Recent advances in microfabrication technology, liquid crystal material technology, and high-density packaging technology have resulted in the provision of large quantities of television images and various image display devices on a commercial basis on liquid crystal panels with a diagonal of 5 to 50 cm. ing. Further, color display can be easily realized by forming an RGB colored layer on one of the two glass substrates constituting the liquid crystal panel. In particular, in a so-called active type liquid crystal panel in which a switching element is incorporated for each picture element, an image having little crosstalk, high speed response, and high contrast ratio is guaranteed.

[0003] These liquid crystal image display devices (liquid crystal panels)
Represents 200 to 1200 scanning lines and 200 to 16 signal lines
A matrix organization of about 00 lines is generally used, but recently, a large screen and a high definition have been simultaneously developed to cope with an increase in display capacity.

FIG. 19 shows a mounting state on a liquid crystal panel.
A semiconductor integrated circuit chip 3 for supplying a drive signal to one of the transparent insulating substrates constituting the liquid crystal panel 1, for example, a group of scanning line terminal electrodes 6 formed on a glass substrate 2, is connected using a conductive adhesive. COG (Chip-On-Glass) method, for example, a T based on a polyimide resin thin film and having gold or solder plated copper foil terminals (not shown)
TCP (Tape-Car) for fixing the CP film 4 to the terminal electrodes 5 of the signal lines by pressing with a suitable adhesive containing a conductive medium.
An electric signal is supplied to the image display unit by a mounting means such as a carrier-package method. Here, for the sake of convenience, two mounting methods are shown simultaneously, but in practice, either method is appropriately selected.

[0005] Reference numerals 7 and 8 denote an image display portion located substantially at the center of the liquid crystal panel 1 and terminal electrodes 5 and 6 for signal lines and scanning lines.
Between the terminal electrode groups 5, 6
It is not necessary to be made of the same conductive material as that described above. Reference numeral 9 denotes another transparent insulating substrate or a color filter, which is another transparent insulating substrate having a transparent conductive counter electrode common to all liquid crystal cells on the opposite surface.

FIG. 20 shows an equivalent circuit diagram of an active liquid crystal panel in which insulated gate transistors 10 are arranged as switching elements for each picture element, and 11 (8 in FIG. 19).
Is a scanning line, 12 (7 in FIG. 19) is a signal line, 13 is a liquid crystal cell, and the liquid crystal cell 13 is electrically treated as a capacitive element. The elements drawn by solid lines are formed on one glass substrate 2 constituting the liquid crystal panel, and the common electrodes 14 common to all the liquid crystal cells 13 drawn by dotted lines are formed on the other glass substrate 9. ing. When the OFF resistance of the insulated gate transistor 10 or the resistance of the liquid crystal cell 13 is low, or when importance is placed on the gradation of a display image, an auxiliary storage capacitor 15 for increasing the time constant of the liquid crystal cell 13 as a load. Are added to the liquid crystal cell 13 in parallel. Reference numeral 16 denotes a common bus of the storage capacitor 15.

FIG. 21 is a sectional view of a main part of an image display portion of a liquid crystal panel. Two glass substrates 2 and 9 constituting the liquid crystal panel 1 are made of a spacer material (not shown) such as resin fibers or beads. Is formed at a predetermined distance of about several μm, and the gap is sealed at the periphery of the glass substrate 9 with a sealing material made of an organic resin and a sealing material (neither is shown). The closed space is filled with liquid crystal 17.

In order to realize a color display, an organic thin film having a thickness of about 1 to 2 μm containing one or both of a dye and a pigment called a colored layer 18 is applied to the closed space side of the glass substrate 9. Since a color display function is provided, in this case, the glass substrate 9 is also called a color filter (Color
The Filter abbreviation is called CF). Then, depending on the properties of the liquid crystal material 17, a polarizing plate 19 is attached to either or both of the upper surface of the glass substrate 9 or the lower surface of the glass substrate 2, and the liquid crystal panel 1 functions as an electro-optical element.
At present, most liquid crystal panels on the market use TN (twisted nematic) type liquid crystal materials.
Usually, two polarizing plates 19 are required. Although not shown, a rear light source is arranged as a light source in the transmission type liquid crystal panel, and white light is emitted from below.

The two glass substrates 2 and 9 are in contact with the liquid crystal 17.
The polyimide resin thin film 20 having a thickness of, for example, about 0.1 μm formed thereon is an alignment film for aligning liquid crystal molecules in a predetermined direction. 21 is an insulated gate transistor 1
0 is a drain electrode (wiring) for connecting the transparent conductive picture element electrode 22 to the signal line (source line) 12.
Often formed at the same time. The semiconductor layer 23 is located between the signal line 12 and the drain electrode 21 and will be described later in detail. Colored layers 1 adjacent on color filter 9
8 and a Cr thin film layer 24 having a thickness of about 0.1 μm
Is a light shield for preventing external light from entering the semiconductor layer 23, the scanning lines 11 and the signal lines 12, and is a technology fixed as a so-called black matrix (abbreviated as BM).

Here, the structure and manufacturing method of an insulated gate transistor as a switching element will be described. Two types of insulated gate transistors are currently in heavy use, and one of them is introduced as a conventional example (referred to as an etch stop type). FIG. 22 is a plan view of a unit picture element of an active substrate (semiconductor device for an image display device) constituting a conventional liquid crystal panel. FIG. Is briefly described below. The projection 50 formed on the scanning line 11
A region 51 where the pixel electrode 22 and the pixel electrode 22 overlap with each other with a gate insulating layer interposed therebetween (a hatched portion inclined downward to the right) forms the storage capacitor 15, but a detailed description thereof is omitted here.

First, as shown in FIG. 23A, an insulating substrate having a high heat resistance, a high chemical resistance and a high transparency has a thickness of 0.5 to 0.5 mm.
A glass substrate 2 having a thickness of about 1.1 mm, for example, a first metal layer having a thickness of about 0.1 to 0.3 μm is formed on one main surface of a product 1737 manufactured by Corning using a vacuum film forming apparatus such as SPT (sputtering). By depositing Cr, Ta, Mo, or the like, or an alloy or silicide thereof, a gate electrode 11 also serving as a scanning line is selectively formed by a fine processing technique. The material of the scanning line is preferably selected in consideration of heat resistance, chemical resistance, hydrofluoric acid resistance and conductivity.

In order to reduce the resistance of the scanning line in response to the increase in the screen size of the liquid crystal panel, AL (aluminum) is used as the material of the scanning line. At present, it is also a general technique to laminate with Cr, Ta, Mo or silicide thereof, or to add an oxide layer (AL2O3) to the surface of AL by anodic oxidation. That is, the scanning line 11 is formed of one or more metal layers.

Next, as shown in FIG. 23 (b), a first SiNx (silicon nitride) layer serving as a gate insulating layer is formed on the entire surface of the glass substrate 2 by using a PCVD (Plasma Thievey) apparatus. Not including first amorphous silicon (a-Si) to be the channel of the insulated gate transistor
A second SiNx layer serving as an insulating layer for protecting the layer and the channel and three types of thin film layers are sequentially deposited to a thickness of, for example, about 0.3-0.05-0.1 μm to form 30, 31, and 32.

As a know-how technique, when forming a gate insulating layer, another type of insulating layer (for example, TaOx or SiO2) is used.
Etc. or laminated with AL2O3) mentioned above, or S
In many cases, yield improvement measures such as providing an iNx layer in two steps and providing a cleaning step in the middle thereof are performed, and the gate insulating layer is not limited to one type or a single layer.

Subsequently, the second amorphous SiNx layer on the gate 11 is selectively left narrower than the gate 11 by a fine processing technique to form 32 ', exposing the first amorphous silicon layer 31, and the PCVD apparatus is also used. A second amorphous silicon layer 33 containing, for example, phosphorus as an impurity is deposited on the entire surface with a thickness of, for example, about 0.05 μm, and then only on the vicinity of the gate 11 as shown in FIG. The gate insulating layer 30 is exposed while leaving the first amorphous silicon layer 31 and the second amorphous silicon layer 33 in island shapes 31 'and 33'.

Subsequently, as shown in FIG.
For example, ITO (Indium-Tin-Oxide) is applied as a transparent conductive layer having a thickness of about 0.1 to 0.2 μm using a vacuum film forming apparatus such as PT, and the pixel electrode 22 is formed on the gate insulating layer 30 by a fine processing technique. Formed selectively.

Further, as shown in FIG. 23 (e), a selective opening 63 is formed in the gate insulating layer 30 on the scanning line 11 at the periphery of the image display section necessary for electrical connection to the scanning line 11. After that, as shown in FIG. 23 (f), a thin film layer 34 of, for example, Ti, Cr, Mo or the like is formed as a heat-resistant metal layer having a thickness of about 0.1 μm by using a vacuum film forming apparatus such as SPT. An AL thin film layer 35 having a thickness of about 0.3 μm is sequentially deposited as a wiring layer, and is formed by laminating a heat-resistant metal layer 34 ′ and a low-resistance wiring layer 35 ′ by a fine processing technique. A drain electrode 21 of the transistor and a source electrode 12 also serving as a signal line are selectively formed. Using the photosensitive resin pattern used for the selective pattern formation as a mask, the second amorphous silicon layer 33 'between the source and drain electrodes is removed to expose the second SiNx layer 32', and the other regions are formed. Then, the first amorphous silicon layer 31 'is also removed to expose the gate insulating layer 30. This step is called an etch stop because the etching of the second amorphous silicon layer 33 'is automatically terminated due to the presence of the second SiNx layer 32' which is a protective layer of the channel. It is.

The source / drain electrodes 12 and 21 are formed so as to partially overlap the gate 11 (several μm) so that the insulated gate transistor does not have an offset structure.
Since this overlap electrically acts as a parasitic capacitance, the smaller the better, the better. However, it is determined by the alignment accuracy of the exposure machine, the accuracy of the mask, the expansion coefficient of the glass substrate, and the glass substrate temperature at the time of exposure. It is about. In addition, at the periphery of the image display unit, including the opening 63 on the scanning line 11, the signal line 12 and the scanning line side terminal electrode 6 simultaneously with the signal line 12, or the wiring connecting the scanning line 11 and the scanning line side terminal electrode 6. Forming the road 8 is also a general pattern design.

Finally, as a transparent insulating layer, a SiNx layer having a thickness of about 0.3 to 0.7 μm is deposited on the entire surface of the glass substrate 2 using a PCVD apparatus in the same manner as the gate insulating layer 30 to form a passivation insulating layer. 37, and an opening 38 is formed on the pixel electrode 22 as shown in FIG.
Are exposed, and the manufacturing process of the active substrate ends. At this time, openings are also formed on the terminal electrodes 6 of the scanning lines and the terminal electrodes 5 of the signal lines, and most of the terminal electrodes are also exposed.

When the wiring resistance of the signal line 12 does not matter, the low-resistance wiring layer 35 made of AL is not always necessary. The drain wirings 12 and 21 can be made into a single layer. The heat resistance of the insulated gate transistor is described in detail in Japanese Patent Application Laid-Open No. 7-74368, which is a prior example.

The passivation insulating layer 3 on the picture element electrode 22
The reason for removing 7 is, firstly, to prevent a decrease in the effective voltage applied to the liquid crystal cell, and secondly, because the film quality of the passivation insulating layer 37 is generally poor, This is for avoiding the accumulation of the electric charges and the burning of the displayed image. This is because the heat resistance of the insulated gate transistor is not so high, so that the film forming temperature of the passivation insulating layer 37 is inevitably lower than that of the gate insulating layer 30 by several tens of degrees Celsius and lower than 250 degrees Celsius. Because.

The manufacturing process of the active substrate described above requires a photolithography process seven times, and is an almost standard manufacturing method called a seven-mask process. Reduction of the number of manufacturing processes is an important proposition for liquid crystal panel manufacturers in order to realize lower prices for liquid crystal panels and respond to further increases in demand. I've been.

FIG. 24 is a plan view of a unit picture element of the active substrate corresponding to the five masks. FIG. 25 is a cross-sectional view taken along the line AA 'in FIG. A brief description will be given below of a case where another conventional one (referred to as a channel etch type) is employed. A region 52 where the storage capacitance line 16 and the drain electrode 21 overlap each other with the gate insulating layer 30 interposed therebetween (a hatched portion falling to the right) forms the storage capacitance 15, but a detailed description thereof is omitted here. .

First, similarly to the conventional example, as shown in FIG. 25A, a first film having a thickness of about 0.1 to 0.3 μm is formed on one main surface of a glass substrate 2 by using a vacuum film forming apparatus such as SPT. And a gate electrode 11 also serving as a scanning line and a storage capacitor line 16 are selectively formed by a fine processing technique.

Next, as shown in FIG. 25B, a SiNx layer serving as a gate insulating layer is formed on the entire surface of the glass substrate 2 by using a PCVD apparatus, and a first channel serving as a channel of an insulated gate transistor containing almost no impurities. An amorphous silicon layer, a second amorphous silicon layer containing impurities and serving as a source / drain of an insulated gate transistor, and three types of thin film layers are sequentially formed in a thickness of, for example, about 0.3-0.2-0.05 μm. 30, 31, and 33 are attached.

Then, as shown in FIG. 25C, the gate insulating layer 30 is formed on the gate 11 by leaving the semiconductor layers made of the first and second amorphous silicon layers in the form of islands 31 'and 33'. Exposed.

Subsequently, as shown in FIG.
Using a vacuum film forming apparatus such as PT, for example, a Ti thin film layer 34 as a heat-resistant metal layer with a thickness of about 0.1 μm, an AL thin film layer 35 with a thickness of about 0.3 μm as a low-resistance wiring layer, and a 0.1 μm-thick For example, a Ti thin film layer 36 is sequentially deposited as an intermediate conductive layer, and the drain electrode 21 of the insulated gate transistor and the source electrode 12 also serving as a signal line are selectively formed by a fine processing technique. This selective patterning is
Using the photosensitive resin pattern used for forming the drain wiring as a mask, the Ti thin film layer 36, the AL thin film layer 35, the Ti thin film layer 34, the second amorphous silicon layer 33 ', and the first amorphous silicon layer 31' Are sequentially etched, and the first amorphous silicon layer 31 'is etched by leaving about 0.05 to 0.1 .mu.m, so that it is called a channel etch.

After removing the photosensitive resin pattern, a transparent insulating layer is formed on the entire surface of the glass substrate 2 as shown in FIG.
A passivation insulating layer 37 is formed by depositing a SiNx layer having a thickness of about 0.3 μm using an apparatus, and an opening 63 is formed on the drain electrode 21 and an opening 63 is formed on a position where the terminal electrode 6 of the scanning line 11 is formed. To form the drain electrode 21 and the scanning line 1
Expose a portion of 1. Although not shown, an opening 64 is also formed on the position where the terminal electrode 5 of the signal line is formed to expose a part of the signal line 12.

Finally, as shown in FIG.
For example, ITO (Indium-Tin-Oxide) is applied as a transparent conductive layer having a thickness of about 0.1 to 0.2 μm using a vacuum film forming apparatus such as Then, the picture element electrode 22 is selectively formed to complete the active substrate 2. A part of the scanning line 11 exposed in the opening 63 may be used as the terminal electrode 6, and the terminal electrode 6 ′ made of ITO is selectively formed on the passivation insulating layer 37 including the opening 63 as shown in the figure. It may be formed.

As described above, the five-mask process is one time in the rationalization of the islanding process of the semiconductor layer, compared with the seven-mask process.
In addition, the step of forming an opening (contact) to a scanning line and the step of forming an opening to a pixel electrode and the step of forming a contact, which were required twice, have been streamlined once, thereby eliminating a total of two photo etching steps. Can be. In addition, since the pixel electrode 22 is located on the uppermost layer of the active substrate 2, the passivation insulating layer 37 is formed by using a transparent resin thin film, for example, for 1.5 times.
If the pixel electrode 22 is formed thicker than μm, even if the pixel electrode 22 overlaps the scanning line 11 or the signal line 12, interference due to capacitance is small and deterioration of image quality can be avoided.
Can be formed large and the aperture ratio can be improved.

[0031]

As described above, the source / drain electrodes 12 and 21 are formed so as to partially overlap the gate 11 so that the insulated gate transistor does not have an offset structure. Since this overlap electrically acts as a parasitic capacitance, the smaller the better, the better.
It is about μm. Rather, the thickness is preferably about 3 μm from the viewpoint of manufacturing margin during mass production.

In the case of the etch stop type, since the gate and the source / drain electrodes are aligned with an etch stop layer interposed therebetween, an overlap capacitance of two times of alignment accuracy is required. Although it cannot be obtained, these overlapping capacitances fluctuate within the glass substrate (although at most 1 μm) due to the optical distortion of the lens or mirror of the exposure apparatus, so that flickering, printing, and display occur on a large screen and high definition device. It is inevitable from image quality problems such as spots.

Japanese Patent Application Laid-Open Nos. 62-205664 and 63-168052 disclose prior art examples in which a source / drain electrode can be formed in a self-aligned manner with a gate. Then, an etch stop layer slightly thinner (at most 1 μm) than the gate is formed on the gate, and the source / drain is formed by irradiating or implanting impurities with the etch stop layer as a mask. For the source / drain formed in a self-aligned manner, the former is incomplete and cannot be formed in a self-aligned manner up to the source / drain electrodes. When a metal having a melting point, for example, Cr is deposited and heated, silicide is formed on the source / drain. Therefore, if Cr on the etch stop layer is removed with an etching solution, a source / silicide having a low resistance value is formed.
The drain electrode is formed in a self-aligned manner.

However, the back exposure stage naturally requires a highly transparent quartz or glass plate, and a warp or undulation of the glass substrate requires a vacuum suction mechanism to the stage. Whether it can meet the requirements and be able to be mass-produced stably is still opaque compared to the conventional metallic stage. There is a problem that deterioration of electrical characteristics is inevitable due to heat treatment (200 ° C. or higher).

In general, a passivation insulating layer is employed for passivating the source / drain wirings.
Even if it is carried out in a low-temperature film formation of several tens of degrees Celsius or lower and 250 degrees Celsius or less in comparison with
Especially, the ON current of the insulated gate transistor is 10 to 30%.
It is inevitable that the degree will decrease. The reduction in the current driving capability of the insulated gate transistor becomes a major obstacle to increase the wiring resistance in order to obtain a large screen and high definition liquid crystal panel.

In addition, in the case of a channel-etch type insulated gate transistor, the first region containing no impurity in the channel region is used.
If the amorphous silicon layer is not deposited thick (usually 0.2 μm or more in the case of a channel etch type), the transistor characteristics tend to be uneven due to the in-plane uniformity of the glass substrate. . This greatly affects the operation rate of PCVD and the state of particle generation, and is very important from the viewpoint of production cost.

The present invention has been made in view of the above situation, and has developed a new self-aligned source / drain formation technique without using backside exposure, and also has a low-temperature passivation to compensate for the low heat resistance of an insulated gate transistor. It is an object of the present invention to solve the above-mentioned problems by formation. As already mentioned, it is necessary to pursue a further reduction in the number of manufacturing steps in order to realize a reduction in the price of the liquid crystal panel and to respond to an increase in demand.

[0038]

According to the present invention, first, a resist pattern at the time of gate formation is receded to expose an amorphous silicon layer containing no impurities on the end of the gate. Source / drain and source / drain composed of an amorphous silicon layer containing impurities on a crystalline silicon layer
A lift-off layer is also used so that the drain electrode is formed in a self-aligned manner. Further, in order to effectively passivate only the source / drain wiring, the anodic oxidation technique for forming an insulating layer on the surface of the source / drain wiring made of aluminum disclosed in Japanese Patent Application Laid-Open No. 2-216129, which is a prior art, is fused. In this way, it is intended to realize a streamlining process and a low temperature. Further, by forming an organic insulating layer on the exposed scanning line to further reduce the number of steps, it is possible to streamline the step of forming source / drain wiring and the step of forming an opening in the gate insulating layer.

The insulated gate transistor according to claim 1, wherein at least one metal layer having a gate insulating layer on its surface and an organic insulating layer on its side surface is used as a gate, and a gate insulating layer is formed on the gate. A semiconductor layer containing no impurity is formed, and a stack of a semiconductor layer containing a pair of impurities and a metal layer formed in a self-aligning manner on both ends of the semiconductor layer containing no impurity is used as a source / drain electrode. It is characterized by doing.

With this configuration, in the insulated gate transistor, the source / drain electrodes are formed in a self-aligned manner with respect to the gate, and the parasitic capacitance between the gate and the source / drain is reduced to a fraction of the conventional value.

According to a second aspect of the present invention, in the liquid crystal image display device, a unit pixel having at least an insulated gate transistor on one main surface and a pixel electrode connected to a drain of the insulated gate transistor is two-dimensional. In a liquid crystal image display device in which liquid crystal is filled between an insulating substrate arranged in a matrix and a transparent insulating substrate or a color filter facing the insulating substrate, the surface of the insulating substrate is formed on one main surface. 1 having a gate insulating layer and an organic insulating layer on its side
A scan line formed of a metal layer or more and also serving as a gate of the insulated gate transistor is formed, and a semiconductor layer containing no impurities is formed over the gate with a gate insulating layer interposed therebetween.
A source (signal line) except for a drain electrode and a scanning line formed by stacking a pair of a semiconductor layer containing an impurity and a metal layer on both ends of the semiconductor layer containing no impurity and on the insulating substrate.
An electrode is formed, and a passivation insulating layer having a first opening on the drain electrode and a pair of second openings on the source (signal line) electrode is formed on the entire surface and includes the first opening. And a connection layer for connecting a source (signal line) electrode divided including the second opening is formed on the passivation insulating layer.

With this structure, the parasitic capacitance between the gate and the source / drain is reduced to a fraction of that of the conventional device. Reduce.

A liquid crystal image display device according to claim 3, wherein the insulated gate comprises at least one metal layer having a gate insulating layer on one main surface of the insulating substrate and an organic insulating layer on the side surface. A scanning line also serving as a gate of the transistor is formed, a semiconductor layer containing no impurities is formed on the gate via a gate insulating layer, and a pair of semiconductor layers on both ends of the semiconductor layer containing no impurities and the insulating substrate are formed. A source / drain electrode composed of a stack of a semiconductor layer containing impurities and a metal layer is formed; a signal line composed of one or more metal layers including the source electrode is formed on an insulating substrate; A passivation insulating layer having an opening is formed on the entire surface, and a pixel electrode is formed on the passivation insulating layer including the opening.

With this configuration, not only can a self-aligned insulated gate transistor be obtained, but also the resistance of the signal line can be reduced, and a large screen device can be easily manufactured.

A liquid crystal image display device according to claim 4, wherein the insulated gate comprises at least one metal layer having a gate insulating layer on one main surface of the insulating substrate and an organic insulating layer on the side surface thereof. A scanning line also serving as a gate of the type transistor is formed, a semiconductor layer containing no impurity is formed on the gate via a gate insulating layer, and a pair of semiconductor layers on both ends of the semiconductor layer containing no impurity and the insulating substrate are formed. A source (signal line) electrode is formed except for a drain electrode and a scanning line except for a scanning line, and a pixel electrode including the drain electrode is formed on an insulating substrate. A connection layer for connecting the separated source (signal line) electrode is formed, and anodization is performed on the surface of the semiconductor layer containing no impurities and the source electrode excluding the connection layer and the drain electrode excluding the pixel electrode. Wherein the but has been formed.

With this configuration, not only can a self-aligned insulated gate transistor be obtained, but also the process can be performed at a lower temperature, and it is not necessary to apply a passivation insulating layer over the entire surface of the glass substrate. Is reduced in heat resistance.

A liquid crystal image display device according to a fifth aspect of the present invention also comprises one or more anodically oxidizable metal layers on one main surface of the insulating substrate, a gate insulating layer on the surface thereof, and an organic insulating layer on the side surface. A scanning line also serving as a gate of an insulated gate transistor and an auxiliary signal line having an opening at both ends having a gate insulating layer and an anodized layer on the side surface thereof are formed on the surface thereof, and on the gate, A semiconductor layer containing no impurity is formed via the gate insulating layer, a picture element electrode is formed on the insulating substrate including the drain electrode, and both ends of the semiconductor layer containing no impurity and on the insulating substrate are formed. A drain electrode and a source / drain electrode composed of a stack of a semiconductor layer containing a pair of impurities and an anodizable metal layer are formed,
A picture element electrode including the drain electrode and a connection layer connecting the divided auxiliary signal line including the opening and the source electrode are formed on the insulating substrate, and the source electrode and the picture element except the connection layer are formed. An anodic oxide layer is formed on the surface of the drain electrode excluding the electrode and the surface of the semiconductor layer containing no impurities.

According to this configuration, not only a self-aligned insulated gate transistor can be obtained, but also lower temperature of the process and lowering of the resistance of the signal line can be promoted without increasing the number of film forming steps. Production becomes possible.

The liquid crystal image display device according to claim 6, further comprising at least one metal layer having a gate insulating layer on one surface and an organic insulating layer on the side surface on one main surface of the insulating substrate. A scanning line also serving as a gate of the type transistor is formed, a semiconductor layer containing no impurity is formed on the gate via a gate insulating layer, and a pair of semiconductor layers on both ends of the semiconductor layer containing no impurity and the insulating substrate are formed. A source / drain electrode formed of a stack of a semiconductor layer containing an impurity and an anodizable metal layer, and a signal line comprising at least one anodizable metal layer including the source electrode on an insulating substrate. Is formed, a picture element electrode including the drain electrode is formed on the insulating substrate, and the signal line, the source electrode excluding the signal line, the drain electrode excluding the picture element electrode, and the impurity-free semiconductor layer are formed. And an anodized layer is formed on the surface.

With this configuration, not only a self-aligned insulated gate transistor can be obtained, but also a lower temperature process and a lower resistance of the signal line are promoted, so that a large screen device can be easily manufactured.

According to a seventh aspect of the present invention, in the liquid crystal image display device, at least one layer having an organic insulating layer on one main surface of the insulating substrate except for between channels and below a source (signal line) / drain electrode. A scanning line which is also made of a metal layer and which also serves as a gate of the insulated gate transistor is formed, a semiconductor layer containing no impurities is formed on the gate via a gate insulating layer, and both ends of the semiconductor layer containing no impurities are formed on the gate. A drain electrode composed of a stack of a pair of a semiconductor layer containing impurities and an anodizable metal layer on the insulating substrate and a source (signal line) electrode except on a scanning line; and forming the drain electrode on the insulating substrate. To form a connection layer for connecting the picture element electrode and the separated source (signal line) electrode, and the source electrode excluding the connection layer, the drain electrode excluding the picture element electrode, and the impurities are not included. And an anodized layer is formed on the surface of the semiconductor layer.

With this configuration, not only can a self-aligned insulated gate transistor be obtained, but also the process can be reduced in temperature and rationalized, and the manufacturing cost can be reduced.

In the liquid crystal image display device according to the present invention, at least one anodic oxidizable layer having an organic insulating layer on one main surface of the insulating substrate except for between channels and below source / drain electrodes. A scanning line composed of a metal layer and also serving as a gate of an insulated gate transistor and an auxiliary signal line having an anodized layer on its surface except for both end portions are formed, and impurities are contained on the gate via a gate insulating layer. And a source / drain electrode formed of a stack of a pair of a semiconductor layer containing an impurity and an anodizable metal layer on both ends of the semiconductor layer containing no impurity and on an insulating substrate. Forming a picture element electrode on the insulating substrate including the drain electrode and a connection layer connecting the divided auxiliary signal lines including the both ends and the source electrode, excluding the connection layer; And an anodized layer is formed on the surface of the semiconductor layer containing no drain electrode and impurities excluding electrode and the pixel electrode.

According to this configuration, not only can a self-aligned insulated gate transistor be obtained, but also a reduction in the resistance of the signal line can be realized without increasing the film forming process in addition to lowering and rationalizing the process. Large screen devices can be manufactured.

A liquid crystal image display device according to a ninth aspect of the present invention comprises one or more metal layers having an organic insulating layer on the surface of the insulating substrate except for between channels and below source / drain electrodes on one main surface of the insulating substrate. A scanning line serving also as a gate of the insulated gate transistor is formed, a semiconductor layer containing no impurity is formed on the gate via a gate insulating layer, and both ends of the semiconductor layer containing no impurity and on an insulating substrate are formed. A source / drain electrode formed of a stack of a semiconductor layer containing a pair of impurities and an anodizable metal layer is formed on the insulating substrate by using one or more anodizable metal layers including the source electrode. A signal line is formed on the insulating substrate, and a picture element electrode including the drain electrode is formed on the insulating substrate. The signal line, a source electrode excluding the signal line, a drain electrode excluding the picture element electrode, and an impurity are formed. And an anodized layer is formed on the surface without semiconductor layer.

According to this configuration, not only can a self-aligned insulated gate transistor be obtained, but also not only can the process be reduced in temperature and rationalized, but also the resistance of the signal line can be reduced, and a large screen device can be manufactured. It is easy to manufacture.

According to a tenth aspect of the present invention, there is provided a method of manufacturing a liquid crystal image display device according to the second aspect, wherein one or more first metal layers are formed on one main surface of the insulating substrate, and Depositing a lift-off layer after sequentially depositing at least one gate insulating layer and a first semiconductor layer containing no impurities except on a part of the first metal layer at a peripheral portion of the substrate; Selectively forming a photosensitive resin pattern corresponding to a scanning line also serving as a gate of an insulated gate transistor on the lift-off layer; and using the photosensitive resin pattern as a mask, a lift-off layer, a first semiconductor layer, and a gate insulating layer. A step of sequentially etching the first metal layer; a step of partially exposing the lift-off layer by reducing the film thickness of the photosensitive resin pattern; Chopping A step of partially exposing the first semiconductor layer, a step of forming an organic insulating layer on a side surface of the scanning line, and a step of sequentially depositing a second semiconductor layer containing impurities and a second metal layer. Selectively removing the second semiconductor layer and the second metal layer on the lift-off layer together with the removal of the lift-off layer; and removing the second semiconductor layer and the second metal layer on the gate and the insulating substrate on both ends of the gate. A step of selectively forming a drain electrode formed of a stack of a second semiconductor layer and a second metal layer and a separated source (signal line) electrode; a step of applying a passivation insulating layer; Forming an opening on the upper side and on a source (signal line) electrode, selectively removing the passivation insulating layer in the opening, applying a conductive thin film, and forming the drain on the passivation insulating layer. Picture element including the opening on the electrode Characterized by a step of selectively forming a connection layer for connecting the shed source (signal line) electrodes comprise electrode To the source (signal line) opening on the electrode.

According to this structure, an impurity-containing semiconductor layer can be formed on both ends of the impurity-free semiconductor layer formed on the gate via the gate insulating layer, and the impurity-free semiconductor layer at both ends can be formed. A semiconductor layer (source / drain) containing impurities and source / drain electrodes are formed in a self-aligned manner, whereby a self-aligned insulated gate transistor is obtained.

An eleventh aspect is the method for manufacturing a liquid crystal image display device according to the third aspect, wherein one principal surface on the insulating substrate is
Depositing at least one first metal layer and at least one gate insulating layer and an impurity-free first semiconductor except on a part of the first metal layer at a peripheral portion of the insulating substrate. Forming a photosensitive resin pattern corresponding to a scanning line also serving as a gate of an insulated gate transistor on the lift-off layer; and A step of sequentially etching the lift-off layer, the first semiconductor layer, the gate insulating layer and the first metal layer using the resin pattern as a mask, and a step of partially exposing the lift-off layer by reducing the film thickness of the photosensitive resin pattern When,
Etching the lift-off layer using the photosensitive resin pattern reduced in thickness as a mask to partially expose the first semiconductor layer; forming an organic insulating layer on the side surface of the scan line; Successively depositing a second semiconductor layer and a second metal layer including the second semiconductor layer and a second metal layer, and selectively removing the second semiconductor layer and the second metal layer on the lift-off layer together with the removal of the lift-off layer Selectively forming source / drain electrodes comprising a stack of a second semiconductor layer and a second metal layer on the exposed first semiconductor layer and on the insulating substrate; A step of applying the third metal layer,
Selectively forming a signal line made of a third metal layer including the source electrode; applying a passivation insulating layer; forming an opening on the drain electrode to form a passivation insulating layer in the opening. Selectively removing a layer, applying a conductive thin film, and selectively forming a pixel electrode on the passivation insulating layer including an opening on the drain electrode. Features.

According to this configuration, not only a self-aligned insulated gate transistor can be obtained, but also the resistance of the signal line can be reliably reduced, and a large-screen device can be easily manufactured.

A twelfth aspect of the present invention is the method of manufacturing a liquid crystal image display device according to the fourth aspect, wherein one principal surface on the insulating substrate is
Depositing at least one first metal layer and at least one gate insulating layer and an impurity-free first semiconductor except on a part of the first metal layer at a peripheral portion of the insulating substrate. Forming a photosensitive resin pattern corresponding to a scanning line also serving as a gate of an insulated gate transistor on the lift-off layer; and A step of sequentially etching the lift-off layer, the first semiconductor layer, the gate insulating layer and the first metal layer using the resin pattern as a mask, and a step of partially exposing the lift-off layer by reducing the film thickness of the photosensitive resin pattern When,
A step of etching the lift-off layer using the photosensitive resin pattern having a reduced film thickness as a mask to partially expose the first semiconductor layer, a step of forming an organic insulating layer on a side surface of the scan line, and impurities Anodically oxidizable second semiconductor layer
Sequentially removing the second semiconductor layer and the second metal layer on the lift-off layer while removing the lift-off layer; and removing the first and second metal layers on both ends of the gate. Selectively forming a drain electrode formed of a stack of a second semiconductor layer and a second metal layer and a separated source (signal line) electrode on the semiconductor layer and the insulating substrate, and a conductive thin film And selectively connecting a picture element electrode including the drain electrode and a divided source (signal line) electrode including the source (signal line) electrode on the insulating substrate. Forming a source electrode excluding the connection layer and a drain excluding the pixel electrode while irradiating light while protecting the pixel electrode using the photosensitive resin pattern used as a mask for the selective pattern formation of the pixel electrode as a mask. Electrode and first semiconductor without impurities Forming an anodic oxide layer on the layer.

With this configuration, not only can a self-aligned insulated gate transistor be obtained, but also the process can be reduced in temperature and the heat resistance of the insulated gate transistor can be reduced.

According to a thirteenth aspect, in the method for manufacturing a liquid crystal image display device according to the fifth aspect, at least one anodizable first metal layer is applied on one main surface of the insulating substrate. A step of depositing a lift-off layer after sequentially depositing at least one gate insulating layer and a first semiconductor layer containing no impurities except for a part of the first metal layer in a peripheral portion of the insulating substrate. And selectively forming a photosensitive resin pattern corresponding to a scanning line also serving as a gate of an insulated gate transistor and an auxiliary signal line on the lift-off layer, and a lift-off layer using the photosensitive resin pattern as a mask. Sequentially etching the first semiconductor layer, the gate insulating layer, and the first metal layer; reducing the film thickness of the photosensitive resin pattern to partially expose the lift-off layer; Photosensitive resin pattern Etching the lift-off layer to partially expose the first semiconductor layer, forming an organic insulating layer on a side surface of the scan line, and depositing a second semiconductor layer containing impurities. Forming an opening on the scanning line outside the image display unit and at both ends of the auxiliary signal line, and selectively removing the second semiconductor layer, the lift-off layer, the first semiconductor layer, and the gate insulating layer; Applying a second metal layer capable of being anodized, selectively removing the second semiconductor layer and the second metal layer on the lift-off layer together with the removal of the lift-off layer, A step of selectively forming source / drain electrodes composed of a stack of a second semiconductor layer and a second metal layer on the first semiconductor layer at both ends and on the insulating substrate; and applying a conductive thin film. Process, including the drain electrode on the insulating substrate and the pixel electrode Selectively forming an opening and a connection layer for connecting the divided auxiliary signal lines including the source electrode, and using the photosensitive resin pattern used for the selective pattern formation of the picture element electrode as a mask to form a picture. Forming an anodic oxide layer on the side surface of the auxiliary signal line, the source electrode excluding the connection layer, the drain electrode excluding the pixel electrode, and the first semiconductor layer containing no impurities while irradiating light while protecting the element electrode; And characterized in that:

With this configuration, not only can a self-aligned insulated gate transistor be obtained, but also the resistance of the signal line can be reliably reduced without lowering the temperature of the process and increasing the number of film forming steps. Can be manufactured.

A fourteenth aspect is the method for manufacturing a liquid crystal image display device according to the sixth aspect, wherein one principal surface on the insulating substrate is
Depositing at least one first metal layer and at least one gate insulating layer and an impurity-free first semiconductor except on a part of the first metal layer at a peripheral portion of the insulating substrate. Forming a photosensitive resin pattern corresponding to a scanning line also serving as a gate of an insulated gate transistor on the lift-off layer; and A step of sequentially etching the lift-off layer, the first semiconductor layer, the gate insulating layer and the first metal layer using the resin pattern as a mask, and a step of partially exposing the lift-off layer by reducing the film thickness of the photosensitive resin pattern When,
Etching the lift-off layer using the photosensitive resin pattern reduced in thickness as a mask to partially expose the first semiconductor layer; forming an organic insulating layer on the side surface of the scan line; Sequentially depositing a second semiconductor layer including a second metal layer capable of being anodically oxidized, and removing the second semiconductor layer on the lift-off layer together with the second semiconductor layer on the lift-off layer.
And selectively removing the metal layer of the first and second metal layers, and forming a pair of source and source layers comprising a stack of a second semiconductor layer and a second metal layer on the first semiconductor layer at both ends on the gate and on the insulating substrate. A step of selectively forming a drain electrode; a step of forming an opening on a scan line in a region outside the image display portion and selectively removing a gate insulating layer on the scan line; 3
Applying a metal layer, and selectively forming a signal line including a third metal layer including the source electrode;
A step of applying a conductive thin film, a step of selectively forming a pixel electrode including the drain electrode on an insulating substrate, and a step of forming a photosensitive resin pattern used for selective pattern formation of the pixel electrode. Forming an anodized layer on a signal line, a source electrode excluding the signal line, a drain electrode excluding the pixel electrode, and a first semiconductor layer containing no impurities while irradiating light while protecting the pixel electrode as a mask; And characterized in that:

According to this configuration, not only a self-aligned insulated gate transistor can be obtained, but also the process can be performed at a low temperature and the resistance of the signal line can be reduced, so that a large-screen device can be easily manufactured.

A fifteenth aspect of the present invention is also the method of manufacturing a liquid crystal image display device according to the sixth aspect, wherein one principal surface on the insulating substrate is
Depositing at least one first metal layer and at least one gate insulating layer and an impurity-free first semiconductor except on a part of the first metal layer at a peripheral portion of the insulating substrate. Forming a photosensitive resin pattern corresponding to a scanning line also serving as a gate of an insulated gate transistor on the lift-off layer; and A step of sequentially etching the lift-off layer, the first semiconductor layer, the gate insulating layer and the first metal layer using the resin pattern as a mask, and a step of partially exposing the lift-off layer by reducing the film thickness of the photosensitive resin pattern When,
Etching the lift-off layer using the photosensitive resin pattern reduced in thickness as a mask to partially expose the first semiconductor layer; forming an organic insulating layer on the side surface of the scan line; Sequentially depositing a second semiconductor layer including a second metal layer capable of being anodically oxidized, and removing the second semiconductor layer on the lift-off layer together with the second semiconductor layer on the lift-off layer.
Selectively removing the metal layer of the first and second layers; and forming a pair of source and source layers each comprising a stack of a second semiconductor layer and a second metal layer on the first semiconductor layer at both ends on the gate and on the insulating substrate. Selectively forming a drain electrode, applying one or more third metal layers capable of being anodized, and selectively forming a signal line including a third metal layer including the source electrode. Forming, and selectively removing a gate insulating layer on the scanning line by forming an opening on the scanning line in a region outside the image display unit,
A step of applying a conductive thin film, a step of selectively forming a pixel electrode including the drain electrode on an insulating substrate, and a step of forming a photosensitive resin pattern used for selective pattern formation of the pixel electrode. Forming an anodized layer on a signal line, a source electrode excluding the signal line, a drain electrode excluding the pixel electrode, and a first semiconductor layer containing no impurities while irradiating light while protecting the pixel electrode as a mask; And characterized in that:

With this configuration, not only can a self-aligned insulated gate transistor be obtained, but also the process can be performed at a low temperature and the resistance of the signal line can be reduced, and a large-screen device can be easily manufactured.

A sixteenth aspect of the present invention is the method for manufacturing a liquid crystal image display device according to the seventh aspect, wherein one principal surface on the insulating substrate is
Depositing at least one first metal layer and at least one gate insulating layer and an impurity-free first semiconductor except on a part of the first metal layer at a peripheral portion of the insulating substrate. Forming a photosensitive resin pattern corresponding to a scanning line also serving as a gate of an insulated gate transistor on the lift-off layer; and A step of sequentially etching the lift-off layer, the first semiconductor layer, the gate insulating layer and the first metal layer using the resin pattern as a mask, and a step of partially exposing the lift-off layer by reducing the film thickness of the photosensitive resin pattern When,
Etching the lift-off layer using the photosensitive resin pattern reduced in thickness as a mask to partially expose the first semiconductor layer; forming an organic insulating layer on the side surface of the scan line; Sequentially depositing a second semiconductor layer including a second metal layer capable of being anodically oxidized, and removing the second semiconductor layer on the lift-off layer together with the second semiconductor layer on the lift-off layer.
Selectively removing the metal layer of the first and second layers, and separating the drain electrode formed of a stack of the second semiconductor layer and the second metal layer on the first semiconductor layer at both ends on the gate and on the insulating substrate. Forming the source (signal line) electrode selectively and exposing the scanning line except for between the source and drain electrodes and under the source and drain electrode; and exposing the scanning line and the gate on the exposed portion in the image display portion. Forming an organic insulating layer on the substrate, applying a conductive thin film, and connecting a pixel electrode including the drain electrode and a source electrode divided including the source electrode on the insulating substrate. And forming a source electrode and a picture element except for a connection layer while irradiating light while protecting the picture element electrode using the photosensitive resin pattern used as a mask for the selective pattern formation of the picture element electrode. Drain excluding elementary electrodes Characterized by a step of forming an anodic oxide layer on the first semiconductor layer not containing the poles and impurities.

According to this configuration, not only can a self-aligned insulated gate transistor be obtained, but also in addition to lowering the process temperature, the rationalization of devices and processes is promoted, and the number of photolithography steps is reduced. A device can be manufactured with a single photomask.

A seventeenth aspect is the method for manufacturing a liquid crystal image display device according to the eighth aspect, wherein one or more anodically oxidizable first metal layers are deposited on one main surface of the insulating substrate. A step of depositing a lift-off layer after sequentially depositing at least one gate insulating layer and a first semiconductor layer containing no impurities on a peripheral portion of the insulating substrate except for a part of the first metal layer. And a step of selectively forming a photosensitive resin pattern corresponding to a scanning line and an auxiliary signal line also serving as a gate of an insulated gate transistor on the lift-off layer, and a lift-off layer using the photosensitive resin pattern as a mask, Sequentially etching the first semiconductor layer, the gate insulating layer and the first metal layer; reducing the thickness of the photosensitive resin pattern to partially expose the lift-off layer; Resin pattern Etching a lift-off layer to partially expose the first semiconductor layer, forming an organic insulating layer on a side surface of the scan line, and anodizing the second semiconductor layer containing impurities. Sequentially depositing a second metal layer, selectively removing the second semiconductor layer and the second metal layer on the lift-off layer together with the removal of the lift-off layer, A source / drain electrode formed by laminating a second semiconductor layer and a second metal layer is selectively formed on the first semiconductor layer and the insulating substrate, and between the source / drain electrode and below the source / drain electrode. Exposing the scanning lines and auxiliary signal lines except for forming an organic insulating layer on the exposed scanning lines and gates in the image display unit, applying a conductive thin film, A pixel electrode including the drain electrode And a connection layer for connecting a source electrode including both ends of the auxiliary signal line, and a pixel electrode using the photosensitive resin pattern used for the selective pattern formation of the pixel electrode as a mask. Forming an anodic oxide layer on the source electrode excluding the connection layer, the auxiliary signal line, the drain electrode excluding the picture element electrode, and the first semiconductor layer containing no impurities while irradiating light while protecting the semiconductor device. It is characterized by.

With this configuration, not only can a self-aligned insulated gate transistor be obtained, but also, in addition to lowering the temperature of the process, the rationalization of devices and processes is promoted, and the number of photolithography steps is reduced. The device can be manufactured with a single photomask, and the resistance of the wiring can be reduced, thereby promoting the manufacture of a large-screen device.

In a eighteenth aspect of the present invention, there is provided a method of manufacturing a liquid crystal image display device according to the ninth aspect, wherein one principal plane on the insulating substrate is provided.
Depositing at least one first metal layer, and one or more gate insulating layers and a first semiconductor containing no impurities except for a part of the first metal layer at a peripheral portion of the insulating substrate. Forming a photosensitive resin pattern corresponding to a scanning line pattern also serving as a gate of an insulated gate transistor on the lift-off layer; and Sequentially etching a lift-off layer, a first semiconductor layer, a gate insulating layer, and a first metal layer using a conductive resin pattern as a mask; forming an organic insulating layer on a side surface of the scan line; Retreating the resin pattern to partially expose the lift-off layer; etching the lift-off layer using the retreated photosensitive resin pattern as a mask to partially expose the first semiconductor layer; Feeling Retreating the conductive resin pattern to partially expose the lift-off layer, and using the recessed photosensitive resin pattern as a mask to sequentially etch the lift-off layer to partially expose the first semiconductor layer. Sequentially depositing a second semiconductor layer containing impurities and a second metal layer capable of being anodized after removing the photosensitive resin pattern, and removing the lift-off layer and removing the second semiconductor on the lift-off layer. Selectively removing the layer and the anodically oxidizable second metal layer; and forming a second semiconductor layer and a second metal layer on the first semiconductor layer at both ends on the gate and on the insulating substrate. A step of selectively forming a pair of source / drain electrodes composed of a stack of layers and exposing scanning lines except between the source / drain electrodes and below the source / drain electrodes; and Gate Forming an organic insulating layer on the substrate, applying one or more third metal layers capable of being anodized, and selectively forming a signal line made of a third metal layer including the source electrode. , A step of applying a conductive thin film, a step of selectively forming a pixel electrode including the drain electrode on an insulating substrate, and a step of selectively forming a pixel electrode on the insulating substrate. While irradiating light while protecting the picture element electrodes using the conductive resin pattern as a mask, the anodic oxide layer is formed on the signal line, the source electrode excluding the signal line, the drain electrode excluding the picture element electrode, and the first semiconductor layer containing no impurities. And a step of forming

According to this configuration, not only can a self-aligned insulated gate transistor be obtained, but also, in addition to lowering the process temperature, the rationalization of devices and processes is promoted, and the number of photolithography steps is reduced. The device can be manufactured with a single photomask, and the resistance of the wiring is surely reduced, thereby promoting the manufacture of a large-screen device.

[0075]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Claim 1 shows the basic structure of an insulated gate transistor as a skeleton of the present invention, and its positioning as a component of a liquid crystal image display device will be described in detail in the embodiments. . 1 to 1 show an embodiment of the present invention.
8 will be described. FIG. 1 is a plan view of a semiconductor device (active substrate) for an image display device according to a first embodiment of the present invention, and FIG. 2 is a view showing a manufacturing process on lines AA ′ and BB ′ in FIG. FIG. Similarly, the second embodiment is shown in FIGS. 3 and 4, the third embodiment is shown in FIGS. 5 and 6, the fourth embodiment is shown in FIGS. 7 and 8, and the fifth embodiment is shown in FIGS. ,
The sixth embodiment is shown in FIGS. 11 and 12, the seventh embodiment is shown in FIGS. 13 and 14, the eighth embodiment is shown in FIGS.
17A and 17B are a plan view of an active substrate and a cross-sectional view of a manufacturing process, respectively, in FIGS. The same parts as those in the conventional example are denoted by the same reference numerals, and detailed description is omitted.

In the first embodiment of the present invention, that is, in the method of manufacturing an active substrate according to claim 10, first,
As shown in FIG. 2A, a glass substrate 2 which is an insulating substrate
A first metal layer 80 having a thickness of about 0.1 to 0.5 μm is deposited on one main surface of the substrate by using a vacuum film forming apparatus such as SPT (sputtering). The film thickness is a main determining parameter of the screen size and definition of the liquid crystal display device. AL considering low resistance
Is overwhelmingly preferable, but considering that the heat resistance of the AL alone is poor, in order to reduce the resistance of the scanning line, the scanning line may be composed of a single layer of AL (Zr, Ta) alloy or AL / Ta, Ta
A laminated configuration such as / AL / Ta, AL / Ti, Ti / AL / Ti, and AL / AL (Zr, Ta) can be selected. Note that AL (Zr, Ta) means an AL-based alloy to which Zr, Ta or the like is added in an amount of several percent or less in order to improve heat resistance. In FIG. / AL (Z
r) illustrates a two-layer configuration. Next, a first SiNx (silicon nitride) layer serving as a gate insulating layer and a first semiconductor layer serving as a channel of an insulated gate transistor are formed on the entire surface except for a part of the peripheral portion of the glass substrate 2 by using a PCVD apparatus. An amorphous silicon layer containing almost no impurities and two types of thin film layers are sequentially deposited to a thickness of, for example, about 0.3 to 0.05 μm to obtain 30 and 31. Further, on the first amorphous silicon layer 31 as a lift-off layer, for example, a film thickness of 0.2 μm
A Mo (molybdenum) layer 40 is deposited.

Subsequently, as shown in FIG. 2B, a photosensitive resin pattern 41 corresponding to a gate (and a common capacitance line) also serving as a scanning line is selectively formed with a film thickness of, for example, about 2 μm by a fine processing technique. Form. And the photosensitive resin pattern 4
1 is used as a mask, the molybdenum layer 40, the first amorphous silicon layer 31, the gate insulating layer 30, and the first metal layer 80 are sequentially etched to form 40 ′, 31 ′, 30 ′ and the scanning line 11 ( And a common capacitance line 16). At this time, as shown in FIG. 26, the wiring paths 82 (and 83) connecting the leading ends of the scanning lines 11 (and the common capacitance lines 16) in an area outside the image display unit.
It is necessary that the wiring path includes the first metal layer 80 ′ exposed at a part of the peripheral portion of the glass substrate 2 as described above. Note that this wiring path 82
Disconnects the scanning line 1 somewhere in the subsequent manufacturing process.
It is needless to say that if not separated one by one, not only the electrical inspection of the active substrate 2 but also the actual operation as a liquid crystal image display device will be hindered. However, the common capacitance line 16
Do not need to be released from the wiring path 83 that connects them in parallel. In this step, since a plurality of types of thin films are etched, it is reasonable to employ dry etching using a gas, and it is preferable to control the taper of the cross section of the multilayer film.

Subsequently, the film thickness of the photosensitive resin pattern 41 is reduced by, for example, about 0.5 μm to 41 ′ by a treatment in an oxygen gas plasma, and then the photosensitive resin pattern 41 is formed as shown in FIG. Using the 41 ′ as a mask, the molybdenum layer 40 ′ is etched to partially expose the first amorphous silicon layer 31 ′ (about 0.5 μm on one side). In order to enhance the lift-off function of the molybdenum layer 40 ″ after the etching, the molybdenum layer 40 ′ is etched by a RIE (Reactive-Ion-Etch) method having a strong anisotropy so that its cross-sectional shape is sharp. It is necessary to adopt dry etching.

Thereafter, the photosensitive resin pattern 41 ′ is removed, and then a direct current is applied to the first metal layer 80 ′ exposed at a part of the peripheral portion of the glass substrate 2 shown in FIG. Electrodeposition is performed in an electrodeposition solution while giving a + (plus) potential, and an organic insulating layer 71 is formed on the side surface of the gate 11 as shown in FIG. The thickness of the organic insulating layer 71 is 0.5
μm or more is required.

Here, the organic insulating thin film and its manufacturing method will be described in detail. Among materials that can be electrodeposited as an organic insulating thin film that can secure the insulating properties necessary for a device, as described in the literature Electronology C-112 Vol. 0.01% salt
The solution containing the solution was used as an electrodeposition solution, and + (plus) was added to the scanning line 11.
When the electrodeposition is performed by applying a potential, the polyimide layer 71 can be selectively formed on the side surface of the gate 11 as shown in FIG. The electrodeposition voltage is about several volts and the polyimide layer 7
It is easy to make the thickness of 1 more than 0.5 μm. After the formation of the polyimide layer 71, preferably 200 to 300 ° C., several minutes to several
Insulation properties and chemical resistance of the polyimide layer 71 by performing a heat treatment for 10 minutes (for example, there is a step of removing the photosensitive resin pattern in a subsequent step, and the organic insulating thin film needs to have resistance to chemicals such as a resist stripping solution) ) May be increased, but the required insulation characteristics are governed by the heat resistance of the insulated gate transistor and the composition of the liquid crystal material. Therefore, the optimum heating conditions may be determined experimentally.

After the organic insulating layer 71 is formed on the side surface of the gate 11, as shown in FIG. 2E, a second semiconductor layer containing impurities is formed using a PCVD apparatus to a thickness of 0.05 μm containing phosphorus, for example. A Ti thin film 34 having a thickness of, for example, about 0.1 μm is deposited on the entire surface of the amorphous silicon layer 33 and the source / drain metal electrode layers using an SPT apparatus. Then, the thickness of the lift-off layer 40 ″ is 0.2 μm, which is thicker than the lamination of the amorphous silicon layer 33 and the Ti thin film 34. It is easy to cause disconnection in the part. After this,
When the insulating substrate 2 is left in a hydrogen peroxide solution containing a small amount of diluted nitric acid or ammonia, the molybdenum layer 40 "disappears, and the amorphous silicon layer 33 containing phosphorus and the Ti thin film 34 on the molybdenum layer 40" Amorphous silicon layer 31 ″ which is selectively lifted off (peeled off) and contains no impurities
Is exposed.

Subsequently, as shown in FIG. 2F, the amorphous silicon containing phosphorus is formed on the amorphous silicon layer 31 ′ containing no impurities on the gate 11 and on the insulating substrate 2 by the fine processing technique. A pair of source (signal line) / drain electrodes 12 ′ and 21 formed by laminating a layer 33 ′ and a Ti thin film 34 ′ are selectively formed. Since the signal line 12 'has already disappeared, the signal line 12' is divided and formed on the scanning line 11 as shown in FIG. At the time of etching the amorphous silicon layer 33 ′, the amorphous silicon layer 31 ′ containing no impurities on the scanning line 11 (and the common capacitance line 16) is removed by over-etching to remove the scanning line 11 (and the common capacitance line 16). Exposing the upper gate insulating layer 30 'is important to prevent formation of a parasitic transistor.

Subsequently, as shown in FIG. 2G, a transparent insulating layer having a thickness of about 0.3 μm was formed on the entire surface of the glass substrate 2 by using a PCVD apparatus in the same manner as the gate insulating layer.
The passivation insulating layer 37 is formed by depositing an iNx layer.
An opening 61 is formed on both ends of the signal line 12 ′ separated by the fine processing technology, and an opening 62 is formed on the drain electrode 21.
An opening 63 is formed at a position where the terminal electrode 6 of the scanning line 11 is formed, and an opening 64 is also formed at a position where the terminal electrode 5 of the signal line 12 is formed. Part 6
2 to remove the passivation insulating layer 37 and remove the signal line 1
2 'and the drain electrode 21 are partially exposed to form an opening 63.
The passivation insulating layer 37 and the gate insulating layer 30 in the inside are removed to partially expose the scanning line 11, and the opening 6 is further removed.
4 to remove the passivation insulating layer 37 and remove the signal line 1
2 'is also partially exposed.

Finally, as shown in FIG. 2H, the entire surface of the glass substrate 2 is coated with a film having a thickness of 0.
As a transparent conductive layer of about 1 to 0.2 μm, for example, ITO (Indiu
m-Tin-Oxide), and the drain electrode 21 in the opening 62 is formed on the passivation insulating layer 37 by a fine processing technique.
And a connection layer 91 interconnecting the separated signal lines 12 ′ including the pixel electrodes 22 and the signal lines (source electrodes) 12 ′ in the openings 61.
(Semiconductor device for image display device).

As to the configuration of the scanning line terminal electrode 6, when forming the picture element electrode 22, the transparent conductive terminal electrode 6 'may be formed so as to include a part of the exposed scanning line 11 in the opening 63. Alternatively, part of the scanning line 11 exposed in the opening 63 by removing the transparent conductive layer may be used as the terminal electrode 6. Regarding the configuration of the terminal electrode 5 of the signal line, the exposed signal line 1 in the opening 64 when the pixel electrode 22 is formed.
The transparent conductive terminal electrode 5 ′ may be formed to include a part of the signal line 12 ′. You can also. Generally, the signal line 12 'is left while leaving the transparent conductive layer.
And the terminal electrode 6 ′ of the scanning line 11 are formed.
In addition, it is likely that these terminal electrodes are connected by a transparent conductive layer to provide a short-circuit line for countermeasures against static electricity. The active substrate 2 thus obtained and the color filter are bonded together to form a liquid crystal panel, and the first embodiment of the present invention is completed.

As for the configuration of the storage capacitor 15, FIG. 1 shows an example in which the pixel electrode 22 and the preceding scanning line 11 are formed via the gate insulating layer 30 ′.
The configuration of the pixel electrode 22 is not limited to this.
And the storage capacitor line 16. However, when the storage capacitor line 16 is introduced, the signal line 12 ′ that intersects like the scanning line 11 is divided, so that a new connection layer is required (see FIG. 27). Other configurations are also possible, but detailed description is omitted.

In the first embodiment, the impurity is contained between the amorphous silicon layer 31 ′ containing no impurity and the source / drain electrodes 12 and 21, similarly to the conventional etch-stop type insulated gate transistor. Since the amorphous silicon layer 33 'is interposed, the source / drain electrode material is AL.
Since a single layer cannot be adopted and a metal layer having high heat resistance must be selected, and the thickness of the source / drain electrodes cannot be increased due to the response to lift-off, wiring resistance becomes an issue. There remains a problem that is limited by the formation of devices with a diagonal of 50 cm or less. Therefore, in the second embodiment, the resistance of the signal line is reduced by newly providing a signal line.

In the second embodiment, that is, in the method of manufacturing an active substrate according to the eleventh aspect, as shown in FIG. 4F, the first embodiment is performed up to the formation of the source / drain electrodes 12 ″ and 21. Thereafter, using a vacuum film forming apparatus such as SPT, an AL thin film layer 35 having a thickness of about 0.3 μm as a low-resistance wiring layer, and
A heat-resistant metal thin film layer 36 of Ti, Ta, Cr or the like is sequentially deposited as an intermediate conductive layer of about μm. Then, these two metal layers are sequentially etched by using a photosensitive resin pattern by a fine processing technique, and as shown in FIG. 4 (g), the signal line 12 including the source electrode 12 ″ of the insulated gate transistor Are formed selectively.

Further, as shown in FIG. 4H, a passivation insulating layer is formed on the entire surface of the glass substrate 2 by applying a SiNx layer having a thickness of about 0.3 μm as a transparent insulating layer using a PCVD apparatus. 37, an opening 63 is formed on the position where the opening 62 and the terminal electrode 6 of the scanning line 11 are formed on the drain electrode 21 and an opening 64 is also formed on the position where the terminal electrode 5 of the signal line 12 is formed. Then, the insulating layer in the opening is removed to expose the drain electrode 21, the scanning line 11, and a part of the signal line 12.

Finally, as shown in FIG. 4 (i), the entire surface of the glass substrate 2 is processed to a film thickness of 0.5 using a vacuum film forming apparatus such as SPT.
As a transparent conductive layer of about 1 to 0.2 μm, for example, ITO (Indiu
m-Tin-Oxide) and the opening 6
The picture element electrode 22 is selectively formed on the passivation insulating layer 37 including the drain electrode 21 in 2 to complete the active substrate 2. The configuration of the terminal electrodes 6 of the scanning lines and the terminal electrodes 5 of the signal lines can be selected in the same manner as in the first embodiment. The active substrate 2 thus obtained and the color filter are bonded together to form a liquid crystal panel, thereby completing the second embodiment of the present invention.

Regarding the configuration of the storage capacitor 15, an example in which the storage electrode 21 ′ including the drain electrode 21 and formed simultaneously with the signal line 12 and the storage capacitor line 16 are formed via the gate insulating layer 30 ′. Although illustrated in FIG. 3, the configuration of the storage capacitor 15 is not limited to this, and the pixel electrode 2
A configuration between the scanning line 2 and the preceding scanning line 11 is also possible. Other configurations are also possible, but detailed description is omitted.

In the first and second embodiments, a conventional SiNx layer formed by PCVD is adopted as the passivation insulating layer. However, passivation that can be formed at a low temperature of 200 ° C. or less is also possible. In the third embodiment, that is, in the method of manufacturing an active substrate according to the twelfth aspect, as shown in FIG. 6F, the amorphous silicon layer 31 ′ containing no impurities on the gate 11 by the fine processing technique. Until a pair of source (signal line) / drain electrodes 12 ′ and 21 composed of a stack of an amorphous silicon layer 33 ′ containing phosphorus and a Ta thin film 34 ′ are formed selectively on the upper surface and on the insulating substrate 2. The process proceeds in the same manufacturing process as in the first embodiment. However, unlike the first and second embodiments, the source / drain electrodes 12 ′ and 21 also need to be made of an anodizable metal.
Silicides such as a, W, and Mo are selected. Since the film thickness is reduced by anodic oxidation, the film is formed to be slightly thicker, for example, about 0.15 μm. The amorphous silicon layer 31 'containing no impurities is formed to be slightly thicker, for example, about 0.1 μm for the reason described later.

Subsequently, as shown in FIG. 6G, an opening 63 is formed on the scanning line 11 at a position where the terminal electrode 6 is to be formed, and the gate insulating layer 30 'is etched to form the scanning line 11. Expose a part of.

Subsequently, as shown in FIG. 6 (h), a transparent conductive layer having a thickness of about 0.1 to 0.2 μm is formed on the entire surface of the glass substrate 2 by using a vacuum film forming apparatus such as SPT, for example, as ITO (I).
signal line 1 including a drain electrode 21 and a picture element electrode 22 and a signal line (source electrode) 12 ′ on an insulating substrate 2 by fine processing technology.
A connection layer 91 for interconnecting 2 'is selectively formed. Then, while irradiating light using the photosensitive resin pattern 65 used for the selective pattern formation of the connection layer 91 and the pixel electrode 22 as a mask, the signal line 12 ′ (source electrode) except the connection layer 91 and the pixel electrode 22 are connected. The removed drain electrode 21 and the amorphous silicon layer 31 'containing no impurities are anodized to form these oxide layers. The thickness of the anodized layer is 0.1 μm
That's enough. At this time, a silicon oxide layer (SiO 2) 6 serving as an insulating layer is formed on the amorphous silicon layer 31 ″ containing no impurity to be a channel of the insulated gate transistor.
6 and an amorphous silicon layer 3 containing impurities.
On the side surface 3 ', a silicon oxide layer (SiO2) 67 containing impurities, which is also an insulating layer, is formed. That is, the amorphous silicon layer 31 ″ containing no impurity is reduced in film thickness by an amount corresponding to the amount of the silicon oxide layer (SiO 2) 66 formed on the surface thereof. Unlike the second embodiment, the amorphous silicon layer 31 containing no impurities needs to be formed to be slightly thicker as described above.

When Ta is used as the source / drain electrode material, the surface of the signal line 12 'and the drain electrode 21 excluding the picture element electrode 22 are formed on the drain electrode 21 as an insulating layer by anodic oxidation.
Tantalum oxide (Ta2O5) 68 is formed. A point to be noted in anodic oxidation of the source / drain electrodes 12 ′ and 21 is that although not shown, all the signal lines 12 ′ need to be formed electrically in parallel or in series. If this series-parallel connection is not released, it goes without saying that not only the electrical inspection of the active substrate 2 but also the actual operation of the liquid crystal image display device is hindered.

Further, unless the resistance of the channel semiconductor layer of the insulated gate transistor is reduced by irradiating a strong light of preferably 10,000 lux or more, the thickness of the anodic oxide layer on the drain electrode 21 becomes thin. Caution must be taken. The signal line 12 'need only be anodized only in the image display area. In order to prevent the anodized layer from being formed in the terminal electrode formation region at the end of the signal line 12', a prior patent is disclosed. It is recommended to use an in-substrate selective electrochemical treatment apparatus as disclosed in JP 2000-107577.

The reason that the pixel electrode 22 is covered with the photosensitive resin pattern 65 is not only that the pixel electrode 22 does not need to be anodized, but also that the formation current that flows to the drain electrode 21 via the insulated gate transistor is used. This is because it is not necessary to secure the value larger than necessary. In addition, since the electrode on the terminal 6 of the scanning line 11 is electrically floating (neutral) at the time of the anodic oxidation, even if the terminal electrode 6 is exposed, no anodic oxidation layer is formed, and If the terminal electrode is formed of the transparent conductive layer 6 ', no problem arises as in the case of the pixel electrode 22 because the terminal electrode is covered with the photosensitive resin. As described above, if the selective anodic oxidation in the glass substrate 2 is performed, as shown in FIG.
Part of 2 ′ can be used as the terminal electrode 5. In a conventional anodic oxidation method in which the entire glass substrate 2 is immersed in a chemical conversion solution, the signal line 1 is used unless an appropriate mask material is used in combination.
2 'cannot be selectively anodized, and as shown separately in FIG. 5, a terminal electrode 5' made of a transparent conductive layer is formed including a part of the signal line 12 'in a region outside the image display portion. Will be done. This configuration is the same as the connection configuration between the picture element electrode 22 and the drain electrode 21 shown in FIG.

Regarding the configuration of the scanning line terminal electrode 6, the transparent conductive terminal electrode 6 'may be formed so as to include a part of the exposed scanning line 11 in the opening 63 when the pixel electrode 22 is formed. Alternatively, the transparent conductive layer can be removed and a part of the scanning line 11 exposed in the opening 63 can be used as the terminal electrode 6. Avoiding exposure of dissimilar metals can easily avoid side effects due to the battery effect. As described above, the terminal electrode 5 ′ of the signal line is also formed of a transparent conductive layer, and it is safe to connect the terminal electrode 5 ′ and the terminal electrode 6 ′ with the transparent conductive layer to form a short-circuit line for preventing static electricity. It is a choice.

Finally, the photosensitive resin pattern 65 is removed to complete the active substrate 2 as shown in FIG. The active substrate 2 thus obtained and the color filter are bonded together to form a liquid crystal panel, thereby completing the third embodiment of the present invention.

In the third embodiment described above, similarly to the conventional etch stop type insulated gate transistor, the amorphous silicon layer containing no impurity and the amorphous silicon layer containing the impurity are located between the source / drain electrodes. Although the silicon layer is interposed, the passivation
As the drain electrode material, a low-resistance AL single layer other than Ta can be used as the anodizable metal layer. It is necessary to add Nd to AL in order to avoid the disappearance or film loss of these electrodes. It is also possible to use a stack of a Ta layer and a low-resistance AL layer as a source / drain electrode material. In addition, since the AL is soft, the lift-off is likely to be difficult. Therefore, there is a restriction that the chemical liquid must be strongly jetted at the time of the lift-off.

As described above, in the third embodiment, it is not so easy to increase the thickness of the source / drain electrodes, and there remains a problem that the wiring resistance is a problem which is restricted by the formation of a device with a diagonal of 50 cm or less. Therefore, in the fourth embodiment, the multilayer wiring technology is introduced to promote the reduction in the resistance of the signal line.

In the fourth embodiment, that is, in the method of manufacturing an active substrate according to the thirteenth aspect, as shown in FIG.
Until 1 is formed, the process proceeds in the same manufacturing process as in the first embodiment. However, as shown in FIG.
This is also different from the third embodiment in that it is formed simultaneously with the scanning line 11.

Subsequently, as shown in FIG. 8E, an amorphous silicon layer 33 containing, for example, phosphorus and having a thickness of about 0.05 μm is deposited as a semiconductor layer containing impurities using a PCVD apparatus.

Subsequently, as shown in FIG. 8F, the opening 63 is formed on the position where the terminal electrode 6 of the scanning line 11 is formed by the fine processing technique, and the opening 6 is formed at both ends of the auxiliary signal line 92.
1 and the semiconductor layer 3 containing impurities in the opening.
3, lift-off layer 40 "and impurity-free semiconductor layer 3
1 'and the gate insulating layer 30' are removed to expose the scanning line 11 and a part of the auxiliary signal line 92.

Further, as a source (signal line) / drain electrode material, anodization can be performed by using an SPT device, for example, with a film thickness of 0.1 mm.
A Ta thin film 34 of about 15 μm is deposited on the entire surface. After this,
When the insulating substrate 2 is left in a hydrogen peroxide solution containing a small amount of diluted nitric acid or ammonia, the molybdenum layer 40 ″ disappears as shown in FIG.
The Ta thin film 34 on the molybdenum layer 40 "and the amorphous silicon layer 33 containing impurities are selectively lifted off (peeled off), and the amorphous silicon layer 31" containing no impurities constituting the channel of the insulated gate transistor is provided. Is exposed. At the same time, the insides of the openings 61 and 63 are covered with a Ta thin film.

Thereafter, as shown in FIG. 8H, the amorphous silicon containing phosphorus is formed on the amorphous silicon layer 31 ′ containing no impurities on the gate 11 and the insulating substrate 2 by the fine processing technique. A pair of source (signal line) / drain electrodes 12 ″ and 21 composed of a stack of a layer 33 ′ and a Ta thin film 34 ′ are selectively formed. The impurity-free amorphous silicon layer 31 'on the gate line 11 is removed to remove the gate insulating layer 3 on the scan line 11.
Expose 0 '. In order to leave the Ta thin film in the opening 63, a photosensitive resin may be left around the opening 63 and the periphery thereof during the above-mentioned fine processing.

Then, as shown in FIG. 8 (i), the entire surface of the glass substrate 2 is processed to a film thickness of 0.5 using a vacuum film forming apparatus such as SPT.
As a transparent conductive layer of about 1 to 0.2 μm, for example, ITO (Indiu
m-Tin-Oxide), and the auxiliary signal line 9 divided including the pixel electrode 22 including the drain electrode 21 and the opening 61 of the auxiliary signal line 92 on the insulating substrate 2 by the fine processing technique.
A connection layer 91 interconnecting the two is selectively formed. Then, while irradiating light using the photosensitive resin pattern 65 used for the selective pattern formation of the connection layer 91 and the pixel electrode 22 as a mask, the side surface of the auxiliary signal line 92 and the signal line 12 ″ excluding the connection layer 91 (source electrode) ), The drain electrode 21 excluding the picture element electrode 22 and the amorphous silicon layer 3 containing no impurities
1 "is anodized to form oxide layers of these thin films in the same manner as in the third embodiment. Since the first metal layer is exposed on the side surface of the auxiliary signal line 92, it is preferable to use the above-described method. As described above, it is preferable to select an anodic oxidizable material for the first metal layer in order to provide insulation by the anodic oxide layer.

Regarding the configuration of the terminal electrodes of the signal lines, if the selective anodic oxidation in the glass substrate 2 is performed as described above, the signal lines 1 in the region outside the image display section as shown in FIG.
A part of 2 "can be used as the terminal electrode 5. In a conventional anodic oxidation method in which the entire glass substrate 2 is immersed in a chemical conversion solution, the signal line 1 is used unless an appropriate mask material is used in combination.
2 "cannot be selectively anodized, and as shown separately in FIG. 7, the terminal electrode element 5 'made of a transparent conductive layer in a region outside the image display portion includes a part of the signal line 12". Will be formed. This configuration is the same as the connection between the picture element electrode 22 and the drain electrode 21 shown in FIG.
Further, part of the terminal electrode 9 made of the same material as the scanning line 9
It is also possible to obtain a terminal electrode 5 'made of 2' or a transparent conductive layer formed including the same.

Regarding the configuration of the scanning line terminal electrode 6, the transparent conductive terminal electrode 6 ′ including the Ta thin film in the opening 63 can be formed when the picture element electrode 22 is formed, or the transparent conductive layer can be formed. And the Ta thin film in the opening 63 can be used as the terminal electrode 6.

Finally, the photosensitive resin pattern 65 is removed to complete the active substrate 2 as shown in FIG. The active substrate 2 thus obtained and the color filter are bonded to form a liquid crystal panel, thereby completing the fourth embodiment of the present invention.

The fifth embodiment is similar to the second embodiment except that a manufacturing process for easily forming a low-resistance signal line is added to the third embodiment in order to facilitate fabrication of a large-screen device. is there. In the fifth embodiment, that is, in the method for manufacturing an active substrate according to the fourteenth aspect, as shown in FIG. A pair of source (signal line) / drain electrodes 1 composed of a stack of an amorphous silicon layer 33 'containing phosphorus and a Ta thin film 34' on the upper surface and on the insulating substrate 2
Until the 2 ″ and 21 are selectively formed, the process proceeds in the same manufacturing process as in the third embodiment.

Subsequently, as shown in FIG. 10 (g), an opening 63 is formed on the scanning line 11 at a position where the terminal electrode 6 is formed, and the gate insulating layer 30 'is etched to form the scanning line 11 Expose a part of.

Subsequently, the AL thin film layer 35 having a thickness of about 0.3 μm was formed as a low resistance wiring layer using a vacuum film forming apparatus such as SPT.
Then, a heat-resistant metal thin film layer 36 of Ta or the like is further sequentially deposited as an intermediate conductive layer having a thickness of about 0.1 μm. These two layers are sequentially etched using a photosensitive resin pattern by a fine processing technique, and as shown in FIG. 10 (h), the signal line 12 including the source electrode 12 ″ of the insulated gate transistor is selectively formed. The signal line 12 can be formed as a single AL layer without being laminated with the intermediate conductive layer 36 made of a heat-resistant metal thin film layer of Ta or the like.
In order to avoid disappearance by a developing solution or an alkaline resist stripping solution due to a battery action with the layer, it is necessary to add Nd to AL or to use a special developing solution or resist stripping solution.

At this time, regarding the configuration of the scanning line terminal electrode 6, the AL thin film layer 35 and the heat-resistant metal thin film layer 36 such as Ta
Of the scanning line 11 exposed in the opening 63 by removing the stack of the AL thin film layer 35 and the heat-resistant metal thin film layer 36 of Ta or the like. Can be used as the terminal electrode 6, or the transparent conductive terminal electrode 6 'can be formed in the next step including a part of the scanning line 11 exposed in the opening 63. The AL thin film layer 35 A transparent conductive terminal electrode 6 ′ may be formed by including a laminate 6 ″ of a heat-resistant metal thin film layer 36 of Ta or the like.

After forming the signal lines 12, as shown in FIG. 10 (i), a transparent conductive layer having a thickness of about 0.1 to 0.2 μm is formed on the entire surface of the glass substrate 2 by using a vacuum film forming apparatus such as SPT, for example, ITO. (Indium-Tin-Oxide), and a pixel electrode 22 including a drain electrode 21 is selectively formed on the insulating substrate 2 by a fine processing technique. Then, while irradiating light with the photosensitive resin pattern 65 used for selective pattern formation of the picture element electrodes 22 as a mask, the signal lines 12 and 12 are
And the drain electrode 21 excluding the picture element electrode 22 and the amorphous silicon layer 3 containing no impurities.
1 "is anodized to form these oxide layers. At this time, a silicon oxide layer (SiO2) serving as an insulating layer is formed on the amorphous silicon layer 31 'which does not contain impurities and becomes a channel of the insulated gate transistor. ) 66 is formed, and a silicon oxide layer (SiO 2) 67 containing an impurity, which is also an insulating layer, is formed on the side surface of the amorphous silicon layer 33 ′ containing the impurity. Tantalum pentoxide (Ta2O5) 68, which is an insulating layer, is formed on the surface. Alumina (Al 2 O 3) 6 which is an insulating layer is provided on the side of the signal line 12.
The point that 9 is formed is a difference between the third and fourth embodiments. Needless to say, when an AL alloy layer containing Nd or the like is used for the signal line 12, alumina (Al2O3) 69, which is an insulating layer, is entirely formed on the signal line 12.

By performing selective anodic oxidation in the glass substrate 2, a part of the signal line 12 can be used as the terminal electrode 5 in a region outside the image display section as shown in FIG. In this case, the signal line 12 does not necessarily have to be a laminate of the low resistance wiring layer and the intermediate conductive layer 36, and there is no problem with a single layer of the AL thin film layer 35 as the low resistance wiring layer. However, if the scanning wire is A
In the case of the L-based alloy, the AL thin film layer (6 ″) is also formed on a part of the exposed scanning line 11 (region where the terminal electrode 6 is formed) as shown in FIG. However, when the scanning line material is a laminated layer such as Ta / AL / Ta, it is not necessary because Ta exerts a mask function against the etching of AL. If a conventional anodic oxidation method such as immersion in a chemical conversion solution is used, the signal line 12 cannot be selectively anodized unless an appropriate mask material is used in combination. The terminal electrode 5 'made of a transparent conductive layer in the region is formed to include a part of the signal line 12 (on which the intermediate conductive layer 36' is formed). Is removed to form an active substrate 2 as shown in FIG. To formed. Fifth embodiment of this manner a liquid crystal panel by bonding the active substrate 2 and the color filter obtained by the present invention is completed.

The main manufacturing steps in the fifth embodiment are as follows:
A semiconductor device for an image display device having a heterogeneous configuration can be obtained by performing a step of forming an opening in a gate insulating layer and a step of forming a source / drain electrode, and this will be described below as a sixth embodiment. . In the sixth embodiment, that is, in the method of manufacturing an active substrate according to the fifteenth aspect, as shown in FIG. 6F, an amorphous silicon layer 31 ′ containing no impurities on the gate 11 by the fine processing technique. Until a pair of source (signal line) / drain electrodes 12 ″ and 21 composed of a stack of an amorphous silicon layer 33 ′ containing phosphorus and a Ta thin film 34 ′ are formed on the upper surface and the insulating substrate 2. The process proceeds in the same manufacturing process as in the fifth embodiment.

Subsequently, an AL thin film layer 35 having a thickness of about 0.3 μm is formed as a low-resistance wiring layer using a vacuum film forming apparatus such as SPT.
Then, a heat-resistant metal thin film layer 36 of Ta or the like is further sequentially deposited as an intermediate conductive layer having a thickness of about 0.1 μm. Then, these two metal layers are sequentially etched using a photosensitive resin pattern by a fine processing technique, and as shown in FIG. Is selectively formed.

Subsequently, as shown in FIG. 12 (h), an opening 63 is formed above the position where the electrode terminal 6 of the scanning line 11 is formed.
Is formed, and the gate insulating layer 30 ′ is etched to expose a part of the scanning line 11.

Further, as shown in FIG. 12 (i), the film thickness is
As a transparent conductive layer of about 0.1 to 0.2 μm, for example, ITO (Ind
ium-Tin-Oxide), and a pixel electrode 22 including a drain electrode 21 is selectively formed on the insulating substrate 2 by a fine processing technique.

As for the configuration of the scanning line terminal electrode 6, at this time, a transparent conductive terminal electrode 6 'including a part of the scanning line 11 exposed in the opening 63 can be formed at the same time. A part of the scanning line 11 exposed in the opening 63 by removing the conductive layer may be used as the terminal electrode 6.

Using the photosensitive resin pattern 65 used for selective pattern formation of the pixel electrodes 22 as a mask, the signal lines 12 and the source electrodes 12 ″ excluding the signal lines 12 and the pixel electrodes 22 are irradiated while irradiating light. The drain electrode 21 and the amorphous silicon layer 31 ″ containing no impurities are anodized to form an oxide layer on the surface of these thin films.

By performing selective anodic oxidation in the glass substrate 2, a part of the signal line 12 can be used as the terminal electrode 5 in a region outside the image display section as shown in FIG. In this case, the signal line 12 does not have to be a laminate of the low resistance wiring layer and the intermediate conductive layer 36, and the formation of the signal line 12 is not limited to the opening 63.
Therefore, the signal line 12 is a single layer of the AL thin film layer 35 as a low-resistance wiring layer without any problem even if the scanning line material is an AL-based alloy. With a conventional anodic oxidation method in which the entire glass substrate 2 is immersed in a chemical conversion solution, the signal line 12 cannot be selectively anodized unless an appropriate mask material is used in combination. The terminal electrode 5 ′ made of a transparent conductive layer in a region outside the image display unit is formed including a part of the signal line 12.

Finally, the photosensitive resin pattern 65 is removed to complete the active substrate 2 as shown in FIG. Active substrate 2 thus obtained
And a color filter are bonded to form a liquid crystal panel, thereby completing the sixth embodiment of the present invention.

The manufacturing process can be reduced by rationalizing the process of forming the source (signal line) / drain electrode and the process of forming the opening in the gate insulating layer, which will be described below as a seventh embodiment. I do. In the seventh embodiment, that is, in the method of manufacturing an active substrate according to claim 17, the amorphous silicon layer 3 containing, for example, phosphorus and having a thickness of about 0.05 μm using a PCVD apparatus as the semiconductor layer containing impurities.
After a Ta thin film 34 having a thickness of, for example, about 0.15 μm is deposited on the entire surface using an SPT device as a source (signal line) / drain electrode, an amorphous silicon layer 33 containing phosphorus on the molybdenum layer 40 ″ is formed. Until the Ta thin film 34 is selectively lifted off, the process proceeds in the same manufacturing process as in the third, fifth, and sixth embodiments, and thereafter, as shown in FIGS. Source (signal line) / drain electrode 1 composed of a layered structure of a semiconductor layer 33 containing impurities.
2 ′ and 21 are selectively formed. At this time, due to over-etching of the amorphous silicon layer 33 'or change of the etching material (gas), the amorphous silicon layer 3 containing no impurities on the scanning line 11 is formed.
In addition to 1 ', the gate insulating layer 30' is also removed to remove the source
Between the drain electrodes 12 'and 21 and the source / drain electrode 1
Most of the scanning line 11 is exposed except below the 2 ′ and 21 (at the intersection of the scanning line 11 and the signal line pattern, the scanning line 1 is exposed).
1, the amorphous silicon layer 33 and the Ta thin film 34 have already disappeared, but by leaving the photosensitive resin, the gate insulating layer 30 'is added to the amorphous silicon layer 31' containing no impurities. Can be left). Also in this step, since a plurality of types of thin films are etched, it is reasonable to employ dry etching using gas. As the source / drain electrodes 12 ′ and 21, a low-resistance AL other than Ta can be used as a metal layer which can be anodized. In order to avoid the disappearance by the liquid, it is necessary to add Nd to AL, and to set the thickness 40 of the lift-off layer to be thick because AL is soft.

As a result, the source / drain electrodes 12 ',
21 (the amorphous silicon 31 ′ containing no impurity constituting the channel portion of the insulated gate transistor) and the scanning lines 11 except for the intersections between the scanning lines 11 and the signal line patterns.
Most are exposed. However, since a direct current bias is applied between the scanning line 11 and the counter electrode 14 in the liquid crystal panel state, the scanning line 11 cannot be used as a liquid crystal device when the scanning line 11 is exposed. The scanning line 10 exposed there
6 and the organic insulating layer 7 on the part 105 of the gate by electrodeposition.
2 must be formed. It is sufficient that the thickness is 0.1 μm or more.
5 is disadvantageous in terms of configuration. In this electrodeposition step, the source / drain electrodes 12 ′ and 21 are connected to the scanning line 11 and the gate insulating layer 3.
Since it is electrically insulated through 0 ', no organic insulating layer is formed on the uppermost Ta thin film layer 34' on the source / drain electrodes 12 'and 21. However, in performing the electrodeposition of the exposed scanning line 106 and the gate 105,
The selective electrodeposition step using a photosensitive resin pattern as a mask to prevent an organic insulating layer from being formed on the scanning line 11 in a region where the terminal electrode 6 of the scanning line 11 outside the image display portion is formed is manufactured. Here again, the use of an in-substrate selective electrochemical processing apparatus is recommended because it increases the number of steps.

Subsequently, as shown in FIG. 14 (g), a transparent conductive layer having a film thickness of about 0.1 to 0.2 μm is formed on the entire surface of the glass substrate 2 by using a vacuum film forming apparatus such as SPT, for example, using ITO (I
A source electrode (signal line) 12 ′ including a drain electrode 21, a picture element electrode 22 and a source electrode 12 ′ is formed on the insulating substrate 2 by microfabrication technology. A connection layer 91 for interconnecting is selectively formed.

The photosensitive resin pattern 65 used for selective pattern formation of the connection layer 91 and the pixel electrode 22 is used as a mask to irradiate light while excluding the source electrode 12 ′ except the connection layer 91 and the pixel electrode 22. The drain electrode 21 and the amorphous silicon layer 31 ″ containing no impurities are anodized to form an oxide layer on the surface of these thin films.

Regarding the configuration of the scanning line terminal electrode 6, the transparent conductive terminal electrode 6 'can be formed so as to include a part of the scanning line 11 which is simultaneously exposed at this time. A part of the scanning line 11 that has been removed and exposed can be used as the terminal electrode 6.

By performing selective anodic oxidation in the glass substrate 2, a part of the signal line 12 'can be used as the terminal electrode 5 in a region outside the image display section as shown in FIG. A conventional anodic oxidation method in which the entire glass substrate 2 is immersed in a chemical solution cannot selectively anodize the signal line 12 ′ unless a suitable mask material is used in combination, as shown in FIG. In a region outside the image display section, the terminal electrode 5 'made of a transparent conductive layer is formed including a part of the signal line 12'. This configuration corresponds to the picture element electrode 2 shown in FIG.
2 and the drain electrode 21 are connected in the same manner. Finally, the photosensitive resin pattern 65 is removed, and FIG.
The active substrate 2 is completed as shown in FIG. The active substrate 2 thus obtained and the color filter are bonded together to form a liquid crystal panel, thereby completing the seventh embodiment of the present invention.

Regarding the configuration of the storage capacitor 15, the preceding scanning line 11 (projection 106 of the scanning line) and the pixel electrode 22 are formed via the organic insulating layer 72 formed on the scanning line 11. Although an example is illustrated in FIG. 13, the configuration of the storage capacitor 15 is not limited to this, and may be configured between the pixel electrode 22 and the storage capacitor line 16. Other configurations are also possible, but detailed description is omitted.

Also in the seventh embodiment, it is not so easy to increase the thickness of the source / drain electrodes, and there remains a problem that the wiring resistance is a problem which is restricted to the formation of a device with a diagonal of 50 cm or less. Therefore, in the eighth embodiment, the multilayer wiring technology is introduced to promote the reduction in the resistance of the signal line. In the eighth embodiment, that is, in the method of manufacturing an active substrate according to claim 17, the semiconductor layer containing impurities is formed using a PCVD apparatus, for example, with a thickness of 0.05 containing phosphorus.
μm amorphous silicon layer 33 and source (signal line)
Using an SPT device as the drain electrode, for example, a film thickness of 0.15
After the Ta thin film 34 having a thickness of about μm is deposited on the entire surface, the same manufacturing as that of the seventh embodiment is performed until the amorphous silicon layer 33 containing phosphorus and the Ta thin film 34 on the molybdenum layer 40 ″ are selectively lifted off. However, this embodiment is different from the seventh embodiment in that the auxiliary signal line 92 is formed at the same time as the scanning line 11. Also, since the auxiliary signal line 92 is anodized in a later step, it is formed by anodic oxidation. The point that an insulating layer needs to be formed is also a major difference from the other embodiments.
For the scanning line 11 (auxiliary signal line 92), Ta or AL is selected alone. Alternatively, silicide which is an alloy of Ta, W, Mo, Cr and the like with Si may be used. Considering the low resistance, AL is overwhelmingly preferable, but considering that the heat resistance of the AL alone is poor, the structure of the scanning line is made of AL (Zr, Ta) alloy or the like to reduce the resistance of the scanning line. Layer structure or AL / T
A laminated configuration such as a, Ta / AL / Ta, or AL / AL (Zr, Ta) can be selected.

Thereafter, as shown in FIGS. 15 and 16 (f), the Ta thin film layer 34 'and the semiconductor layer 33' containing impurities are formed.
And the source / drain electrodes 12 ″ and 21, which are formed by lamination, are selectively formed, and the gate insulating layer 30 ′ is removed in addition to the amorphous silicon layer 31 ′ containing no impurities.
Most of the scanning lines 11 and the auxiliary signal lines 92 are exposed except between the source / drain electrodes 12 ", 21 and under the source / drain electrodes 12", 21. As described above, it is necessary to form the organic insulating layer 72 by electrodeposition on the exposed scanning line 106 and part of the gate 105, and the thickness of 0.1 μm or more is sufficient.

Subsequently, as shown in FIG. 16 (g), a transparent conductive layer having a thickness of about 0.1 to 0.2 μm is formed on the entire surface of the glass substrate 2 by using a vacuum film forming apparatus such as SPT, for example, using ITO (I
n-tin-oxide), the auxiliary electrode divided by including the drain electrode 21, the pixel electrode 22, the source electrode 12 ″, and both ends of the auxiliary signal line 92 on the insulating substrate 2 by the fine processing technique. A connection layer 91 for interconnecting the signal lines 92 is selectively formed.

Using the photosensitive resin pattern 65 used for selective pattern formation of the connection layer 91 and the pixel electrode 22 as a mask, the source electrode 12 ″ excluding the connection layer 91 and the auxiliary signal line 92 are irradiated with light while irradiating light. The drain electrode 21 excluding the picture element electrode 22 and the amorphous silicon layer 3 containing no impurities
1 "is anodized to form an oxide layer on the surface of these thin films.

Regarding the configuration of the scanning line terminal electrode 6, the transparent conductive terminal electrode 6 'may be formed so as to include a part of the scanning line 11 exposed at the same time, or the transparent conductive layer may be removed. The exposed part of the scanning line 11 is connected to the terminal electrode 6.
It can also be.

By performing selective anodic oxidation in the glass substrate 2, a part of the source electrode 12 ″ (signal line) can be used as the terminal electrode 5 in a region outside the image display section as shown in FIG. Further, it is also possible to obtain a terminal electrode 92 'made of the same material as the scanning line 11 or a terminal electrode 5' made of a transparent conductive layer formed including the same. In the case of a conventional anodic oxidation method such as immersion, the signal line 12 cannot be selectively anodized unless an appropriate mask material is used in combination. The terminal electrode 5 ′ made of a layer is formed to include a part of the signal line 12 ″. This configuration is the same as the connection between the picture element electrode 22 and the drain electrode 21 shown in FIG. Finally, the photosensitive resin pattern 65 is removed to complete the active substrate 2 as shown in FIG. The active substrate 2 thus obtained and the color filter are bonded together to form a liquid crystal panel, thereby completing the eighth embodiment of the present invention.

Also in the eighth embodiment, the thickness of the source / drain electrodes cannot be made too large to cope with the lift-off. In the ninth embodiment, the second, fifth and fifth layers are formed to reduce the wiring resistance. As in the sixth embodiment, a low-resistance signal line is separately formed. In a ninth embodiment, that is, a method for manufacturing an active substrate according to claim 18,
As shown in FIG. 17 and FIG.
The source / drain electrodes 12 "and 21 comprising a stack of 4 'and a semiconductor layer 33' containing impurities are selectively formed, and the gate insulating layer 30 'is also removed to remove the source-drain electrodes 12" and 21'. Source / drain electrodes 12 ″,
The scanning line 11 is exposed excluding the portion below the scanning line 21 and the exposed scanning line 1
The process is the same as in the eighth embodiment until the organic insulating layer 72 is formed on the surface of the gate 06 and the portion 105 of the gate.

Thereafter, the AL thin film layer 35 having a thickness of about 0.3 μm
Then, a heat-resistant metal thin film layer 36 of Ta or the like is further sequentially deposited as an intermediate conductive layer having a thickness of about 0.1 μm. Then, these two metal layers are sequentially etched by a fine processing technique using a photosensitive resin pattern, and as shown in FIG. 18 (g), the signal line 1 including the source electrode 12 ″ of the insulated gate transistor is formed.
2 is selectively formed. At this time, since the scanning line 11 is exposed in a region outside the image display unit, when the scanning line material is an AL-based alloy, a part of the exposed scanning line 11 as shown in FIG. It is necessary to leave the AL thin film layer also in (the formation region of the terminal electrode 6) when the signal line 12 is formed. FIG. 18 (g) shows a case where the scanning line 11 does not disappear because the Ta is used as a mask to protect the underlying AL when the AL thin film layer 35 is etched when the scanning line 11 is formed of, for example, a layer of AL / Ta. Is exemplified.

Subsequently, as shown in FIG. 18 (h), a transparent conductive layer having a thickness of about 0.1 to 0.2 μm is formed on the entire surface of the glass substrate 2 by using a vacuum film forming apparatus such as SPT, for example, using ITO (I
Then, a pixel electrode 22 including a drain electrode 21 is selectively formed on the insulating substrate 2 by a fine processing technique.

Using the photosensitive resin pattern 65 used for the selective pattern formation of the pixel electrodes 22 as a mask, the signal lines 12 and the source electrodes 12 ″ excluding the signal lines and the pixel electrodes 22 are removed while irradiating light. The drain electrode 21 and the impurity-free amorphous silicon layer 31 'are anodized to form an anodized layer on the surface of these thin films.

By performing selective anodic oxidation in the glass substrate 2, a part of the signal line 12 can be used as the terminal electrode 5 in a region outside the image display section as shown in FIG. In this case, the signal line 12 does not necessarily have to be a laminate of the low resistance wiring layer and the intermediate conductive layer 36, and there is no problem with a single layer of the AL thin film layer 35 as the low resistance wiring layer. With a conventional anodic oxidation method in which the entire glass substrate 2 is immersed in a chemical conversion solution, the signal line 12 cannot be selectively anodized unless an appropriate mask material is used in combination. The terminal electrode 5 ′ made of a transparent conductive layer in a region outside the image display unit is formed including a part of the signal line 12. Finally, the photosensitive resin pattern 65 is removed to complete the active substrate 2 as shown in FIG.

The configuration of the scanning line terminal electrode 6 includes a part of the scanning line 11 exposed at the time of forming the signal line 12 and a terminal electrode composed of a laminate of the AL thin film layer 35 and the Ta heat resistant metal thin film layer 36. 6 "can be formed, AL
A portion of the scanning line 11 exposed by removing the lamination of the thin film layer 35 and the heat-resistant metal thin film layer 36 of Ta may be used as the terminal electrode 6, or a transparent conductive material including the exposed portion of the scanning line 11 may be used. A terminal electrode 6 ′ having a characteristic property can also be formed. The active substrate 2 thus obtained and the color filter are bonded together to form a liquid crystal panel, thereby completing the ninth embodiment of the present invention.

Regarding the configuration of the storage capacitor 15, an example is shown in which the storage electrode 21 'formed simultaneously with the signal line 12 including the drain electrode 21 and the storage capacitor line 16 are formed via the organic insulating layer 72. 17, the storage capacity 1
The configuration of the pixel electrode 22 is not limited to this.
And the scanning line 11 in the preceding stage. Other configurations are also possible, but detailed description is omitted.

The polyimide thin film which is an organic insulating layer employed in the present invention has a certain resistance to an organic resist stripping solution, but is not sensitive to a stripping means such as an oxygen plasma treatment or a high-concentration ozone aqueous solution. Therefore, it is necessary to restrict and pay attention to resist stripping.

[0146]

As described above, according to the liquid crystal image display device of the present invention, the source and the source are formed of an amorphous silicon layer containing an impurity on the edge of the gate pattern in a self-aligned manner.
A source and a drain electrode made of a drain and a heat-resistant metal can be formed, and the parasitic capacitance of the insulated gate transistor can be reduced to a value one-several of the conventional value. As a result, even in a large-screen, high-definition liquid crystal image display device, a special effect is obtained in which flicker, printing, or display unevenness is less likely to occur.

Next, since the passivation formation according to the present invention does not involve a special heating step, an insulated gate transistor using an amorphous silicon layer as a semiconductor layer does not require excessive heat resistance. In other words, the effect of preventing the electrical performance from being deteriorated by the passivation is obtained. In some cases, it is also possible to adopt a single-layer AL source / drain electrode without interposing a heat-resistant barrier metal layer.

Further, since the isolation of the amorphous silicon layer containing a pair of impurities which becomes the source / drain of the insulated gate transistor is performed by using the lift-off layer, the conventional method is used for etching the channel semiconductor layer at the time of etching. There is no danger that the electrical characteristics of the insulated gate transistor will be degraded due to damage.
Although the VD process is performed, not only the device configuration of the PCVD device is simplified, but also the thickness of the amorphous silicon layer containing no impurities is at most 0.1 μm, which is sufficient. And the operation of the PCVD apparatus and the state of particle generation are improved.

In addition, by making the auxiliary signal line formed of the same member as the scanning line function as a signal line, the resistance of the signal line can be reduced without increasing the number of manufacturing steps, and a large screen can be realized. became. Furthermore, by introducing an organic insulating layer by electrodeposition, it is possible to simultaneously perform the step of forming the source / drain electrodes and the step of forming the opening in the gate insulating layer, thereby reducing the number of photolithography steps from the conventional 5 times. As a result, excellent effects such as reduction of manufacturing costs were promoted.

As is clear from the above description, the requirements of the present invention are as follows: the gate metal layer, the gate insulating layer, the semiconductor layer, and the lift-off layer are collectively etched to form a scanning line which is exposed. Of forming an organic insulating layer by electrodeposition on the side surface of the substrate, retreating (decreasing the film thickness) of the photosensitive resin pattern used for forming the scanning lines, and forming the semiconductor layer containing impurities and the source / drain electrodes by lift-off. For other configurations, the semiconductor device for an image display device in which the material and thickness of the picture element electrode, the gate metal layer, the gate insulating layer, and the like are different, or the difference in the manufacturing method is also included in the scope of the present invention. An IPS (In-Pla) that controls by applying a horizontal electric field to a liquid crystal between a pixel electrode and a counter electrode formed at a predetermined distance on the same substrate.
The present invention can be easily applied to an in-switching type liquid crystal panel. For example, in the semiconductor device for an image display device according to the third embodiment shown in FIG. Counter electrode (common capacitance line) 1
6 is formed at a predetermined distance from the drain (picture element) electrode 21, and a region where the drain electrode 21 and the counter electrode 16 overlap with each other via the gate insulating layer (a double shaded portion) forms a storage capacitor. I have. In addition, the usefulness of the present invention is not changed even in a reflection type liquid crystal image display device using a picture element electrode as a metal electrode (in the claims, both a transparent conductive layer and a metal reflection layer are expressed by a conductive thin film). It is obvious that, since a transparent conductive layer is not required, a signal line forming step for lowering resistance and a reflective electrode forming step can be performed simultaneously. The same applies to a transflective liquid crystal image display device that requires both a transparent conductive (transmissive) picture element electrode and a reflective electrode. Also, the semiconductor layer of the insulated gate transistor is not limited to amorphous silicon, and it is apparent that microcrystalline silicon, polycrystalline silicon, or a mixed crystal thereof does not cause any problem.

[Brief description of the drawings]

FIG. 1 is a plan view of a semiconductor device for an image display device according to a first embodiment of the present invention.

FIG. 2 is a sectional view showing a manufacturing process of the semiconductor device for an image display device according to the first embodiment of the present invention;

FIG. 3 is a plan view of a semiconductor device for an image display device according to a second embodiment of the present invention.

FIG. 4 is a sectional view showing a manufacturing process of a semiconductor device for an image display device according to a second embodiment of the present invention.

FIG. 5 is a plan view of a semiconductor device for an image display device according to a third embodiment of the present invention.

FIG. 6 is a sectional view showing a manufacturing process of the semiconductor device for an image display device according to the third embodiment of the present invention.

FIG. 7 is a plan view of a semiconductor device for an image display device according to a fourth embodiment of the present invention.

FIG. 8 is a sectional view showing a manufacturing process of a semiconductor device for an image display device according to a fourth embodiment of the present invention.

FIG. 9 is a plan view of a semiconductor device for an image display device according to a fifth embodiment of the present invention.

FIG. 10 is a sectional view showing a manufacturing process of a semiconductor device for an image display device according to a fifth embodiment of the present invention.

FIG. 11 is a plan view of a semiconductor device for an image display device according to a sixth embodiment of the present invention.

FIG. 12 is a sectional view showing a manufacturing process of the semiconductor device for an image display device according to the sixth embodiment of the present invention.

FIG. 13 is a plan view of a semiconductor device for an image display device according to a seventh embodiment of the present invention.

FIG. 14 is a sectional view showing a manufacturing process of the semiconductor device for an image display device according to the seventh embodiment of the present invention.

FIG. 15 is a plan view of a semiconductor device for an image display device according to an eighth embodiment of the present invention.

FIG. 16 is a sectional view showing the manufacturing process of the semiconductor device for an image display device according to the eighth embodiment of the present invention.

FIG. 17 is a plan view of a semiconductor device for an image display device according to a ninth embodiment of the present invention;

FIG. 18 is a sectional view showing a manufacturing process of the semiconductor device for an image display device according to the ninth embodiment of the present invention.

FIG. 19 is a diagram showing a mounting state of a liquid crystal panel.

FIG. 20 is an equivalent circuit diagram of a liquid crystal panel.

FIG. 21 is a sectional view of a main part of a liquid crystal panel.

FIG. 22 is a plan view of a conventional active substrate.

FIG. 23 is a sectional view showing a manufacturing process of a conventional active substrate.

FIG. 24 is a plan view of a streamlined active substrate.

FIG. 25 is a sectional view of a manufacturing process of a streamlined active substrate.

FIG. 26 is a view showing a pattern arrangement when forming an organic insulating layer on the side of a scanning line according to the present invention.

FIG. 27 is a plan view of a semiconductor device for an IPS image display device according to the present invention.

[Explanation of symbols]

Reference Signs List 1 liquid crystal image display device (liquid crystal panel) 2 active substrate (insulating substrate, glass substrate) 3 semiconductor integrated circuit chip 4 TCP film 5, 6 terminal electrode 9 color filter (opposing glass substrate) 10 insulated gate transistor 11 scanning line ( (Gate) 12 (12 ′, 12 ″) signal line (source electrode) 16 common capacitance line 17 liquid crystal 21 drain electrode 22 (transparent conductive) picture element electrode 30 gate insulating layer (first SiNx layer) 31 impurity Amorphous silicon layer 32 which is not included (which is a first semiconductor layer) 32 (which is an insulating layer for protecting a channel)
Nx layer 33 Amorphous silicon layer containing impurities (second semiconductor layer) 34 (anodically oxidizable) heat-resistant metal layer 35 (anodically oxidizable) low-resistance metal layer (AL) 36 (anodically oxidizable) ) Intermediate conductive layer 37 Passivation insulating layer 40 Lift-off layer 61 Opening (on auxiliary signal line) 62 Opening (on drain electrode) 63 Opening (on scanning line) 64 Opening (on signal line) 65 (pixel electrode) Photosensitive resin pattern (formed) 66 Impurity-free silicon oxide layer 67 Impurity-containing silicon oxide layer 68 5 Tantalum oxide (Ta2O5) 69 Alumina (Al2O3) 71 Organic insulating layer 72 formed on the side surface of gate (scanning line) 72 Organic insulating layer formed on the surface of the gate (scanning line) 80 First metal layer 91 Connection layer (connecting the divided source electrode) 92 Auxiliary signal line

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (Reference) H01L 29/78 616M F-term (Reference) 2H092 GA14 GA48 GA49 GA50 GA51 HA25 JA26 JA29 JA38 JA42 JA44 JB13 JB23 JB32 JB33 JB38 JB51 JB56 JB63 JB69 KA05 KA07 MA05 MA08 MA14 MA15 MA16 MA18 MA19 MA20 MA24 MA27 MA35 MA37 MA41 MA43 NA25 NA27 QA18 5C094 AA02 AA03 AA43 AA44 BA03 BA43 CA19 CA24 DA14 DA15 EA04 EA05 EA06 EA07 EB02 FB12 A03 EB14 AFB FB14 EE06 EE14 EE15 EE32 EE44 FF03 FF30 GG02 GG15 GG25 GG35 GG39 GG45 HK03 HK04 HK09 HK16 HK21 HK22 HK25 HK33 HK35 HL07 HL23 HL27 NN04 NN24 NN35 NN72 QQ01 QQ11 QQ14

Claims (18)

[Claims] 1. A semiconductor layer free of impurities is formed on a gate by using at least one metal layer having a gate insulating layer on its surface and an organic insulating layer on its side surface, with the gate insulating layer interposed therebetween. And a source / drain electrode comprising a stack of a pair of impurity-containing semiconductor layers and metal layers formed in a self-aligned manner on both ends of the impurity-free semiconductor layer. 2. An insulating substrate in which unit picture elements having at least an insulated gate transistor on one main surface and a picture element electrode connected to a drain of the insulated gate transistor are arranged in a two-dimensional matrix; In a liquid crystal image display device in which liquid crystal is filled between the insulating substrate and a transparent insulating substrate or a color filter opposed to the insulating substrate, a gate insulating layer is formed on one main surface of the insulating substrate and an organic insulating layer is formed on a side surface thereof. A scanning line which is formed of one or more metal layers having the following characteristics and also serves as a gate of the insulated gate transistor; a semiconductor layer containing no impurities is formed on the gate via a gate insulating layer; A source (signal line) except for a drain electrode and a scanning line, which are formed by laminating a semiconductor layer containing a pair of impurities and a metal layer on both ends of a semiconductor layer and on an insulating substrate.
An electrode is formed, and a first opening and a source (signal line) are formed on the drain electrode.
A passivation insulating layer having a pair of second openings is formed on the entire surface of the electrode, and the source electrode (signal line including the first opening and the pixel electrode separated from the second opening) is separated. A) a liquid crystal image display device, wherein a connection layer for connecting electrodes is formed on a passivation insulating layer. 3. An insulating substrate in which unit pixels having at least an insulated gate transistor on one main surface and a pixel electrode connected to a drain of the insulated gate transistor are arranged in a two-dimensional matrix; In a liquid crystal image display device in which liquid crystal is filled between the insulating substrate and a transparent insulating substrate or a color filter opposed to the insulating substrate, a gate insulating layer is formed on one main surface of the insulating substrate and an organic insulating layer is formed on a side surface thereof. A scanning line which is formed of one or more metal layers having the following characteristics and also serves as a gate of the insulated gate transistor; a semiconductor layer containing no impurities is formed on the gate via a gate insulating layer; Source / drain electrodes composed of a stack of a semiconductor layer containing a pair of impurities and a metal layer are formed on both ends of the semiconductor layer and on the insulating substrate. A signal line including one or more metal layers including the source electrode is formed, a passivation insulating layer having an opening on the drain electrode is formed on the entire surface, and a picture is formed on the passivation insulating layer including the opening. A liquid crystal image display device comprising elementary electrodes. 4. An insulating substrate in which unit picture elements having at least an insulated gate transistor on one main surface and a picture element electrode connected to a drain of the insulated gate transistor are arranged in a two-dimensional matrix; In a liquid crystal image display device in which liquid crystal is filled between the insulating substrate and a transparent insulating substrate or a color filter opposed to the insulating substrate, a gate insulating layer is formed on one main surface of the insulating substrate and an organic insulating layer is formed on a side surface thereof. A scanning line which is formed of one or more metal layers having the following characteristics and also serves as a gate of the insulated gate transistor; a semiconductor layer containing no impurities is formed on the gate via a gate insulating layer; Except for the drain electrode and the scanning line, which are formed by laminating a semiconductor layer containing a pair of impurities and a metal layer capable of being anodized on both ends of the semiconductor layer and on the insulating substrate. A source (signal line) electrode is formed, a connection layer connecting the picture element electrode including the drain electrode and the divided source (signal line) electrode is formed on an insulating substrate, and a source excluding the connection layer is formed. A liquid crystal image display device, wherein an anodized layer is formed on a surface of a semiconductor layer containing no impurities and a drain electrode excluding an electrode and a pixel electrode. 5. An insulating substrate in which unit pixels having at least an insulated gate transistor on one main surface and a pixel electrode connected to a drain of the insulated gate transistor are arranged in a two-dimensional matrix; In a liquid crystal image display device in which liquid crystal is filled between the insulating substrate and a transparent insulating substrate or a color filter opposed to the insulating substrate, one or more anodically oxidizable metal layers are formed on one main surface of the insulating substrate. A scanning line which has a gate insulating layer on the surface and an organic insulating layer on the side surface and also serves as the gate of an insulated gate transistor, has a gate insulating layer on the surface and an anodic oxide layer on the side surface, and has openings at both ends. Forming an auxiliary signal line, a semiconductor layer containing no impurities is formed on the gate via a gate insulating layer, and a pixel electrode is formed on an insulating substrate including the drain electrode A drain electrode and a source / drain electrode each formed of a stack of a pair of a semiconductor layer containing an impurity and a metal layer capable of being anodized are formed on both ends of the semiconductor layer containing no impurity and on the insulating substrate; A pixel electrode including the drain electrode, a connection layer connecting the divided auxiliary signal lines including the opening and the source electrode including the drain electrode, and a source electrode and a pixel electrode excluding the connection layer; A liquid crystal image display device, wherein an anodized layer is formed on the surface of the drain electrode and the semiconductor layer containing no impurities. 6. An insulating substrate in which unit picture elements having at least an insulated gate transistor on one main surface and a picture element electrode connected to a drain of the insulated gate transistor are arranged in a two-dimensional matrix; In a liquid crystal image display device in which liquid crystal is filled between the insulating substrate and a transparent insulating substrate or a color filter opposed to the insulating substrate, a gate insulating layer is formed on one main surface of the insulating substrate and an organic insulating layer is formed on a side surface thereof. A scanning line which is formed of one or more metal layers having the following characteristics and also serves as a gate of the insulated gate transistor; a semiconductor layer containing no impurities is formed on the gate via a gate insulating layer; Source / drain electrodes formed of a stack of a semiconductor layer containing a pair of impurities and an anodizable metal layer are formed on both ends of the semiconductor layer and on the insulating substrate, Anodizable 1 including the source electrode on an insulating substrate
A signal line composed of at least one metal layer; a pixel electrode including the drain electrode on an insulating substrate; a drain electrode excluding the signal line, a source electrode excluding the signal line, and a pixel electrode; A liquid crystal image display device, wherein an anodized layer is formed on a surface of a semiconductor layer that does not contain any. 7. An insulating substrate in which unit picture elements having at least an insulated gate transistor on one main surface and a picture element electrode connected to a drain of the insulated gate transistor are arranged in a two-dimensional matrix; In a liquid crystal image display device in which liquid crystal is filled between the insulating substrate and a transparent insulating substrate or a color filter facing the insulating substrate, a channel and a source (signal line).
A scanning line which is formed of one or more metal layers having an organic insulating layer on the surface except for the area under the drain electrode and also serves as the gate of the insulated gate transistor is formed, and does not contain impurities on the gate via the gate insulating layer. A semiconductor layer is formed, except on a drain electrode and a scan line, which are formed by stacking a pair of a semiconductor layer containing an impurity and an anodizable metal layer on both ends of the semiconductor layer containing no impurity and on an insulating substrate. A source (signal line) electrode is formed, a picture element electrode including the drain electrode and a connection layer for connecting the divided source (signal line) electrode are formed on an insulating substrate, and a source excluding the connection layer is formed. A liquid crystal image display device, wherein an anodized layer is formed on a surface of a semiconductor layer containing no impurities and a drain electrode excluding an electrode and a pixel electrode. 8. An insulating substrate in which unit picture elements having at least an insulated gate transistor on one main surface and a picture element electrode connected to a drain of the insulated gate transistor are arranged in a two-dimensional matrix; In a liquid crystal image display device in which liquid crystal is filled between the insulating substrate and a transparent insulating substrate or a color filter opposed to the insulating substrate, the surface of the insulating substrate is formed on one main surface of the insulating substrate except for between channels and below source / drain electrodes. A scanning line which is formed of one or more metal layers capable of anodization and has an organic insulating layer and also serves as a gate of the insulated gate transistor, and an auxiliary signal line having an anodized layer on its surface except for both end portions are formed, A semiconductor layer containing no impurities is formed on the gate via a gate insulating layer, and a pair of impurities is formed on both ends of the semiconductor layer containing no impurities and on the insulating substrate. And a source / drain electrode composed of a stack of a semiconductor layer containing anodized metal layer and an anodizable metal layer. The source / drain electrode is divided on the insulating substrate including the drain electrode, including the pixel electrode, the both ends, and the source electrode. A connection layer for connecting the auxiliary signal line, and a source electrode except for the connection layer, a drain electrode except for the pixel electrode, and an anodic oxide layer formed on a surface of the semiconductor layer containing no impurities. Liquid crystal image display device. 9. An insulating substrate in which unit picture elements having at least an insulated gate transistor on one main surface and a picture element electrode connected to a drain of the insulated gate transistor are arranged in a two-dimensional matrix; In a liquid crystal image display device in which liquid crystal is filled between the insulating substrate and a transparent insulating substrate or a color filter opposed to the insulating substrate, the surface of the insulating substrate is formed on one main surface of the insulating substrate except for between channels and below source / drain electrodes. A scanning line which is formed of at least one metal layer having an organic insulating layer and also serves as a gate of the insulated gate transistor; a semiconductor layer containing no impurity is formed on the gate via a gate insulating layer; Source / drain consisting of a stack of a pair of semiconductor layers containing impurities and an anodizable metal layer on both ends of a semiconductor layer not containing silicon and on an insulating substrate Pole is formed, which can be anodized comprise the source electrode on an insulating substrate 1
A signal line composed of at least one metal layer; a pixel electrode including the drain electrode on an insulating substrate; a drain electrode excluding the signal line, a source electrode excluding the signal line, and a pixel electrode; A liquid crystal image display device, wherein an anodized layer is formed on a surface of a semiconductor layer that does not contain any. 10. One or more first layers on one main surface of an insulating substrate.
A step of depositing one or more gate insulating layers and a first semiconductor layer containing no impurities in the peripheral portion of the insulating substrate except for a part of the first metal layer. A step of applying a lift-off layer after the deposition, a step of selectively forming a photosensitive resin pattern corresponding to a scanning line also serving as a gate of an insulated gate transistor on the lift-off layer, and using the photosensitive resin pattern as a mask. Lift-off layer, first
Sequentially etching the semiconductor layer, the gate insulating layer, and the first metal layer, reducing the thickness of the photosensitive resin pattern to partially expose the lift-off layer, and removing the photosensitive resin pattern. Etching the lift-off layer using the pattern as a mask to partially expose the first semiconductor layer; forming an organic insulating layer on a side surface of the scan line; A step of sequentially depositing the second metal layer and a step of selectively removing the second semiconductor layer and the second metal layer on the lift-off layer together with the removal of the lift-off layer; Selectively forming, on the first semiconductor layer and the insulating substrate, a drain electrode formed of a stack of a second semiconductor layer and a second metal layer and a separated source (signal line) electrode; Depositing a layer; Forming an opening on the in-electrode and on the source (signal line) electrode and selectively removing the passivation insulating layer in the opening; applying a conductive thin film; A step of selectively forming a pixel electrode including an opening on the drain electrode and a connection layer for connecting a divided source (signal line) electrode including an opening on the source (signal line) electrode; A method for manufacturing a semiconductor device for an image display device, comprising: 11. One or more first layers on one main surface of an insulating substrate.
A step of depositing one or more gate insulating layers and a first semiconductor layer containing no impurities in the peripheral portion of the insulating substrate except for a part of the first metal layer. A step of applying a lift-off layer after the deposition, a step of selectively forming a photosensitive resin pattern corresponding to a scanning line also serving as a gate of an insulated gate transistor on the lift-off layer, and using the photosensitive resin pattern as a mask. Lift-off layer, first
Sequentially etching the semiconductor layer, the gate insulating layer, and the first metal layer, reducing the thickness of the photosensitive resin pattern to partially expose the lift-off layer, and removing the photosensitive resin pattern. Etching the lift-off layer using the pattern as a mask to partially expose the first semiconductor layer; forming an organic insulating layer on a side surface of the scan line; A step of sequentially applying a second metal layer and a step of selectively removing a second semiconductor layer and a second metal layer on the lift-off layer together with the removal of the lift-off layer; Selectively forming a source / drain electrode comprising a laminate of a second semiconductor layer and a second metal layer on the first semiconductor layer and the insulating substrate;
A step of depositing at least a third metal layer, a step of selectively forming a signal line comprising the third metal layer including the source electrode, and a step of depositing a passivation insulating layer;
Forming an opening on the drain electrode to selectively remove the passivation insulating layer in the opening, applying a conductive thin film, and including an opening on the drain electrode on the passivation insulating layer. Forming a picture element electrode by using the method described above. 12. One or more first layers on one main surface of an insulating substrate.
A step of depositing one or more gate insulating layers and a first semiconductor layer containing no impurities in the peripheral portion of the insulating substrate except for a part of the first metal layer. A step of applying a lift-off layer after the deposition, a step of selectively forming a photosensitive resin pattern corresponding to a scanning line also serving as a gate of an insulated gate transistor on the lift-off layer, and using the photosensitive resin pattern as a mask. Lift-off layer, first
Sequentially etching the semiconductor layer, the gate insulating layer, and the first metal layer, reducing the thickness of the photosensitive resin pattern to partially expose the lift-off layer, and removing the photosensitive resin pattern. Etching the lift-off layer using the pattern as a mask to partially expose the first semiconductor layer; forming an organic insulating layer on the side surface of the scan line; Sequentially depositing an oxidizable second metal layer; selectively removing the second semiconductor layer and the second metal layer on the lift-off layer while removing the lift-off layer; Selectively forming a drain electrode formed of a stack of a second semiconductor layer and a second metal layer and a separated source (signal line) electrode on the first semiconductor layer and the insulating substrate at both ends of the semiconductor device. And a step of depositing a conductive thin film. Selectively forming, on a substrate, a picture element electrode including the drain electrode and a connection layer connecting the divided source (signal line) electrode including the source (signal line) electrode; The photosensitive resin pattern used for the selective pattern formation of the electrodes is used as a mask to protect the picture element electrodes while irradiating light while excluding the connection layer.
Forming an anodic oxide layer on the semiconductor layer of the present invention. 13. A step of depositing one or more anodically oxidizable first metal layers on one main surface of an insulating substrate, and a step of forming a portion of the first metal layer at a peripheral portion of the insulating substrate. Exposing a lift-off layer after sequentially depositing one or more gate insulating layers and a first semiconductor layer containing no impurities except for the above, and a scanning line serving also as a gate of an insulated gate transistor on the lift-off layer Selectively forming a photosensitive resin pattern corresponding to the substrate and the auxiliary signal line; and sequentially etching the lift-off layer, the first semiconductor layer, the gate insulating layer, and the first metal layer using the photosensitive resin pattern as a mask. Engraving; reducing the thickness of the photosensitive resin pattern to partially expose the lift-off layer; and etching the lift-off layer using the reduced thickness photosensitive resin pattern as a mask to form a first semiconductor layer. Partially expose Forming an organic insulating layer on a side surface of the scanning line, applying a second semiconductor layer containing impurities, forming openings on the scanning line outside the image display unit and at both ends of the auxiliary signal line. Forming a portion and selectively removing the second semiconductor layer, the lift-off layer, the first semiconductor layer, and the gate insulating layer; applying an anodically oxidizable second metal layer; Selectively removing the second semiconductor layer and the second metal layer on the lift-off layer together with the removal; and forming the second semiconductor layer on both ends of the first semiconductor layer on the gate and on the insulating substrate. A step of selectively forming source / drain electrodes made of a laminate with a second metal layer; a step of depositing a conductive thin film; and a pixel electrode including the drain electrode on an insulating substrate and the opening. To connect the separated auxiliary signal line including the source electrode And forming the source electrode and the picture element except for the connection layer while irradiating light while protecting the picture element electrode using the photosensitive resin pattern used as a mask for the selective pattern formation of the picture element electrode. Forming an anodic oxide layer on the drain electrode excluding the elementary electrode and the first semiconductor layer containing no impurity. 14. One or more first layers on one main surface of an insulating substrate.
A step of depositing one or more gate insulating layers and a first semiconductor layer containing no impurities in the peripheral portion of the insulating substrate except for a part of the first metal layer. A step of applying a lift-off layer after the deposition, a step of selectively forming a photosensitive resin pattern corresponding to a scanning line also serving as a gate of an insulated gate transistor on the lift-off layer, and using the photosensitive resin pattern as a mask. Lift-off layer, first
Sequentially etching the semiconductor layer, the gate insulating layer, and the first metal layer, reducing the thickness of the photosensitive resin pattern to partially expose the lift-off layer, and removing the photosensitive resin pattern. Etching the lift-off layer using the pattern as a mask to partially expose the first semiconductor layer; forming an organic insulating layer on the side surface of the scan line; Sequentially depositing an oxidizable second metal layer; selectively removing the second semiconductor layer and the second metal layer on the lift-off layer while removing the lift-off layer; Selectively forming a pair of source / drain electrodes composed of a laminate of a second semiconductor layer and a second metal layer on the first semiconductor layer and the insulating substrate at both ends of the image display unit; An opening is formed on the scanning line in the area Selectively removing the upper gate insulating layer, depositing one or more third metal layers capable of being anodized, and forming a signal line comprising the third metal layer including the source electrode. A step of selectively forming, a step of applying a conductive thin film, a step of selectively forming a pixel electrode including the drain electrode on an insulating substrate, and a step of selectively forming a pattern of the pixel electrode. A signal line, a source electrode excluding the signal line, a drain electrode excluding the pixel electrode, a first semiconductor layer containing no impurity, and a signal line while irradiating light while protecting the pixel electrode using the photosensitive resin pattern used as a mask. Forming an anodized layer on a semiconductor device. 15. One or more first layers on one main surface of an insulating substrate.
A step of depositing one or more gate insulating layers and a first semiconductor layer containing no impurities in the peripheral portion of the insulating substrate except for a part of the first metal layer. A step of applying a lift-off layer after the deposition, a step of selectively forming a photosensitive resin pattern corresponding to a scanning line also serving as a gate of an insulated gate transistor on the lift-off layer, and using the photosensitive resin pattern as a mask. Lift-off layer, first
Sequentially etching the semiconductor layer, the gate insulating layer, and the first metal layer, reducing the thickness of the photosensitive resin pattern to partially expose the lift-off layer, and removing the photosensitive resin pattern. Etching the lift-off layer using the pattern as a mask to partially expose the first semiconductor layer; forming an organic insulating layer on the side surface of the scan line; Sequentially depositing an oxidizable second metal layer; selectively removing the second semiconductor layer and the second metal layer on the lift-off layer while removing the lift-off layer; Selectively forming a pair of source / drain electrodes composed of a laminate of a second semiconductor layer and a second metal layer on the first semiconductor layer and the insulating substrate at both ends of the substrate; Work to apply one or more third metal layers Selectively forming a signal line made of a third metal layer including the source electrode; and forming an opening on a scanning line in a region outside the image display unit to selectively form a gate insulating layer on the scanning line. Removing, a step of applying a conductive thin film, a step of selectively forming a pixel electrode including the drain electrode on an insulating substrate, and a step of selectively forming the pixel electrode. While irradiating light while protecting the picture element electrodes using the photosensitive resin pattern as a mask, the anode is formed on the signal line, the source electrode excluding the signal line, the drain electrode excluding the picture element electrode, and the first semiconductor layer containing no impurities. Forming an oxide layer. 16. One or more first layers on one main surface of an insulating substrate.
A step of depositing one or more gate insulating layers and a first semiconductor layer containing no impurities in the peripheral portion of the insulating substrate except for a part of the first metal layer. A step of applying a lift-off layer after the deposition, a step of selectively forming a photosensitive resin pattern corresponding to a scanning line also serving as a gate of an insulated gate transistor on the lift-off layer, and using the photosensitive resin pattern as a mask. Lift-off layer, first
Sequentially etching the semiconductor layer, the gate insulating layer, and the first metal layer, reducing the thickness of the photosensitive resin pattern to partially expose the lift-off layer, and removing the photosensitive resin pattern. Etching the lift-off layer using the pattern as a mask to partially expose the first semiconductor layer; forming an organic insulating layer on the side surface of the scan line; Sequentially depositing an oxidizable second metal layer; selectively removing the second semiconductor layer and the second metal layer on the lift-off layer while removing the lift-off layer; And selectively forming a source (signal line) electrode separated from a drain electrode composed of a stack of a second semiconductor layer and a second metal layer on the first semiconductor layer and the insulating substrate at both ends of the substrate. Between source-drain electrode and source Exposing the scanning lines except under the drain electrode, forming an organic insulating layer on the exposed scanning lines and the gate in the image display unit, applying a conductive thin film, and Selectively forming a pixel electrode including the drain electrode and a connection layer for connecting the divided source electrode including the source electrode, and a selective pattern formation of the pixel electrode. Forming an anodic oxide layer on the source electrode excluding the connection layer, the drain electrode excluding the pixel electrode, and the first semiconductor layer containing no impurities while irradiating light while protecting the pixel electrodes using the photosensitive resin pattern as a mask. And a method for manufacturing a semiconductor device for an image display device. 17. A step of depositing one or more anodically oxidizable first metal layers on one main surface on an insulating substrate, and forming a portion of the first metal layer on a peripheral portion of the insulating substrate. Exposing a lift-off layer after sequentially depositing one or more gate insulating layers and a first semiconductor layer containing no impurities except for the above, and a scanning line serving also as a gate of an insulated gate transistor on the lift-off layer And selectively forming a photosensitive resin pattern corresponding to the auxiliary signal line, and sequentially etching the lift-off layer, the first semiconductor layer, the gate insulating layer, and the first metal layer using the photosensitive resin pattern as a mask. Performing the step of reducing the film thickness of the photosensitive resin pattern to partially expose the lift-off layer, and etching the lift-off layer using the reduced photosensitive resin pattern as a mask to form the first semiconductor layer. Partially exposed Forming an organic insulating layer on a side surface of the scanning line, sequentially applying a second semiconductor layer containing impurities and a second metal layer capable of being anodized, and removing the lift-off layer Selectively removing the second semiconductor layer and the second metal layer on the lift-off layer, and
A source comprising a stack of a second semiconductor layer and a second metal layer on the first semiconductor layer at both ends on the gate and on the insulating substrate.
Selectively forming the drain electrode and exposing the scanning lines and auxiliary signal lines except between the source and drain electrodes and under the source and drain electrodes; and forming organic layers on the exposed scanning lines and gates in the image display section. Forming an insulating layer;
A step of applying a conductive thin film, and a step of selectively forming a connection layer connecting the source electrode including both ends of the picture element electrode and the auxiliary signal line including the drain electrode on the insulating substrate, The source electrode, the auxiliary signal line, and the drain electrode excluding the pixel electrode except for the connection layer while irradiating light while protecting the pixel electrode using the photosensitive resin pattern used for the selective pattern formation of the pixel electrode as a mask. And the first that does not contain impurities
Forming an anodic oxide layer on the semiconductor layer of the present invention. 18. One or more first layers on one main surface of an insulating substrate.
A step of depositing one or more gate insulating layers and a first semiconductor layer containing no impurities in the peripheral portion of the insulating substrate except for a part of the first metal layer. A step of applying a lift-off layer after the deposition, a step of selectively forming a photosensitive resin pattern corresponding to a scanning line pattern also serving as a gate of the insulated gate transistor on the lift-off layer, and a step of masking the photosensitive resin pattern. Sequentially etching a lift-off layer, a first semiconductor layer, a gate insulating layer, and a first metal layer, forming an organic insulating layer on a side surface of the scanning line, and retracting the photosensitive resin pattern. Partially exposing the lift-off layer by etching, using the recessed photosensitive resin pattern as a mask to etch the lift-off layer to partially expose the first semiconductor layer, Retracting the lift-off layer by partially exposing the lift-off layer; and sequentially exposing the first semiconductor layer by etching the lift-off layer sequentially using the retracted photosensitive resin pattern as a mask; A step of sequentially depositing a second semiconductor layer containing impurities and a second metal layer capable of being anodized after the removal of the photosensitive resin pattern; and removing the lift-off layer together with the second semiconductor layer on the lift-off layer. Selectively removing the anodically oxidizable second metal layer, and laminating the second semiconductor layer and the second metal layer on the first semiconductor layer at both ends on the gate and on the insulating substrate Selectively forming a pair of source / drain electrodes and exposing the scanning lines except between the source / drain electrodes and below the source / drain electrodes; and exposing the scanning lines and the gates exposed in the image display portion. To organic insulation Forming a first metal layer, applying one or more third metal layers capable of being anodized, and selectively forming a signal line made of a third metal layer including the source electrode; A step of applying a conductive thin film, a step of selectively forming a pixel electrode including the drain electrode on an insulating substrate, and a step of forming a photosensitive resin pattern used for selective pattern formation of the pixel electrode. Forming an anodized layer on a signal line, a source electrode excluding the signal line, a drain electrode excluding the pixel electrode, and a first semiconductor layer containing no impurities while irradiating light while protecting the pixel electrode as a mask; A method for manufacturing a semiconductor device for an image display device, comprising: