1246691 九、發明說明： 【發明所屬之技術領域】 本^明係有關於一種不需要更新循環（巧de )之偽靜態隨機存 取，k體(Pseudo static Random Access Memory，PSRAM)晶胞（cell)，特 別疋有關於一種不需要額外控制信號的偽靜態隨機存取記憶體晶胞。 【先前技術】 <。己體在電腦J1業巾扮演著無可或缺的角色。通常，記憶體可依照其 電源關醜仍跡存資料，_分為動態隨機存取記憶體⑽AM)及 機存取記鐘(SRAM)_。義隨齡取記憶體⑽AM)具有面積小 j低等優點，但操料必須不日杨更新(讀娜)以防止資料因漏電流 機^ ^導致存在有高速化困難及消耗功率大等缺失。相反地，靜態隨 及、、Lti體咖)的操作則較為簡易且毋須更新操作，因此具有高速化 取^刪雜__凯，_蝴珊== 的剖面示圖第—α圖中晶胞實施在半導體基底上 寄生二極體D1QW面存取電晶體⑽源極及儲存電容器⑽形成有 電位為零），儲存^哭存取電晶體Τ處於關閉狀態（字元線WL的 時間:Uttr”存放的信號s(邏輯⑺仍會因漏電流的緣故，隨 地進行更新，亦二先必須周期性 的感應放大器（針絲)放大，再毅讀立元輒上 之位址係分赠行恤及舰址，必财 f如去L dram RAS(行位址閃控）信號及CAS(列位關控)信號，因而序的信號 胞之控制電路，有時序控制比SRAM複雜，且耗電大之‘ “定期更新晶 而以行動電話域表之綱子設備所採用之半^體晴置，目前 !246691 之帝敗二1Λ延長之手機。第二圖即是㈣態隨機存取記憶體(SRAM)晶胞 動：曰：'圖’其中’廳電晶體P1和P2稱為負載電晶體，附和_為驅 動ί曰曰曰二，财稱為存取電晶體’由於該·晶胞需要6個電晶體，且驅 存取電晶體間的電流鶴能力比（即單元比率(cenrati〇))通 “又=在2至3之間，而導致存在有高集積化困難及價格高等缺失。 近之手财㈣料子郵件收發魏，續存取網際網路上之觀伺 雕二間，首頁内谷^顯不之功能，為落實如此之魏，用以將多樣的多媒 j訊提供給使用者之圖形顯示不可或缺，因此必須具備用以暫時儲存由 么小網路狗級之大«料於«的大容量半導體記憶裝置。 旦1者’行動電子設備因有小、輕、耗電低之需求，半導體記憶裝置容 置=時備本身之加大、、變重、消耗功率增加仍須避免。因此，行動電 子:2備载之半導體記憶裝置，考慮取用之簡便、耗電時雖以sram為佳， 仁從大谷里之觀點又以服舰為佳。因而，最適於今後之行動電子設備者， 可說係各摘取SRAM及DRAM之優點的半導體記憶裝置。 如此之半導體記憶裝置，已有使用如同採用kDRAM之晶胞，從外部觀 察時規格大致與SRAM相同之所謂「偽靜態隨機存取記憶體(Pseud〇犯也1246691 IX. Description of the invention: [Technical field to which the invention pertains] This is a pseudo-static random access (PSRAM) cell (cell) that does not require an update loop (cell). In particular, there is a pseudo-static random access memory cell that does not require an additional control signal. [Prior Art] <. The body plays an indispensable role in the computer J1 industry towel. Usually, the memory can be stored in accordance with its power supply, and is divided into dynamic random access memory (10) AM and machine access clock (SRAM)_. The memory (10) AM with the small age has the advantages of small area and low j, but the material must be updated (reading Na) to prevent the data from being leaky due to the leakage current and the high power consumption and power consumption. On the contrary, the operation of static and easy, Lti body coffee is relatively simple and does not need to be updated, so it has a high-speed access to remove the __ Kai, _ _ _ _ = = = The parasitic diode D1QW surface access transistor (10) is implemented on the semiconductor substrate, and the storage capacitor (10) is formed with a potential of zero), and the storage crying access transistor is turned off (time of the word line WL: Uttr) The stored signal s (logic (7) will still be updated locally due to leakage current. Secondly, it must be periodically amplified by a sense amplifier (needle), and then read the address on the Liyuan 系 系The ship site, must be f, such as the L dram RAS (row address flash control) signal and CAS (column address control) signal, so the control circuit of the sequence signal cell, the timing control is more complicated than the SRAM, and the power consumption is large. 'The regular update of the crystal and the mobile phone domain table of the equipment used by the half-body clear, currently! 246691 Emperor defeated the 2 Λ extended mobile phone. The second picture is (four) state random access memory (SRAM) Crystal cell movement: 曰: '图' where 'the hall transistors P1 and P2 are called load transistors, The _ is driven by 曰曰曰 曰曰曰 , , , , , , 存取 存取 存取 存取 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于Passing "again = between 2 and 3, which leads to the difficulty of high accumulation and high price. The recent hand (four) material mail sending and receiving Wei, continued access to the Internet on the view of the two carved, home valley ^The function of the display is indispensable for the implementation of such a Wei, the graphic display for providing various multimedia media to the user, so it must be provided for the temporary storage of the small network dog class. In the large-capacity semiconductor memory device of «1" mobile electronic device because of the need for small, light, low power consumption, semiconductor memory device accommodation = increase in the time itself, increase in weight, power consumption still needs Avoid. Therefore, Action Electronics: 2 semiconductor memory devices are ready for use, considering the ease of use, sram is better when power is consumed, and it is better to serve the ship from the point of view of Otani. Therefore, it is most suitable for future actions. Electronic equipment, it can be said that each of the SRAM and DRAM The semiconductor memory device of the point. The semiconductor memory device so, use has been employed as the cell kDRAM, of substantially the same size when observed from the external SRAM and the so-called "pseudo-static random-access memory (Pseud〇 transgression
Random Access Memory，PSRAM)」之提議，PSRAM可分成二類，一為非隱藏 式更新之PSRAM，例如，JP4243087、JP5166368、JP63206994、US651592^9、 及US6693838料職均是，另―為隱藏式更新(hidden-type refresh)之 PSRAM，例如，TW88117196、US6154409、及US6285578等專利案均是。然而， 無論疋非隱藏式更新之PSRAM或者是隱藏式更新之PSRAM，仍然都需要更新 操作，結果，會有消耗功率偏高之虞，因此有必要開發出不需要更新循環 (refresh cycle )之偽靜態隨機存取記憶體PSRAM。 有鑑於此，本發明之主要目的係提出一種新穎架構且不需要更新循環 (refresh cycle )之偽靜態隨機存取記憶體晶胞，其不但能降低消耗功率， 並且兼具高集積化、高速化以及時序控制簡單等多重功效。 1246691 【發明内容】 NF、提出之偽靜態隨機存取記憶體（PSRAM)晶胞係由一電晶體 ㈣随C以及一電荷補償€路⑴所組成，其中，該電晶體係為一增 S而⑨阳體’其祕雜合到—字元線WL，源極爾馬合到—儲存節點 而合到—位元線BL，該電容11係連接在贿與接地之間， =何術貞電路伽以接受字元線WL之碰觸挪點s之霞，且僅 二2iWL之輕為低賴同時該儲存節如之輕為高電Μ，才提 β ^ =給儲存即點S。本發明所提出之偽靜態隨機存取記憶體(PSRAM) ^古料$要更新猶環（refreSh _ )，並且兼具低消耗功率、高集積 化间速化以及時序控制簡單等多重功效。 【實施方式】 而損循環的魏是藉由提供電流到電容11關償因漏電流的存在 電流到電4以因^本發日月的發明人明確地指出一侧鍵的線索：用以提供 用以I目漏電流的存在而損失的電荷之電荷補償電路⑴和 =之ί常運作的電路，例如字元视與位元輒，是可以 荷補&電路⑴盘用發明人進一步強調下述事實：當用以補償遺失電荷的電 盘位元^等對二=制_晶胞運作的電路是相互分離時，諸如字元線 憎H H 存取記憶體⑽繼胞之讀寫的控制便不需要 中1執仃對電容進行電荷補充之更新操作（refresh〇perati〇n )。而要 (psramU ^解釋上述之概念，本發明提出一種偽靜態隨機存取記憶體 =電所0rr示’其係由一電晶義、一電容器c以及一電荷 =電偷卜細術，™_合到一位元線 受字元、賴I電壓之間，而該電荷補償電路係用以接 同時該儲存節财之電於該字元線孔之_低霞 “電私，才提供-補償電流給儲存節點S。 體-電細Γ電圖曰該電荷補償電路⑴係由一開關電晶 W了刪貝ΐ曰曰體ND所組成’該開關電晶體係為_增強型娜電 1246691 晶體’其間極細以接受字元 之源極’而沒極_合到儲存合到電荷補償電晶體 _S電晶體，其間極係用以接受儲存點偾電晶體肋係為 一空乏型 顧之源極，岐極職麵’雜細匈開關電晶 ^由於本發明之電荷補償電路⑴僅於字元線 · 節點s之龍為高輕時，才提供 且儲存 本實施例完全不需要如習知齡如雨、=一4存即點S ’無可置疑地， 來進行更新循環。換句話說，所用 =fSRAM晶胞 會發生。 1新#衣所引起的缺失本實施例都不 除此之外’由於電晶體呢會在字 元件以5伏特代表高電_被導通，而在半導體 (channel)，並且這個通道可以用來讓訊息被寫入^ 儲^個通道 電容器c之儲存節點5讀出訊息，為了避免電I哭=之=存郎點S或自 補償電路⑴帽所干擾，每#字元線 ζ =自= 路=便為斷路_ 電壓為低電壓且齡節點s之電壓為高電壓時，該電荷 才认路(on)狀恶’以便提供—補償電流給儲存節點s 疋，當字元雜之電壓為低電壓且儲存節點故電 二^^ =路⑴仍呈斷路_狀態。有_補償電路⑴之^ 電壓和儲存節點S之電壓之關係請參見第五圖。 、子几踝WL之 知為了便於說明第四圖之本發明較佳實施例的工作原理，將電 之臨限電壓以Vtne來表示’電荷補償電晶體ND之臨限電壓以％碟表示 關電晶體PE之臨限電壓則以Vtpe來表*，並且為了易於推導說明，忽略了& 晶體之基底偏壓效應，注意：Vtne之值為正值，而Vtnd#Vtpe之值為負^。 (一）當字元線的電壓為高電壓且儲存節點3之電壓為低電壓時‘、 此時開關電晶體PE係呈斷路(off)狀態，故不會對儲存節點艰供補償 電流，結果可有Μ免電容器⑽正常運倾來自觸補償桃⑴的電流 所干擾。此外，由於儲存節點S之電壓為低電壓（即0伏特），且電荷補償電 晶體ND係為-空乏型NM0S電晶體，因此’可將該電荷補償電晶麵之= 1246691 電=¾至I VTND I ’其中丨Vtnd I表示臨限電廢腳之絕對值。 (二字元線的链為高電叙儲存節挪之輕也為高電屡時 電流33=1，斷_ff)« ’故不會對儲存節_供補償 户fit此外’由於儲存節點8之_為高電壓(假設寫人^ 係為電源供應電屬_，則該儲存節默高龍係等於卿 中Vtne表示電晶體NE之碎PP +两、、 _ 八 霞充電至™ V 此，可將該電荷補償電MND之源極 Γ 丨v丨與二者之較小者。 (二）當，元線的電壓為低且儲存節點s之電壓也為低電_ 此τ由於儲存續點s之電麼為低電壓（即〇伏特），因 償電晶體ND之源極電壓夯帝5 i v丨斗兩#、二 7將孩私何補 Λ η M ^ a mvv ^丨勘丨，5亥黾何補乜電晶體ND之源極電壓即 (即Vt #_存祕艰供顯錢，該關電晶_之源極賴 ™D )必射於該開關電晶舰之臨限龍V™的絕對值，亦即According to the proposal of Random Access Memory (PSRAM), PSRAM can be divided into two categories, one is non-hidden update PSRAM, for example, JP4243087, JP5166368, JP63206994, US651592^9, and US6693838 are all jobs, and are hidden updates. (Hidden-type refresh) PSRAM, for example, TW88117196, US6154409, and US6285578 are all patents. However, whether it is a non-hidden update PSRAM or a hidden update PSRAM, an update operation is still required. As a result, there is a high power consumption, so it is necessary to develop a pseudo that does not require a refresh cycle. Static Random Access Memory PSRAM. In view of the above, the main object of the present invention is to provide a pseudo-static random access memory cell with a novel architecture and no need to update a refresh cycle, which not only reduces power consumption, but also has high integration and high speed. And multiple functions such as simple timing control. 1246691 SUMMARY OF THE INVENTION NF, the proposed pseudo-static random access memory (PSRAM) cell system consists of a transistor (4) with C and a charge compensation circuit (1), wherein the cell system is an increase in S 9 Yang body 'its secret hybrid to the word line WL, the source of the horse to the - storage node and the - bit line BL, the capacitor 11 is connected between the bribe and the ground, = 贞 贞 伽 伽Accepting the word line WL touches the sway of the point s, and only the lightness of the two 2iWL is low, and the storage section is as high as the power, then the β ^ = is stored for the point S. The pseudo-static random access memory (PSRAM) proposed by the present invention has an additional function of low power consumption, high integration inter-speed, and simple timing control. [Embodiment] The Wei of the loss cycle is to provide a current to the capacitor 11 to compensate for the presence of the current due to the leakage current to the power 4 to cause the inventor of the present day to clearly indicate the clue of the side key: to provide The circuit of the charge compensation circuit (1) and the voltage that is lost by the presence of the leakage current of the I mesh, such as the word view and the bit 辄, is a charge-compensating & circuit (1) disk which is further emphasized by the inventor. Describe the fact that when the circuit of the electric disk bit used to compensate for the lost charge is separated from each other, the circuit such as the word line 憎HH access memory (10) is read and controlled. It is not necessary to perform the charge replenishment update operation (refresh〇perati〇n) for the capacitor. However, (psramU ^ explains the above concept, the present invention proposes a pseudo-static random access memory = electric station 0rr shows that it is composed of an electro-crystalline, a capacitor c and a charge = electric thief, TM_ The one-bit line is connected between the word and the voltage of the I, and the charge compensation circuit is used to connect the current storage of the money to the line of the word line. To the storage node S. The body-electricity electric circuit 曰 The charge compensation circuit (1) is composed of a switching electric crystal W and a ΐ曰曰 ΐ曰曰 ND 该 该 该 该 该 该 该 该 该 该 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 In the meantime, it is very thin to accept the source of the character' and the immersive _ is connected to the charge-compensated transistor _S transistor, and the pole is used to accept the storage point. The rib of the transistor is a source of depletion.岐 职 ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' = a 4 save, point S ' undoubtedly, to update the cycle. In other words, the The use of = fSRAM unit cell will occur. 1 new # clothing caused by the lack of this embodiment is not except 'because the transistor will be on the word component with 5 volts for high electricity _ is turned on, but in the semiconductor (channel) And this channel can be used to let the message be written to the storage node 5 of the channel capacitor c to read the message, in order to avoid the interference of the electric I cry = the Clang point S or the self-compensation circuit (1) cap, every # Word line ζ = self = road = it is open circuit _ When the voltage is low voltage and the voltage of the age node s is high voltage, the charge is recognized (on) to provide a compensation current to the storage node s 疋, When the voltage of the word cell is low voltage and the storage node is powered, the circuit (1) is still in the open state _ state. For the relationship between the voltage of the _compensation circuit (1) and the voltage of the storage node S, please refer to the fifth figure. For the convenience of explaining the working principle of the preferred embodiment of the present invention in the fourth figure, the threshold voltage of the electric power is represented by Vtne. The threshold voltage of the charge compensation transistor ND is represented by a % dish to turn off the transistor PE. The threshold voltage is expressed in Vtpe* and is ignored for easy derivation. The base bias effect of the crystal, note that the value of Vtne is positive, and the value of Vtnd#Vtpe is negative ^. (1) When the voltage of the word line is high voltage and the voltage of the storage node 3 is low voltage ' At this time, the switching transistor PE is in an off state, so the compensation current is not supplied to the storage node, and as a result, the current of the forcing capacitor (10) can be interfered by the current from the touch compensation peach (1). The voltage of the storage node S is a low voltage (ie, 0 volts), and the charge compensation transistor ND is a depletion type NMOS transistor, so 'the charge compensation electron crystal plane = 1246691 electric = 3⁄4 to I VTND I ' Among them, 丨Vtnd I indicates the absolute value of the temporary waste. (The chain of the two-character line is high-powered. The storage section is also light and high-current. The current is 33=1, broken_ff)« 'There will not be the storage section _ for the compensation of the household. In addition, due to the storage node 8 _ is a high voltage (assuming that the writer is a power supply _, then the storage section is equal to the middle of the Vtne, the transistor NE is broken PP + two, _ 八霞 charging to TM V, The source of the charge-compensated electric MND can be Γ 丨v 丨 and the lesser of the two. (2) When the voltage of the element line is low and the voltage of the storage node s is also low _ this τ due to the storage continuation point s electric power is low voltage (ie 〇 volt), due to the source voltage of the ND crystal 夯 Emperor 5 iv 丨 斗 two #, two 7 will be a child private Λ ^ M ^ a mvv ^ 丨 丨, 5 The source voltage of the ND of the 黾 乜 即 ( ( 即 即 即 即 即 即 即 即 即 即 乜 乜 乜 乜 乜 乜 乜 乜 乜 乜 乜 乜 乜 乜 乜 乜 乜 乜 乜 乜 乜 乜 乜 乜 乜 乜 乜 乜 乜 乜 乜 乜The absolute value of TM, ie
| Vtnd I ^ | Vtpe I ί此兮3保=當字元線孔之電壓為低電壓且儲存節點S之電壓也為ΐ電壓 ^電^。何補償電路⑴係呈斷路(off)狀態，因而不會對儲存節‘齡提供補 (四）田子元線的電壓為低電壓且健存節點§之電壓為高電屢時 曰=時由於儲存節献之電壓為高電壓（即卿—v™之電壓，其幅表示電 限電壓），因此，可將該電荷補償電晶麵之源極電壓充電至 V™D 1與™二者之較小者’該電荷補償電晶體肋之源極電壓 體?1£之源極賴’又由於字元線的電壓為低賴（即G伏特）， 應幵/電晶體簡、呈通路(on)狀態’於是可將儲存節點s之電壓充電至 VDD - V™丨與勸二者之較小者，故不但可將儲存節點s之高電壓由 原來寫入時之_ _ Vtne提升至卿_ Vtne+丨v獅丨與讎二者之較小者，並 t依此重複步驟，只要時間夠長，即可將儲存節點8之電壓充電至丽之電 =位。結果，不但可有效補償電容器因漏電流而損失的電荷，並且也能 錯由將儲存節點S之電壓由原來寫入時之㈣_ g升至·，而提高偽靜 1246691 f遺機存取記憶體⑽AM)之讀取邊際(read margin)。 【發明功效】 本發明所提出之偽靜態隨機存取記憶體(PSRAM)晶胞，具有如下功饮· 序控制簡單：由於本發明所提供之偽靜態隨機細己憶 二曰匕亚不需要更新猶環（refresh cyde )，因此不但可有效降低消耗 功率，並且也能簡化時序控制； ⑵高速化：由於本發明所提供之偽靜態隨機存取記憶體晶胞並不需要更新 1盾=裒’因此可有效謀求記憶裝置之高速化； ’ ⑶t集積化：於本發明所提供之偽靜態隨機存取記憶體晶胞僅使用了三個 电晶體以及一個電容器，並且各電晶體之間係為無比率 m ’因此可纽謀求記赚置之高集積化；° 提供之偽靜誠機存取記憶體晶胞_存節 “ Λ f時，可藉由電荷補償電路⑴以將儲存節點s之電壓 己3〜V™提細D，因此可有效提高偽靜態隨丄 此體(PSRAM)之項取邊際(read margin)。 熟悉本技術之人 雖然本發明制揭露並描述了所選之最佳實施例，但舉凡… =明目=何形式或是細節上可能的變化均未脫離本發明的精 因此’所有相關技術鱗内之改變都包括在本發明之中物^圍、内耗圍 10 1246691 【圖式簡單說明】 第二圖係顯示習知6T靜能隨 「· 一〜…叫/丨、 第三圖係顯示本發明所钱存取記憶體(SRAM)晶胞之電路示意 一. 之偽 袖—一 圖中1Tlc日日胞貫施在半導體基底上的剖面示意圖； 圖 示意圖； w靜態隨機存取記憶體(PSRAM)晶胞之電路 第四圖係顯示本發明較佳實施 電路圖； & %之偽靜態隨機存取記憶體(PSRAM)晶胞之 第五圖係顯示本發明較佳實Vtnd I ^ | Vtpe I ί this 兮 3 guarantee = when the voltage of the word line hole is low voltage and the voltage of the storage node S is also the voltage ^ ^ ^. The compensation circuit (1) is in an off state, so that the voltage of the storage node 'supplement is not provided. (4) The voltage of the field element line is low voltage and the voltage of the health node § is high power and time 曰 = when it is stored The voltage of the contribution is high voltage (ie, the voltage of qing-vTM, the amplitude of which represents the voltage limit voltage). Therefore, the source voltage of the charge compensation plane can be charged to VTMD 1 and TM. The smaller one 'the source of the charge-compensated transistor ribs? The source of the voltage is very high." Since the voltage of the word line is low (ie, G volts), the 幵/transistor is simple and the path is on. The state 'then can charge the voltage of the storage node s to the lower of VDD - VTM丨 and advise, so that the high voltage of the storage node s can be increased from the original _ _ Vtne to the _ Vtne+丨v 丨 丨 丨 雠 较小 , , t t t t t t t t 重复 重复 重复 重复 重复 重复 重复 重复 重复 重复 重复 重复 重复 重复 重复 重复 重复 重复 重复 重复 重复 重复As a result, not only can the electric charge lost by the leakage current be effectively compensated, but also the voltage of the storage node S can be increased from (4)_g to the original write, and the pseudo-static 1246691 f-enable access memory can be improved. (10) AM) Read margin. [Effects of the Invention] The pseudo-static random access memory (PSRAM) cell provided by the present invention has the following functions: simple control of the pseudo-static random sequence, which is provided by the present invention, does not need to be updated. Refuse cyde, therefore not only can effectively reduce power consumption, but also simplify timing control; (2) high speed: because the pseudo-static random access memory cell provided by the present invention does not need to update 1 shield = 裒 ' Therefore, the speed of the memory device can be effectively improved; '(3)t accumulation: only three transistors and one capacitor are used in the pseudo-static random access memory cell provided by the present invention, and the transistors are not The ratio m ' can therefore be used to find the high accumulation of the earning; ° provided by the pseudo-quiet machine access memory cell _ memory section " Λ f, can be used by the charge compensation circuit (1) to store the voltage of the node s 3~VTM is fine D, so it can effectively improve the pseudo-static random margin of this body (PSRAM). Those who are familiar with the technology, although the invention discloses and describes the best implementation selected example, However, all the changes in the form or details of the details are not deviated from the essence of the present invention. Therefore, all the changes in the relevant technical scales are included in the present invention, and the internal friction is 10 1246691. Brief Description] The second figure shows the conventional 6T static energy with "· a ~ ... called / 丨, the third picture shows the circuit of the money access memory (SRAM) unit cell of the invention. 1Tlc is a cross-sectional view of a semiconductor substrate applied to a semiconductor substrate; a schematic diagram of a static random access memory (PSRAM) cell; a fourth circuit diagram showing a preferred embodiment of the present invention; & % The fifth diagram of the pseudo static random access memory (PSRAM) unit cell shows that the present invention is better
BL C N1 N3 ND P1 PE T WL 壓和儲存節點S之雷沒之電荷補償電路的狀態與字元線WL之電 【主要元件符號說明】㈣關係圖。 位元線 電容器 _〇S電晶體 NMOS電晶體 電荷補償電晶體 PMOS電晶體 開關電晶體 電晶體 字元線 BL 互補位元線 D1 二極體 N2 丽0S電晶體 N4 NMOS電晶體 NE 增強型NMOS電晶體 P2 PMOS電晶體 S 儲存節點 VDD電源供應電壓 1 電何補償電路BL C N1 N3 ND P1 PE T WL The state of the charge compensation circuit of the voltage and storage node S and the power of the word line WL [Description of main component symbols] (4) Diagram. Bit line capacitor _〇S transistor NMOS transistor charge compensation transistor PMOS transistor switch transistor transistor word line BL complementary bit line D1 diode N2 丽 0S transistor N4 NMOS transistor NE enhanced NMOS Crystal P2 PMOS transistor S storage node VDD power supply voltage 1 electric compensation circuit