CN104409094B - The transistor memory unit of subthreshold value 6 - Google Patents

Abstract

The invention belongs to the technical field of integrated circuit memory, in particular to a sub-threshold 6-tube memory unit. Its unit structure includes an inverter, a storage PMOS transistor, a power feedback PMOS transistor and two NMOS transmission transistors. The inverter is cross-coupled with the storage PMOS transistor to form the storage core of the memory, and their power supply voltage is controlled by the power feedback transistor; the two NMOS transmission transistors are respectively connected to the two storage nodes to form the read and write circuits of the memory unit ;The power feedback tube is used to control the power supply of the entire storage unit; the storage unit writes data into the storage unit through the differential bit line, and reads the data through the single-ended bit line, that is, through the transmission NMOS tube and the inversion The pull-down path formed by the pull-down tube of the device reads the data to the bit line. The invention has smaller area, very low leakage current, and higher stability of low-voltage operation.

Description

Subthreshold 6-tube memory cell

technical field

The invention belongs to the technical field of integrated circuit memory design, and in particular relates to a register file (RegisterFile) and a static random access memory (Static Random Access Memory, SRAM) unit.

Background technique

With the discovery of process technology, the issue of power consumption has attracted more and more attention from chip designers. The memory, as an important part of the chip, usually occupies most of the area of the chip and dominates the main performance and power consumption of the chip. Therefore, reducing the power consumption of the memory can effectively suppress the power consumption of the chip. Especially for those electronic products that work on batteries, such as medical devices, wireless sensors, portable computers and other portable devices, they have stricter constraints on power consumption, and more urgently need low-power memories.

Lowering the power supply voltage is considered the most direct and effective way to reduce power consumption, because dynamic power consumption is proportional to the square of the power supply voltage, while static power consumption is mainly leakage current power consumption, which is proportional to the exponential of the power supply voltage . The traditional 6-transistor (6 Transistors, 6T) SRAM is difficult to work at a voltage lower than 0.7 volts due to the existence of read and write constraints inside the memory cell and is prone to read corruption. Therefore, designers are more willing to use various new SRAMs to replace 6-tube SRAMs for low-voltage operation. For example, in 2007, the author J. P. Kulkarni published "A 160 mV robust Schmitt trigger based subthreshold SRAM" in the journal "Journal of Solid-State Circuits", proposing a 10-tube memory cell in the form of a Schmitt trigger; in 2011, the author M. F. Chang published "A 130 mV SRAM with expanded write and read margins for subthreshold applications" in the journal "Journal of Solid-State Circuits", proposing a sub-threshold 9-tube SRAM that can work at a voltage of 130mV; in 2009, the author I. J. Chang , published "32 kb 10T sub-threshold SRAM array with bit-interleaving and differential read scheme in 90 nm CMOS" in the journal "Journal of Solid-State Circuits", and proposed a sub-threshold 10TSRAM with bit-interleaving function; in 2012, the author Ming-Hsien Tu, "A Single-Ended Disturb-Free 9T Subthreshold SRAM With Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and adaptiveRead Operation Timing Tracing in Journal of olid-StateCircuits" ”, a subthreshold 9TSRAM was proposed. Although these SRAMs can work at sub-threshold voltages, these memory cells either consume a large area, or have too much leakage current, or read and write speeds are too slow. In response to these problems, the present invention proposes a sub-threshold 6-transistor storage unit, which has high operational stability in the low-voltage domain, only needs 6 transistors, has a small area, and it can be fed back by an internal power supply. The leakage current of the memory cell is suppressed.

Contents of the invention

The object of the present invention is to provide a sub-threshold storage unit which has a small area, can effectively suppress leakage current, and can work under low voltage.

The sub-threshold storage unit provided by the present invention includes:

An inverter and a storage PMOS transistor. Wherein, the power supply end of the inverter is connected to the virtual power supply node, and the ground end is connected to the global ground. The drain of the storage PMOS transistor is connected to the input of the inverter, the gate is connected to the output of the inverter, and the source is also connected to the virtual power node. That is, the inverter is cross-coupled with the storage PMOS transistor to form the storage core of the storage unit, and the input and output of the inverter are the first storage node and the second storage node of the storage unit. Wherein, the second storage node has a sound pull-up network and a pull-down network, while the first storage node has only a pull-up network but no pull-down network.

A power feedback tube. Wherein, the drain of the power feedback transistor is connected to the virtual power node, the source is connected to the global power supply VDD, and the gate is connected to the first storage node. That is, the source feedback transistor and the storage PMOS transistor form a power supply closed-loop feedback loop.

Two transmission NMOS tubes. Among them, the drain of the first transfer NMOS transistor is connected to the second storage node, the source is connected to the bit line BL, and the gate is connected to the global word line WL; the drain of the second transfer NMOS transistor is connected to the first storage node The nodes are connected, the source is connected to the complementary bit line BLB, and the gate is connected to the write word line WWL.

When the storage unit is in a non-working state, the cross-coupling feedback loop inside the storage interacts with the closed-loop feedback loop of the power supply to jointly maintain the stored data.

When the memory cell performs a write operation, the global word line WL and the write word line WWL are turned on, and data is written into the storage node through the complementary bit lines BL and BLB.

When the memory cell performs a read operation, the global word line WL is turned on, and the write word line WWL is turned off. The data passes through the first NMOS transmission transistor and the pull-down transistor of the inverter to form a pull-down path, and the data is read out to the bit line BL. Moreover, since the first storage node lacks a pull-down network, any voltage rise at the second storage node during the read operation will not destroy the stored data, that is, read corruption is eliminated.

The 6T sub-threshold storage unit provided by the present invention has higher working stability under low voltage, and has smaller area and sub-threshold leakage current.

Description of drawings

Fig. 1 is a schematic diagram of the circuit structure of the present invention.

Fig. 2 is a schematic diagram of circuit operation in the state of storing "0" according to the present invention.

Fig. 3 is a schematic diagram of circuit operation in the state of storing "1" according to the present invention.

FIG. 4 is a schematic diagram of the operation of the read circuit of the present invention.

Fig. 5 is a schematic diagram of the operation of the writing "1" circuit of the present invention.

Fig. 6 is a schematic diagram of the operation of the writing "0" circuit of the present invention.

detailed description

The present invention describes a sub-threshold 6-tube storage unit, and the design ideas and examples of the present invention are described below.

Fig. 1 shows the circuit structure of the sub-threshold 6-tube memory cell realized by the present invention. The inverting PMOS transistor M1 and the inverting NMOS transistor M2 form an inverter, and the power supply terminal of the inverter is connected to the virtual power supply node VV _DD . The drain of the PMOS transistor M3 is connected to the input QB of the inverter, the gate is connected to the output Q of the inverter, and the source is also connected to the virtual power supply node VV _DD . That is, the inverter and the PMOS transistor M3 are cross-coupled to form the storage core of the storage unit, and nodes Q and QB are two storage nodes of the storage unit. Wherein, the storage node Q has a sound pull-up network and a pull-down network, while the storage node QB only has a pull-up network but no pull-down network.

The drain of the PMOS transistor M4 is connected to the virtual power supply node VV _DD , the source is connected to the global power supply VDD, and the gate is connected to the storage node QB. In this way, M4 and M3 form a power supply closed-loop feedback loop.

The drain of the transfer NMOS transistor M5 is connected to the storage node Q, the source is connected to the bit line BL, and the gate is connected to the global word line WL; the drain of the transfer NMOS transistor M6 is connected to the storage node QB, and the source is connected to the complementary The bit line BLB is connected, and the gate is connected to the write word line WWL.

FIG. 2 shows the circuit operation of the memory cell of the present invention in a "0" state. At this time, the global word line WL and the write word line WWL are both "0", BL is high level, and BLB is low level, low and Q="0", QB="1". M3 is turned on, and the storage node QB is charged through the power feedback loop formed by M3 and M4. When the voltage of QB reaches a certain value, M1 and M4 are turned off, and M2 is turned on. The final value of this voltage is determined by the subthreshold leakage current through M4 and M6. The storage unit keeps the data through the feedback loop of M2 and the power supply.

FIG. 3 shows the circuit operation of the memory cell of the present invention in a "1" state. At this time, Q="1", QB="0", M2 and M3 are turned off, while M1 and M4 are turned on. The storage node Q is precharged to a high level through the stacked M1 and M4, and maintained. Since the node QB lacks a pull-down network and cannot maintain "0", the sub-threshold leakage current through M3 will charge QB, and as the voltage of QB increases, it will react on the gate of M4 and inhibit the node VVDD. voltage, the leakage current through M3 will decrease due to the reduction of the source voltage. At the same time, due to the rise of the voltage of QB, there is a voltage difference between QB and the bit line BLB, so the transmission tube M6 also has a leakage current, thereby ensuring the "0" data of QB. The final voltage value at node QB is determined by the leakage current through M3 and M6. At this time, the storage unit keeps the data through M1, the power supply feedback loop and M6.

FIG. 4 shows the circuit operation in the read mode of the memory cell of the present invention. When the memory cell is read, the write word line WWL is kept low, the global word line WL is high, and the BL precharge is high and floated. Data is read onto the bit lines via M2 and M5. During the read operation, due to the process deviation, the voltage value of the node Q may reach a high level, but since the node QB has no pull-down NMOS transistor, the raised voltage value will not affect the value of the existing QB. However, in traditional memory cells, such read corruption due to process deviation cannot be avoided. So, in other words, the present invention completely eliminates read corruption.

FIG. 5 shows the circuit operation of the memory cell write "1" mode of the present invention. When the memory cell writes "1", both the global word line WL and the write word line jump to high level, BL is precharged to high level, and BLB is pulled down to low level. The node QB is completely pulled to "0" by M6, and then the node Q is charged to "1" by the joint action of M1, M4 and M5.

FIG. 6 shows the circuit operation of the memory cell write "0" mode of the present invention. At this time, BLB is precharged to a high level, and BL is pulled down to a low level. The node Q is fully pulled to "0" by M5, and then the node QB is charged to "1" by the power feedback and the joint action of M6. This differential write operation has a larger static noise limit.

Claims (4)

1. A sub-threshold 6-tube storage unit, characterized in that it comprises: An inverter is connected to a storage PMOS transistor; wherein, the power supply terminal of the inverter is connected to the virtual power supply node, and the ground terminal is connected to the global ground; the drain terminal of the storage PMOS transistor is connected to the input of the inverter, and the gate is connected to the inverter The output of the phase is connected, and the source is also connected to the virtual power node, that is, the inverter is cross-coupled with the storage PMOS transistor to form the storage core of the storage unit, and the input and output of the inverter are the first storage of the storage unit. node and the second storage node; wherein, the second storage node has a sound pull-up network and a pull-down network, and the first storage node only has a pull-up network without a pull-down network; the inverter is composed of an inverter Phase PMOS tube (M1) and reverse phase NMOS tube (M2); A power feedback tube; the drain of the power feedback tube is connected to the virtual power node, the source is connected to the global power supply VDD, and the gate is connected to the first storage node, that is, the power feedback tube and the storage PMOS tube form a power supply closed feedback loop; Two transfer NMOS transistors; among them, the drain of the first transfer NMOS transistor is connected to the second storage node, the source is connected to the bit line BL, and the gate is connected to the global word line WL; the drain of the second transfer NMOS transistor The pole is connected to the first storage node, the source is connected to the complementary bit line BLB, and the gate is connected to the write word line WWL. 2. The sub-threshold 6-tube memory unit according to claim 1, wherein when the memory unit is in a non-working state, the internal cross-coupling feedback loop interacts with the power supply closed-loop feedback loop to jointly maintain the stored data. 3. The sub-threshold 6-tube memory cell according to claim 1, characterized in that: when the memory cell performs a write operation, the global word line WL and the write word line WWL are turned on, and data is written into the memory cell through complementary bit lines BL and BLB. storage nodes. 4. The sub-threshold 6-transistor memory unit according to claim 1, characterized in that: when the memory unit performs a read operation, the global word line WL is switched on, and the write word line WWL is turned off, and the data passes through the first NMOS transmission tube and The pull-down tube of the inverter forms a pull-down path to read data to the bit line BL.