TWI239041B - Manufacturing method of low-temperature poly-silicon device - Google Patents

Abstract

A manufacturing method of low-temperature poly-silicon device is revealed in the invention. At first, a buffer layer is formed on the substrate. Then, the a-Si:H is deposited on the buffer layer and is undergone with a baking process to remove hydrogen. Laser is then used to melt a-Si:H and to crystallize a-Si:H to form poly-silicon. After that, poly-silicon island is defined after the photolithographic process and etching process. The gate oxide layer is deposited; and the metal layer is formed on the gate oxide layer. The photolithographic and etching method is used to define the regions of the gate and the data line. By using the gate as a mask, implantation of semiconductor ions is then conducted to define the source and the drain. Then, the passivation layer is formed and is undergone with an etching process to form the contact holes. Transparent conductive material is filled into the contact hole to complete the connection between the source/drain and the data line. Finally, the pattern of pixel electrode is formed to manufacture the low-temperature poly-silicon device.

Description

1239041 发明 Description of the invention: [Technical field to which the invention belongs] The present invention relates to a method for manufacturing a low-temperature polycrystalline silicon device, and more particularly to a method with a simplified process and better crystallinity of polycrystalline silicon in order to improve the device characteristics of the low-temperature polycrystalline silicon device Low-temperature polycrystalline silicon device manufacturing method. [Prior art] As shown in Figures 4A to 4E, the conventional low temperature polycrystalline silicon (

The manufacturing process of Low Temperature Poly Silicon) devices is based on the bottom gate method. It is formed by sputtering A1 (aluminum) or Mo (platinum) metal on the substrate 8 and etching the yellow electrode to form a gate electrode 8 1, a source electrode 8 2 and a drain electrode (drain electrode) 8 3, as shown in FIG. 4A; then, a gate oxide layer (gate 〇xide) 8 * and low hydrogen amorphous silicon (a-Si: Η) are deposited using a chemical vapor deposition (CVD) method. Go up, use the laser to melt the amorphous silicon to crystallize it into Poly-Si 8 5 and then etch the poly-Si lsland by yellow light etching, as shown in Figure 4B; Then use the back exposure mode to use the gate electrode 8 丄, the source electrode 8 2 and the electrode electrode 8 3 as photomasks to implant N + ions, as shown in Figure 4c; remove the photoresist and then deposit-coat Layer (passivati⑽) 8 6 and etch the area of contact hole 8 7 as shown in Figure 4D; then fill the contact hole with transparent conductive material (IT〇) 8 8 to complete S / The connection between D and the data line, and finally the pattern of the pixel clectorde is formed, as shown in the 4th figure of the dp channel. The low temperature polycrystal is completed. The fabrication of the device. 5 1239041 The low-temperature polycrystalline silicon device manufactured by the aforementioned bottom gate method has a structural form in which poly-Si is formed above the gate 8 1 '. Therefore, the manufacturing process is such that amorphous silicon is deposited on the gate of a metal material. On the 8 1 ', the amorphous stone is melted and crystallized by laser irradiation. In this process, because the metal gate 8 1 has better thermal conductivity, it will dissipate the thermal energy and cause the amorphous silicon to melt and crystallize into polycrystalline silicon. The particle size of (poly_Si) is small, and the speed of mobility is slow. In this case, the device characteristics of the low-temperature polycrystalline silicon device will be poor. Therefore, it is necessary to improve the existing low temperature polycrystalline stone process. SUMMARY OF THE INVENTION The main object of the present invention is to solve the above-mentioned problems and provide a method for manufacturing a low-temperature polycrystalline silicon device with a simplified manufacturing process and better crystallinity of polycrystalline silicon to improve the characteristics of the low-temperature polycrystalline silicon device. To achieve the foregoing object, the method for manufacturing a low-temperature polycrystalline silicon device according to the present invention includes the following steps: forming a buffer layer on the substrate, and then depositing a layer of core Si (hydrogen-containing amorphous stone) on the buffer layer, and then using a high-temperature oven For baking to remove the gas' and then use laser to melt a-Si (not material) to crystallize into polycrystalline = i After yellow light and etching, polycrystalline silicon islands can be defined, and then gate oxidation is deposited Layer; depositing a metal layer on the gate oxide layer, and defining the area of the gate metal layer and the data line metal layer using yellow light etching method; using the formed gate as a photomask for semiconductors The implantation of N + ions 1239041 can define the source / drain region; form a coating layer, and then etch out the region between the source / drain and the data line electrode to form a contact hole; low resistance value A transparent conductive material is filled into the contact hole to complete the connection between the source / drain and the data line. Finally, the pattern of the pixel electrode is formed to produce a low-temperature polycrystalline chip element. As a result, the polycrystalline silicon (poly-Si) of the present invention is formed under the gate. Therefore, the polycrystalline silicon has better crystallinity during the process of melting a_Si by laser to form poly-Si. , And can achieve the effect of improving the characteristics of the low-temperature polycrystalline silicon device. Moreover, the manufacturing method of the present invention can be completed with only four masks.

The manufacture of TFT low-temperature polycrystalline silicon devices in the form of a top gate has the effect of simplifying the process. The above and other objects and advantages of the present invention are not difficult to obtain in-depth understanding in the following detailed description of the selected embodiments and the accompanying drawings. Of course, the present invention allows some differences in the arrangement or arrangement of other parts, but the selected embodiment is explained in detail in this specification and its structure is shown in the drawings. [Embodiment] $ Please refer to FIG. 1A to FIG. ^, The figure shows the structure of the first embodiment used in the present invention 'This is for illustration purposes only and is not subject to such a structure in patent applications. limit. The manufacturing method of the low-temperature polycrystalline stone element of this embodiment is shown in Figs. 1A to 1 by using a manufacturing method of a clear P-type transistor) or __type: crystal 1239041 body) as an example, and It includes the following steps: As shown in Figure 1A, 'It is deposited on the substrate 10 to form a buffer layer (buffer layer) ^, which is made of sl () 2, SiNx, TEOS () xide and other materials. Then, a layer of a_sij 丨 (hydrogen-containing amorphous silicon) is deposited on the buffer layer 丄: the thickness of the deposition is about 5. ㈠5. " 矣, then use a high-temperature baking phase 乂 400 C 500 C to a_Si: H (hydrogen-containing amorphous stone) for baking 2 ~ to remove hydrogen, and then melt the a-Si (amorphous Shi Xi) crystallized into polycrystalline silicon. After passing through the yellow material, Poli_Si Island (polycrystalline silicon island) 12 can be defined, and then chemical vapor deposition (_ deposition of gateoxlde (interpolar oxide layer)) 1 3 thickness of about 500 ~ 2000 Angstroms, as described in Figure A, using the rhyme method to deposit the mesh tungsten alloy) on the gateQXidei 3 thickness of 1GGG ~ 3GGG Angstroms, and the gate (open electrode metal layer ) The area between 1 4 and data line lnetal (data line metal layer) 5 is defined by the method of yellow light rice carving, as shown in Figure 1 B > Js ° Biliary kappa (mask) can be implanted with n or p 'to define the SQUrce (source) 16 / d_ (promise) 17 area, as shown in Figure 丄 c. Fourth, the use of chemical vapor deposition (CVD) to form sili_⑽ pool silicon nitride or TE0 〇xide as a passivation layer (passivation) 18, the thickness of 3,000 ~ 50000 Angstroms, and the use of 1239041 The yellow light etching method etches out a region of a source / drain and a data line electrode to form a contact hole 19, as shown in FIG. 1D. 5. Fill the contact hole 19 with a low-resistance transparent conductive material (such as T0, IZ〇 ..) A to complete the connection between the source / drain and the data line, and finally By forming the pattern of the pixel electrode, as shown in Figure VIIE, a low-temperature polycrystalline second device can be obtained. Because the structural morphology of the present invention is formed by polycrystalline silicon (poly-Si) under the gate to form a top gate (top-closed) morphology, a-Si is melted by laser to crystallize it into polycrystalline silicon (p 〇b—Henzhong will not be described as the previous technology because the extreme heat conduction between the metal materials is better, and the heat energy material is dispersed H, which can melt the amorphous sand and crystallize into polycrystalline stone (PQly-Si) The grain size is large, and the speed of the mobility is better, so that the crystallinity of the polycrystalline stone obtained is better. Efficacy of element characteristics. As stated on the post, the process of the present invention can effectively improve the following effects: 1 · Poly-Si crystals have a large grain size and a high MobUity ) Speed is better, and can make crystallization / Xunzhixi said that the crystallinity of Shixi is better, and can achieve the effect of improving the characteristics of low-temperature polycrystalline silicon devices. 2 · Only need four masks to complete τ〇 Manufacture of 1239041 TFT low-temperature polycrystalline silicon device in ρ-post (upper pole) form, with The effect of the simplified process. Of course, there are still many examples of the present invention, only the details of which are changed. Please refer to FIG. 2A to FIG. 2F, which is a second embodiment of the present invention, which is manufactured with LDD ( Low doped drain) CM0s (metal oxide semiconductor) is taken as an example, which includes the following steps:-As shown in Fig. 2A, firstly deposited on the substrate 2Q-a layer thickness of 2000 ~ 5000 angstroms SiO2 is used as a buffer layer, and then a method of depositing 500-1500 Angstroms of a-Si: H (hydrogen-containing amorphous silicon) on S02 is used, and the low-hydrogen amorphous silicon is baked using a temperature oven. Hydrogen, temperature 400 C ~ 500 C 'time 2 ~ 4hrs, then use laser to melt a_

Si (amorphous silicon) crystallizes it into polycrystalline silicon. After yellow light and etching, a poly-Si Isiand (polycrystalline silicon island) 2 1 A, 2 1 B can be defined. 2. As shown in Figure 2B, N + implantation is performed. Phosphorus (phosphorus) is implanted in the source 2 2 A / drain 2 3 A area of the M type. 2. As shown in FIG. 2C, a chemical oxide deposition method (CVD) is used to deposit gate oxide 24. The material can be silicon oxide or silicon nitride or TEOS oxide. Fourth, sputtering is then used. The method is to deposit Mww (1000-3000) on 0xide2 4 and then deposit gate metal (gate) 2 5 a, 2 5 B and data line metal 2 6 a, 2 6 B The area is defined by yellow light etching, and then the gate 1239041 is formed.

Metal 2 5 A and data 1 ine metal 2 6 A are used as masks for ΓΓ implantation. In this way, LDD (low-doped) 2 γ regions can be formed. 5. As shown in FIG. 2D, P1 implantation is performed, and a boron is inserted into the source 2 2 A / drain 2 3 A region of the ρ type. 6. As shown in FIG. 2E, a silicon oxide or silicon nitride or TEOS oxide is formed on the gate electrode and the data 1 ine electrode by chemical vapor deposition ((^ 0)) as a passivation layer 2 8. The thickness is 3000 ~ 5000 angstroms, and the area of source / drain and data line electrode is etched to form a contact hold (contact hole) using the method of yellow light relief. 7. As shown in Figure 2F, the transparent conductive material a ( For example, no, IZ0 ··) are filled in Contact hole 2 9 to complete the connection between s / D and data line, and finally the pattern (pattern) of pixel eiectrode (pixel electrode) is formed. This embodiment is based on the invention The method is applied to the manufacture of CMOS (metal oxide semiconductor) low-temperature polycrystalline silicon devices. In this embodiment, the equivalent of "the polycrystalline silicon has better crystallinity" and the simplified Γ process in the first embodiment can be achieved. See also Section 3 Figures A to 3f are the third embodiment of the present invention. The illustration is based on the manufacture of LOS (N-type transistor) with LDD (low doped drain), which includes the following steps: 1239041 four Fifth, as shown in FIG. 3A, on the substrate layer 3 buffer layer 3 1 (, a friend layer, which can be made of Si02, SiNx, / TEOS Oxide, etc.) " Μ 贝 500〜looo 埃 厚 的 a— Si: H (low-hydrogen amorphous stone), then use a high temperature oven to bake the low-hydrogen amorphous silicon (temperature 400 ° C ~ 500 ° C, 2 ～ 4hrs between day and night), and then use the laser Melt a-si (amorphous silicon) to crystallize it into polycrystalline silicon. After yellow light and etching, P〇ly-Si

Island (polycrystalline stone island) 3 2 can be defined, and then chemical vapor deposition (CVD) is used to deposit gate oxide3 3 (gate oxide layer) with a thickness of 500 to 2000 angstroms. _ As shown in Figure 3B, A1 / Cr will be sequentially deposited by sputtering method.

Cr / Al or Al / Mo is on the gate oxide. In this embodiment, M (M) / M ((mesh)) is used as an example, and the description of ⑼ 仏 Metai 3 4 and data line metal 3 5 The area is etched out using the yellow light etching method. The name of the two metals is engraved at different rates using the rice engraving solution. At this time, the upper layer Mo and the lower layer Λ1 will be formed with a distance of 0.5 5 ~. As shown in Fig. 3C, the upper layer of mo is used as a mask (MASK), and Phosphorus (phosphorus) is implanted to form a region of N1. As shown in Figure 3D, immediately after Mo (molybdenum) is etched, A1 (aluminum) is used as MASK to form an N-LDD region. As shown in Fig. 3E, a passivating iayer (coating layer) 3 6 is deposited on the gate electrode and the data line electrode, and a contact hole (contact hole) 3 7 area is defined. 12 1239041 6. As shown in Figure 3 F, fill the low-resistance transparent conductive material A (such as IT〇, 〇 ··) into the Contact hole, complete the connection between S / D and the data line, and finally pixel electr〇 The formation of de. This yoke example is equivalent to the "first polycrystalline silicon with better crystallinity" and "simplified manufacturing process" equivalent to the first embodiment. The disclosure of the embodiments described above is used to illustrate the present invention, and is not intended to limit the present invention. Therefore, changes in numerical values or replacement of equivalent components should still belong to the paradigm of the present invention. '' From the above detailed description, those skilled in the art can understand that the present invention can indeed achieve the aforementioned purpose, and it has indeed complied with the provisions of the Patent Law and filed an application. 13 1239041 [Schematic description] Figures 1A to 1E are schematic diagrams of the manufacturing process of the first embodiment of the present invention. Figures 2A to 2F are schematic diagrams of the manufacturing process of the second embodiment of the present invention. Figures 3A to 3F The diagram is a schematic diagram of the process of the third embodiment of the present invention. Figs. 4A to 4E are diagrams of a conventional low-temperature polycrystalline silicon process. [Illustration of the drawing number] (conventional part) Substrate 8 0 gate electrode 8 1 source ( source ckctn) de) 8 2 drain electrode 8 3 gate oxide 8 4 polycrystalline stone island 8 5 other passivation 8. 6 contact hole 8 7 transparent Conductive material (ITO) 8 8 (part of the invention) Substrate 1 0 buffer layer 1 1 Poli-Si Island 12 gate oxide 1 3 gate metal Layer) 1 4 data line metal (data line metal layer) 1 5

source (source) 1 6 drain (drain) 1 7 passivation 1 8 contact hole 1 9 transparent conductive material A 14 1239041 substrate 2

poly-Si Island 21A, 21B

source 2 2 A

drain (drain) 2 3 A gate oxide (gate oxide) 2 4

gate Metal 2 5 A, 2 5 B

data line metal 2 6 A, 2 6 B LDD (low doped drain) 2 7

source (source) 2 2 B

Drain 2 3 B Passivation 2 8 contact hold 2 9 Substrate 3 0 Buffer layer 3 1 Poly-Si Island 3 2 gate oxide 3 3 gate Metal 3 4 data line metal 3 5 passivation layer (peer layer) 3 6 contact hole (contact hole) 3 7 15

Claims (1)

1239041 The scope of patent application: 1. A method for manufacturing a low-temperature polycrystalline silicon element, which includes the following steps: first forming a buffer layer on a substrate, and then depositing it on the buffer layer-" ι.Η ( (Silicon)) Then use a high-temperature oven to remove the plutonium, and then use a laser to melt the heart (amorphous stone) to crystallize it into polycrystalline stone. After yellow light and button carving, polycrystalline stone island Can be defined, and then deposit a gate oxide layer; deposit a metal layer on the interlayer oxide layer, and define the area of the gate metal layer and the lean metal line using the yellow light button method纟 ·, using the formed gate as a mask to implant semiconductor ions, the source / drain region can be defined; a coating layer is formed, and then the source / non-electrode and the data line electrode are formed The area is etched out and then a contact hole is formed; a transparent conductive material is filled into the contact hole to complete the connection between the source / electrode and the data line, and finally the pattern of the pixel electrode is formed to obtain a low-temperature polycrystal Eve component. Qin 2. According to the method for manufacturing a low-temperature polycrystalline silicon element described in item 1 of the scope of the patent application, wherein the buffer layer (bL1ffer layer) is made of Si02, siNx, TEOS Oxide and other materials. 3 · Manufacture of low temperature multi-elements according to item 1 of the patent scope; r method, wherein the thickness of the low hydrogen amorphous silicon is about 500 ~ 1000 angstroms. 4 According to the item of scope of patent application The low-temperature polycrystalline stone element manufacturing method 16 1239041 method 'which is interesting in a high-temperature oven .... In particular, the process of roasting to remove lice is in the temperature range of C ~ 50GC for roasting for 2 ~ such as to remove hydrogen. • Make a solution according to the low-temperature polycrystal described in item 1 of the scope of patent application ^ wherein the gate oxide layer is formed by a chemical vapor deposition method (_ Shen and formed with a thickness of about 500 to 2000 angstroms.) • According to the scope of patent application The method for manufacturing a low-temperature polycrystalline silicon element described in item 1, wherein the process of depositing a metal layer on the gate oxide layer uses money Mining method deposits _ (_ alloy) on the gate oxide layer with a thickness of 1000 ~ 3000 angstroms. 7. According to the method for manufacturing a low-temperature polycrystalline silicon element described in item 1 of the scope of the patent application, wherein the coating layer is formed by a chemical vapor deposition method (CVD), and the silicon oxide or silicon mtnde is used. Orcon OXide is a material with a thickness of 3 to 5000 angstroms. 8 · In accordance with the patent, please request a patent! Manufacturer of low temperature multi-material components In the method, the transparent conductive material may be a material such as ITQ or IZO. 9 · According to the patent, please refer to the method for manufacturing low-temperature multi-elements described in item 丄 of the patent, wherein the process of plating a metal layer on the gate oxide layer is performed by sputtering 1 or A1 / Mo in order. 2. The lower two layers of metal 俾 use the different ㈣ rates of the two layers of metal to form a gap between the upper layer and the lower layer, and then use the upper layer as a photomask to implant Phosphorus (scale) into the area of ① 丨, which is immediately next to the upper layer. After the moment, 'the lower layer is used as the mask to form the N-⑽ region. 〇. According to the method of manufacturing low-temperature polycrystalline silicon devices described in item i of the patent application 17 1239041 method, in which phosphorus (scale) is first implanted into the source / drain area of N type, and then the formed gate metal and data line metal are used. The fT is implanted as a MASK to form an LDD (low-doped drain) region, and then a boron (boron) is implanted into the source / drain region of the P type to form an LDD (low-doped) Drain) CMOS (metal oxide semiconductor). 18