CN102832169A - Array substrate and preparation method thereof and display device - Google Patents
Array substrate and preparation method thereof and display device Download PDFInfo
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 19
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Abstract
The invention discloses a preparation method of an array substrate. A microcrystal silicon film layer serves as an active layer in the array substrate. A forming process of the microcrystal silicon film layer includes: continuously forming an amorphous silicon film layer and a metallic film layer on the substrate, making a heat conducting layer formed by the metallic film layer through a composition process, performing a laser crystallization process to enable the amorphous silicon film layer right below the heat conducting layer to form the microcrystal silicon film layer, and removing the heat conducting layer. The invention further discloses the array substrate prepared by the method and a display device with the array substrate. By means of the laser crystallization process for crystallization of the amorphous silicon through the heat conducting layer, the array substrate and the preparation method thereof and the display device have the advantages of low cost, high stability and high uniformity. A thin-film transistor made of the microcrystal silicon has the advantages of high mobility, high stability and the like.
Description
Technical field
The present invention relates to the Display Technique field, particularly relate to a kind of array base palte and preparation method thereof, display device.
Background technology
Low temperature polycrystalline silicon (LTPS) has higher electron mobility; Be considered to AMLCD (AMLCD) of the best and the backplane technology of AMOLED; Solid-phase crystallization method (SPC) or PRK crystallization (ELA) technology of adopting are made polycrystalline SiTFT (TFT) more in the prior art.But, 600 ℃ of the required crystallization temperatures of SPC method quite high (>), cause its cost height, be unsuitable for large tracts of landization; Though ELA technology crystallization temperature is lower, equipment needed thereby is expensive, is limited by laser beam size, is unfavorable for the large tracts of land volume production.
Also existing at present many crystallization technology are by developmental research, and in order to overcome above-mentioned disadvantage, wherein microcrystal silicon (uc-Si) technology has characteristics such as high mobility, high stability, cost are low, can be used as the backplane technology of AMLCD and AMOLED.No matter adopt top grid or bottom grating structure, maximum defective is the microcrystal silicon that forms with the PECVD method, and crystallite dimension is very little, and carrier mobility is low, the electric property of TFT and less reliable.
Summary of the invention
The technical problem that (one) will solve
The technical problem that the present invention will solve is how to realize having high electric property and reliability based on thin-film transistor among the AMLCD of microcrystal silicon technology and the AMOLED.
(2) technical scheme
In order to solve the problems of the technologies described above; The present invention provides a kind of preparation method of array base palte; Active layer in the said array base palte is the microcrystalline silicon film layer; The forming process of said microcrystalline silicon film layer is: on substrate, form amorphous silicon membrane layer and metal film layer continuously, make the heat conduction layer that is formed by said metal film layer through composition technology, carry out laser crystallization technology then; Make the amorphous silicon membrane layer under the said heat conduction layer become the microcrystalline silicon film layer, more said heat conduction layer is removed.
Preparation method based on the array base palte of above-mentioned microcrystalline silicon film layer formation process; One scheme is specially: the forming process of said microcrystalline silicon film layer is designated as step 2; Said metal film layer is designated as the 3rd metal film layer, and said composition technology is designated as composition technology for the second time;
Also comprise step 1 before the said step 2: on substrate, form first metal film layer and second metal film layer continuously; Through the first time composition technology make the gate electrode that forms by said first metal film layer, and the grid line that overlaps to form by said first metal film layer and second metal film layer;
Also comprise in the step 2: on the substrate that step 1 forms, before forming said amorphous silicon membrane layer, form first insulating barrier, between said amorphous silicon membrane layer and the 3rd metal film layer, form second insulating barrier;
Also comprise step 3 after the said step 2: on the substrate that step 2 forms, make the diffusion impervious layer that is formed by said second insulating barrier through composition technology for the third time, said diffusion impervious layer is positioned at above the said microcrystalline silicon film layer;
Step 4: on the substrate that step 3 forms, make source electrode, drain electrode, passivation layer and pixel electrode successively.
Wherein, said first metal film layer is a refractory metal; Said second metal film layer is a high conductivity metal.
Wherein, said first insulating barrier, amorphous silicon membrane layer and second insulating barrier form through enhanced chemical vapor deposition; Said the 3rd metal film layer forms through sputtering method.
Wherein, said first insulating barrier is silicon nitride, silica or silicon oxynitride, and its thickness is 200nm ~ 400nm; Said second insulating barrier is silicon nitride, silica or silicon oxynitride, and its thickness is 50nm ~ 100nm; Said the 3rd metal film layer is molybdenum simple substance, titanium simple substance, molybdenum alloy or titanium alloy.
Wherein, said step 4 specifically comprises:
Step 41: on the substrate that step 3 forms, form ohmic contact layer and the 4th metal film layer continuously,, form source electrode and drain electrode through the 4th composition technology; Use the intermediate tone mask plate in said the 4th the composition technology;
Step 42: on the substrate that step 41 forms, form passivation layer, through the 5th composition technology, the preparation via hole;
Step 43: on the substrate that step 42 forms, form five metals and belong to thin layer, through the 6th composition technology, form pixel electrode, said pixel electrode links to each other with source electrode or drain electrode through via hole.
Wherein, said ohmic contact layer is N+ type doped amorphous silicon or P+ type doped amorphous silicon; Said the 4th metal film layer is molybdenum simple substance, titanium simple substance, molybdenum alloy or titanium alloy; Said passivation layer is a silicon nitride; It is indium tin oxide that said five metals belongs to thin layer.
Based on the preparation method of the array base palte of above-mentioned microcrystalline silicon film layer formation process, its another kind of scheme is specially: before the forming process of said microcrystalline silicon film layer, on substrate, be formed with resilient coating; After the forming process of said microcrystalline silicon film layer, form first insulating barrier, gate electrode, interlayer insulating film, source electrode and drain electrode, passivation layer and pixel electrode on the substrate successively.
Wherein, said resilient coating is the composite bed of silicon nitride individual layer, silica individual layer or silicon nitride and silica.
Wherein, said laser crystallization technology is the infrared laser crystallization, and it is lower to compare its cost of ELA.
The present invention also provides a kind of array base palte, and said array base palte makes through above-mentioned arbitrary preparation method.
The present invention further provides a kind of display device, and said display device comprises above-mentioned array base palte.
(3) beneficial effect
Among the preparation method of the array base palte that technique scheme provided, through heat conduction layer amorphous silicon is realized crystallization with laser crystallization technology, it is low to have a cost, the characteristics that stability is high, uniformity is high; The thin-film transistor that microcrystal silicon forms has characteristics such as high mobility, high stability; Wherein, make gate electrode, make grid line, make the LASER HEAT conducting shell with high melting point metal layer with high conductivity metal with refractory metal, and the selectivity crystallization, avoided the grid line metal to receive high-temperature damage.
Description of drawings
Fig. 1 be form in the embodiment of the invention 1 gate electrode and grid line the first time composition technical process sketch map;
Fig. 2 be form in the embodiment of the invention 1 heat conduction layer and microcrystalline silicon film layer the second time composition technical process sketch map;
Fig. 3 is the sketch map that forms the technical process of composition for the third time of diffusion impervious layer, ohmic contact layer and electrode metal layer in the embodiment of the invention 1;
Fig. 4 is the sketch map that forms the 4th composition technical process of source electrode and drain electrode in the embodiment of the invention 1;
Fig. 5 is the sketch map that forms the 5th composition technical process of via hole in the embodiment of the invention 1;
Fig. 6 is the sketch map that forms the 6th composition technical process of pixel electrode in the embodiment of the invention 1;
Fig. 7 is the process sketch map that forms heat conduction layer and microcrystalline silicon film layer in the embodiment of the invention 2;
Fig. 8 is the process sketch map that forms top gate type thin film transistor in the embodiment of the invention 2.
Wherein, 100-substrate, 101-resilient coating, 110-first metal film layer, 120-second metal film layer; 130-first photoresist, 210-gate electrode, 220-grid line, 230-second photoresist, 300-first insulating barrier; The 320-interlayer insulating film, 410-amorphous silicon membrane layer, 420-microcrystalline silicon film layer, 500-second insulating barrier, 510-diffusion impervious layer; 600-the 3rd metal film layer, 610-heat conduction layer, 700-ohmic contact layer, 800-the 4th metal film layer, 810-source electrode; The 820-drain electrode, 830-channel region, 910-passivation layer, 920-via hole, 930-pixel electrode.
Embodiment
Below in conjunction with accompanying drawing and embodiment, specific embodiments of the invention describes in further detail.Following examples are used to explain the present invention, but are not used for limiting scope of the present invention.
The present invention is based on the microcrystal silicon technology and carry out the backboard making of AMLCD and AMOLED,, improve the stability and the uniform particles property that form microcrystal silicon by the amorphous silicon crystallization to reduce the cost of backboard.
As first technical scheme of the present invention, the preparation method of said array base palte comprises:
Active layer in the said array base palte is the microcrystalline silicon film layer; The forming process of said microcrystalline silicon film layer is: on substrate, form amorphous silicon membrane layer and metal film layer continuously; Make the heat conduction layer that forms by said metal film layer through composition technology; Carry out laser crystallization technology then, make the amorphous silicon membrane layer under the said heat conduction layer become the microcrystalline silicon film layer, more said heat conduction layer is removed.
The preparation method of the array base palte that this scheme provided realizes crystallization through heat conduction layer to amorphous silicon with laser crystallization technology, and it is low to have a cost, the characteristics that stability is high, uniformity is high; The thin-film transistor that microcrystal silicon forms has characteristics such as high mobility, high stability.
As second technical scheme of the present invention; On the basis of first technical scheme; Said preparation method is specially: the forming process of said microcrystalline silicon film layer is designated as step 2, and said metal film layer is designated as the 3rd metal film layer, and said composition technology is designated as composition technology for the second time;
Also comprise step 1 before the said step 2: on substrate, form first metal film layer and second metal film layer continuously; Through the first time composition technology make the gate electrode that forms by said first metal film layer, and the grid line that overlaps to form by said first metal film layer and second metal film layer;
Also comprise in the step 2: on the substrate that step 1 forms, before forming said amorphous silicon membrane layer, form first insulating barrier, between said amorphous silicon membrane layer and the 3rd metal film layer, form second insulating barrier;
Also comprise step 3 after the said step 2: on the substrate that step 2 forms, make the diffusion impervious layer that is formed by said second insulating barrier through composition technology for the third time, said diffusion impervious layer is positioned at above the said microcrystalline silicon film layer;
Step 4: on the substrate that step 3 forms, make source electrode, drain electrode, passivation layer and pixel electrode successively.
As the 3rd technical scheme of the present invention, on the basis of above-mentioned arbitrary technical scheme, the present technique scheme increases new technical characterictic, and promptly said first metal film layer is a refractory metal; Said second metal film layer is a high conductivity metal.Make gate electrode with refractory metal, make grid line, make the LASER HEAT conducting shell with high melting point metal layer with high conductivity metal, and the selectivity crystallization, avoided the grid line metal to receive high-temperature damage.
As the 4th technical scheme of the present invention, on the basis of above-mentioned arbitrary technical scheme, the present technique scheme increases new technical characterictic, and said first insulating barrier, amorphous silicon membrane layer and second insulating barrier form through enhanced chemical vapor deposition; Said the 3rd metal film layer forms through sputtering method.。
As the 5th technical scheme of the present invention, on the basis of above-mentioned arbitrary technical scheme, the present technique scheme increases new technical characterictic, and said first insulating barrier is silicon nitride, silica or silicon oxynitride, and its thickness is 200nm ~ 400nm; Said second insulating barrier is silicon nitride, silica or silicon oxynitride, and its thickness is 50nm ~ 100nm; Said the 3rd metal film layer is molybdenum simple substance, titanium simple substance, molybdenum alloy or titanium alloy.With satisfy first insulating barrier as grid electrode insulating layer, second insulating barrier as diffusion impervious layer, the 3rd metal film layer needs as heat conduction layer.
As the 6th technical scheme of the present invention, on the basis of above-mentioned arbitrary technical scheme, the present technique scheme increases new technical characterictic, structures such as preparation source electrode, drain electrode and pixel electrode, and said step 4 specifically comprises:
Step 41: on the substrate that step 3 forms, form ohmic contact layer and the 4th metal film layer continuously,, form source electrode and drain electrode through the 4th composition technology; Use the intermediate tone mask plate in said the 4th the composition technology;
Step 42: on the substrate that step 41 forms, form passivation layer, through the 5th composition technology, the preparation via hole;
Step 43: on the substrate that step 42 forms, form five metals and belong to thin layer, through the 6th composition technology, form pixel electrode, said pixel electrode links to each other with source electrode or drain electrode through via hole.
As the 7th technical scheme of the present invention, on the basis of above-mentioned arbitrary technical scheme, the present technique scheme increases new technical characterictic, and said ohmic contact layer is N+ type doped amorphous silicon or P+ type doped amorphous silicon; Said the 4th metal film layer is molybdenum simple substance, titanium simple substance, molybdenum alloy or titanium alloy; Said passivation layer is a silicon nitride; It is indium tin oxide that said five metals belongs to thin layer.Select best material for use to different thin layers in this scheme, so that this thin layer is realized best effect.
As the 8th technical scheme of the present invention, on the basis of above-mentioned arbitrary technical scheme, the present technique scheme increases new technical characterictic, before the forming process of said microcrystalline silicon film layer, on substrate, is formed with resilient coating; After the forming process of said microcrystalline silicon film layer, form first insulating barrier, gate electrode, interlayer insulating film, source electrode, drain electrode, passivation layer and pixel electrode on the substrate successively.The manufacture method of the corresponding top gate type microcrystal silicon of this technical scheme array base palte.
As the 9th technical scheme of the present invention, on the basis of technique scheme, the present technique scheme increases new technical characterictic, and said resilient coating is the composite bed of silicon nitride individual layer, silica individual layer or silicon nitride and silica.Can improve the bonding strength between this resilient coating and the levels structure.
As the of the present invention ten technical scheme, on the basis of above-mentioned arbitrary technical scheme, the present technique scheme increases new technical characterictic, and said laser crystallization technology is the infrared laser crystallization.Compare with ELA, its cost is lower.
The present invention also provides the technical scheme of protection array base palte, and this technical scheme forms based in above-mentioned ten technical schemes any.
The present invention further provides the technical scheme of protection display device, and this technical scheme forms based on above-mentioned array base palte.Based on technique scheme, the present invention provides four preferred embodiments that such scheme is carried out detailed description, and the numbering of following examples is not represented quality.
Embodiment 1
The preparation method of the array base palte that present embodiment provided is based on that the structure of bottom gate thin film transistor proposes, and at first on substrate, deposits the double layer of metal film successively, by the first time intermediate tone mask form gate electrode and grid line; Be right after and deposit gate insulation layer, semiconductor layer (amorphous silicon), diffusion impervious layer, heat conduction layer successively, through forming directional heat conducting shell figure behind the mask for the second time; Pass through the infrared laser light irradiation then, to the amorphous silicon semiconductor layer annealing in process, make amorphous silicon be transformed into microcrystal silicon, and then remove heat conduction layer through heat conduction layer; Then, the deposition diffusion impervious layer through the diffusion barrier of mask formation for the third time layer pattern, and deposits ohmic contact layer and metallic film on it, carries out mask then the 4th time, in same photoetching process, forms source electrode and drain electrode with the intermediate tone mask plate; Next, deposit passivation layer on substrate is carried out mask then the 5th time, forms sectional hole patterns; At last, depositing metal films layer on substrate through the 6th mask, forms pixel electrode pattern, and said pixel electrode links to each other with source electrode or drain electrode through via hole.Arrive this, accomplish based on the backboard manufacturing of microcrystalline silicon thin film transistor.
Composition technology alleged in the present embodiment comprises technologies such as photoetching, coating, mask, exposure, etching, belongs to prior art, does not do detailed description.Said " deposition " just forms a kind of mode of each rete on substrate, can also comprise sputter, coating etc., not with this as qualification.
Fig. 1 to Fig. 6 shows the technological process for preparing in the present embodiment based on the microcrystalline silicon thin film transistor array base palte, specifically may further comprise the steps:
Step 1: substrate 100 is carried out clean; Utilize sputtering method successive sedimentation first metal film layer (lower floor) 110 and second metal film layer (upper strata) 120 on substrate 100; Through the first time composition technology form the gate electrode 210 that forms by first metal film layer 110, and the grid line 220 that overlaps to form by first metal film layer 110 and second metal film layer 120.
Fig. 1 shows the complete process of step 1; Wherein, Substrate 100 is glass, metal or plastic base, and first metal film layer 110 is a refractory metal, like molybdenum simple substance, titanium simple substance, molybdenum alloy or titanium alloy etc.; Second metal film layer 120 is a high conductivity metal, like copper simple substance, aluminium simple substance, copper alloy or aluminium alloy etc.In gate electrode 210 and grid line 220 forming processes; (said coating just forms a kind of mode of photoresist to applying to use the intermediate tone mask plate; Can also be other modes) first photoresist 130 on second metal film layer 120 double exposes, and forms the gate electrode of being processed by double layer of metal 210 and grid line 220 respectively after the etching.
Step 2: on the substrate of completing steps 1 with enhanced chemical vapor deposition (PECVD) method; Successive sedimentation first insulating barrier 300, amorphous silicon membrane layer 410 and second insulating barrier 500 form the 3rd metal film layer 600 with sputtering method on second insulating barrier 500.First insulating barrier, 300 materials are silicon nitride (SiNx), silica (SiO
2) or silicon oxynitride (SiNxOy), thickness is between 200nm ~ 400nm, as the grid electrode insulating layer; Second insulating barrier, 500 materials are silicon nitride (SiNx), silica (SiO
2) or silicon oxynitride (SiNxOy); Thickness is between 50nm ~ 100nm; As diffusion impervious layer, can stop the 3rd metal film layer 600 and amorphous silicon membrane layer 410 mutual scattering and permeating, can also protect amorphous silicon membrane layer 410 to avoid the damage of postorder etching technics; The 3rd metal film layer 600 materials are metals such as molybdenum simple substance, titanium simple substance, molybdenum alloy or titanium alloy.
Fig. 2 illustrates the complete process of step 2, through the second time composition technology form the pattern of the 3rd metal film layer 600, absorption and conducting shell as the infrared laser heat are called heat conduction layer 610; And then carry out laser crystallization technology, promptly with the infrared laser lamp substrate is scanned, the laser heat is absorbed by heat conduction layer 610 and conducts to amorphous silicon membrane layer 410, makes amorphous silicon membrane layer 410 change microcrystalline silicon film layer 420 into.In the laser crystallization process, the metal ion that second insulating barrier 500 plays a part in the barrier metal layer 600 gets into microcrystal silicon layer 420.Gate electrode 210 is made up of refractory metal, in crystallization process, can not melt, and grid line 220 tops do not have heat conduction layer 610, below heat can not be transmitted to, so grid line 220 can not be affected yet.Remove heat conduction layer 610 through wet-etching technique at last, accomplish laser crystallization technology.
Step 3: on the substrate that step 2 forms, form the pattern of second insulating barrier 500 through composition technology for the third time, as diffusion impervious layer 510, diffusion impervious layer 510 is positioned at microcrystalline silicon film layer 420 top; Then aforesaid substrate is carried out surface treatment, deposition ohmic contact layer 700 and the 4th metal film layer 800 on aforesaid substrate afterwards with soup (like hydrofluoric acid etc.).
Fig. 3 illustrates the complete process of step 3, and wherein, ohmic contact layer 700 promptly is a doping semiconductor layer, for N+ type doped amorphous silicon or P+ type doped amorphous silicon, in process for making, adds PH
3Gas or B
2H
6Gas is to realize the doping purpose; The 4th metal film layer 800 materials are metals such as molybdenum, aluminium, neodymium.
Step 4: on the substrate that step 3 forms,, form source electrode 810 and drain electrode 820 through the 4th composition technology.
Fig. 4 illustrates the complete process of step 4, wherein, uses the intermediate tone mask plate that second photoresist 230 that is coated on the 4th metal film layer 800 is double exposed, and forms source electrode 810, drain electrode 820 and channel region 830 between the two respectively.
Step 5: on the substrate that step 4 forms,,, form via hole 920 then through the 5th composition technology with PECVD method deposit passivation layer 910.As shown in Figure 5, the sketch map of expression completing steps 5.Wherein, passivation layer 910 materials are silicon nitride, and thickness is between 150nm ~ 250nm.
Step 6: on the substrate that step 5 forms, deposit five metals with sputtering method and belong to thin layer, then through the 6th composition technology, form pixel electrode 930, said pixel electrode 930 electrically connects through via hole 920 and source electrode 810 or drain electrode 820.As shown in Figure 6, the sketch map of expression completing steps 6.Wherein, to belong to thin layer be indium tin oxide high conductivity, high permeability metal oxides such as (ITO) to said five metals.
Above-mentioned steps 1-6 shows the main preparation technology based on the array base palte of microcrystalline silicon thin film transistor, and this preparation technology uses mask plate six times, generally needs the above processing procedure of 7MASK (mask plate) compared to the manufacturing of LTPS backboard; Present embodiment preparation technology cost is lower; And the LTPS manufacturing cost is quite high, and laser module is expensive, and microcrystal silicon TFT and existing amorphous silicon technology are compatible easily; Can directly utilize the technology and the equipment of existing amorphous silicon, reduce cost greatly; Tradition amorphous silicon mobility is low, is not suitable for making the AMOLED backboard, and microcrystal silicon TFT has higher mobility, can be used to make the AMOLED backboard; Low temperature polycrystalline silicon TFT lack of homogeneity, microcrystal silicon TFT has characteristics such as high mobility, high stability.
In the present embodiment, laser crystallization technology realizes crystallization through heat conduction layer to amorphous silicon, and it is low to have a cost, the characteristics that stability is high, uniformity is high; Laser crystallization technology not only can be used the infrared laser crystallization process, also can use the PRK crystallization process.And, make gate electrode with refractory metal, make grid line with high conductivity metal, make the LASER HEAT conducting shell with high melting point metal layer, and the selectivity crystallization, avoided the grid line metal to receive high-temperature damage.
Embodiment 2
The preparation method of the array base palte that present embodiment provided; Be based on that the structure of top gate type thin film transistor proposes; Fig. 7 and Fig. 8 show the preparation process of thin-film transistor in the present embodiment; Particularly, deposition resilient coating 101 on substrate 100, resilient coating 101 is formed by silicon nitride individual layer, silica individual layer or both composite beds; And then the deposition of amorphous silicon films layer 410, and according on amorphous silicon membrane layer 410, forming heat conduction layer 610 with embodiment 1 identical technology, through obtaining microcrystalline silicon film layer 420 after the infrared laser crystallization, as shown in Figure 7; Get into post-order process then, form first insulating barrier 300 successively as the grid electrode insulating layer, gate electrode 210, interlayer insulating film 320, source electrode 810, drain electrode 820 and passivation layer 910, as shown in Figure 8.
The structure that function is identical in the present embodiment can adopt and identical materials described in the embodiment 1, and the preparation technology of other structure and embodiment 1 or preparation technology of the prior art are similar, do not give unnecessary details at this.
Can be found out that by above embodiment the embodiment of the invention realizes crystallization through heat conduction layer to amorphous silicon through adopting laser crystallization technology, it is low to have a cost, the characteristics that stability is high, uniformity is high; The thin-film transistor that microcrystal silicon forms has characteristics such as high mobility, high stability; Wherein, make gate electrode, make grid line, make the LASER HEAT conducting shell with high melting point metal layer with high conductivity metal with refractory metal, and the selectivity crystallization, avoided the grid line metal to receive high-temperature damage.
Embodiment 3
The embodiment of the invention also includes the array base palte that the preparation method of above-mentioned arbitrary embodiment makes; The microcrystalline silicon film layer of said array base palte is realized crystallization through heat conduction layer to amorphous silicon through adopting laser crystallization technology; It is low to have cost, the characteristics that stability is high, uniformity is high; The thin-film transistor that microcrystal silicon forms has characteristics such as high mobility, high stability; Wherein, make gate electrode, make grid line, make the LASER HEAT conducting shell with high melting point metal layer with high conductivity metal with refractory metal, and the selectivity crystallization, avoided the grid line metal to receive high-temperature damage.
Embodiment 4
The embodiment of the invention also comprises a kind of display device, and it comprises above-mentioned array base palte, and display device can be liquid crystal panel, LCD TV, LCD, Electronic Paper, DPF, Electronic Paper, AMOLED display etc.The microcrystalline silicon film layer of the said array base palte that comprises in the said display device is realized crystallization through heat conduction layer to amorphous silicon through adopting laser crystallization technology, and it is low to have a cost, the characteristics that stability is high, uniformity is high; The thin-film transistor that microcrystal silicon forms has characteristics such as high mobility, high stability; Wherein, make gate electrode, make grid line, make the LASER HEAT conducting shell with high melting point metal layer with high conductivity metal with refractory metal, and the selectivity crystallization, avoided the grid line metal to receive high-temperature damage.
The above only is a preferred implementation of the present invention; Should be pointed out that for those skilled in the art, under the prerequisite that does not break away from know-why of the present invention; Can also make some improvement and replacement, these improvement and replacement also should be regarded as protection scope of the present invention.
Claims (12)
1. the preparation method of an array base palte; It is characterized in that the active layer in the said array base palte is the microcrystalline silicon film layer, the forming process of said microcrystalline silicon film layer is: on substrate, form amorphous silicon membrane layer and metal film layer continuously; Make the heat conduction layer that forms by said metal film layer through composition technology; Carry out laser crystallization technology then, make the amorphous silicon membrane layer under the said heat conduction layer become the microcrystalline silicon film layer, more said heat conduction layer is removed.
2. the preparation method of array base palte as claimed in claim 1 is characterized in that, the forming process of said microcrystalline silicon film layer is designated as step 2, and said metal film layer is designated as the 3rd metal film layer, and said composition technology is designated as composition technology for the second time;
Also comprise step 1 before the said step 2: on substrate, form first metal film layer and second metal film layer continuously; Through the first time composition technology make the gate electrode that forms by said first metal film layer, and the grid line that overlaps to form by said first metal film layer and second metal film layer;
Also comprise in the step 2: on the substrate that step 1 forms, before forming said amorphous silicon membrane layer, form first insulating barrier, between said amorphous silicon membrane layer and the 3rd metal film layer, form second insulating barrier;
Also comprise step 3 after the said step 2: on the substrate that step 2 forms, make the diffusion impervious layer that is formed by said second insulating barrier through composition technology for the third time, said diffusion impervious layer is positioned at above the said microcrystalline silicon film layer;
Step 4: on the substrate that step 3 forms, make source electrode, drain electrode, passivation layer and pixel electrode successively.
3. the preparation method of array base palte as claimed in claim 2 is characterized in that, said first metal film layer is a refractory metal; Said second metal film layer is a high conductivity metal.
4. the preparation method of array base palte as claimed in claim 2 is characterized in that, said first insulating barrier, amorphous silicon membrane layer and second insulating barrier form through enhanced chemical vapor deposition; Said the 3rd metal film layer forms through sputtering method.
5. the preparation method of array base palte as claimed in claim 4 is characterized in that, said first insulating barrier is silicon nitride, silica or silicon oxynitride, and its thickness is 200nm ~ 400nm; Said second insulating barrier is silicon nitride, silica or silicon oxynitride, and its thickness is 50nm ~ 100nm; Said the 3rd metal film layer is molybdenum simple substance, titanium simple substance, molybdenum alloy or titanium alloy.
6. the preparation method of array base palte as claimed in claim 2 is characterized in that, said step 4 specifically comprises:
Step 41: on the substrate that step 3 forms, form ohmic contact layer and the 4th metal film layer continuously,, form source electrode and drain electrode through the 4th composition technology; Use the intermediate tone mask plate in said the 4th the composition technology;
Step 42: on the substrate that step 41 forms, form passivation layer, through the 5th composition technology, the preparation via hole;
Step 43: on the substrate that step 42 forms, form five metals and belong to thin layer, through the 6th composition technology, form pixel electrode, said pixel electrode links to each other with source electrode or drain electrode through via hole.
7. the preparation method of array base palte as claimed in claim 6 is characterized in that, said ohmic contact layer is N+ type doped amorphous silicon or P+ type doped amorphous silicon; Said the 4th metal film layer is molybdenum simple substance, titanium simple substance, molybdenum alloy or titanium alloy; Said passivation layer is a silicon nitride; It is indium tin oxide that said five metals belongs to thin layer.
8. the preparation method of array base palte as claimed in claim 1 is characterized in that, before the forming process of said microcrystalline silicon film layer, on substrate, is formed with resilient coating; After the forming process of said microcrystalline silicon film layer, form first insulating barrier, gate electrode, interlayer insulating film, source electrode, drain electrode, passivation layer and pixel electrode on the substrate successively.
9. the preparation method of array base palte as claimed in claim 8 is characterized in that, said resilient coating is the composite bed of silicon nitride individual layer, silica individual layer or silicon nitride and silica.
10. the preparation method of array base palte as claimed in claim 1 is characterized in that, said laser crystallization technology is the infrared laser crystallization.
11. an array base palte is characterized in that, said array base palte makes through the arbitrary described preparation method of claim 1-10.
12. a display device is characterized in that, said display device comprises the described array base palte of claim 11.
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| CN107910242A (en) * | 2017-01-17 | 2018-04-13 | 南京新创力光电科技有限公司 | A kind of method that infrared laser prepares polysilicon membrane |
| CN108878445A (en) * | 2018-06-11 | 2018-11-23 | 深圳市华星光电技术有限公司 | TFT substrate and preparation method thereof |
| CN112736087A (en) * | 2019-10-10 | 2021-04-30 | 京东方科技集团股份有限公司 | Manufacturing method of array substrate, array substrate and display panel |
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| CN115810637A (en) * | 2022-12-27 | 2023-03-17 | Tcl华星光电技术有限公司 | Array substrate, manufacturing method thereof and display panel |
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| CN115911059B (en) * | 2022-12-29 | 2025-06-27 | Tcl华星光电技术有限公司 | Array substrate and preparation method thereof |
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Application publication date: 20121219 |