TWI236324B - Insulating structure of circuit board and method for fabricating the circuit board by using the insulating structure - Google Patents

Abstract

An insulating structure of circuit board and method for fabricating the circuit board by using the insulating structure are proposed. The insulating structure is formed with a fully cured layer and two partially cured layer formed on both surfaces of the fully cured layer, wherein the partially cured layers are preferably thinner than the fully cured layer so as to minimize the shrinkage of the insulating structure in subsequent processes and maintain the accuracy of alignment for the subsequent processes. Meanwhile, the insulating structure can serve as a core substrate.

Description

1236324 V. Description of the invention (1) '' ------- [Technical field to which the invention belongs] The present invention relates to the structure and use of an insulating layer of an insulating circuit board. r 土 a 社 十 Ί "The method of forming a circuit board by using a rim layer.

L 先 刖 技术 J Pursue in the global electronics industry Mounting and printed circuit board technology has become an inevitable trend. To meet half

Integration) and miniaturization (Μ ··, Ishibei City, 4, Tan Wish Private +, Shi Mlniaturizat ion) packaging requirements, providing most active and passive components and ticks. The circuit board (C i rcu itb〇ard) connected by dry and spring roads has also gradually been cleaned by double-layer boards, Dian Xi ', Multi-layerboard, and in a limited space, hereby Aa ^ By interlayer connection technology (Inte Γ 1 ayer connect ion) to expand the circuit ^ circuit board available circuit area, to meet the high electron density integrated circuit (Integrated circuit) requirements. Taking the circuit board manufacturing process as an example, the manufacturing method of a multilayer circuit board is roughly two methods: laminating press and BuUd-up. As shown in Figures 1A to 1C, it is a schematic diagram showing a conventional process for manufacturing a multilayer circuit board by a press bonding method, such as U.S. Patent No. 4,526 8] 5 Yu Su and No. 5,806 ^ 77. To apply this method. -First, prepare a plurality of pen boards 11, 12, 13 'made of copper and insulating substrates, for example. The circuit board unit 11 is formed with upper and lower wiring layers 1 1 a, 1 1 b, and The conductive vias 1 1 c, and the circuit board units 丄 2, 丨 3 are respectively formed with circuit layers 1 2 a, 1 3 a on one side, and the circuit board units i 2 1 3 are opposite to the circuit layer 1 2 a, 1 3 a are also formed with conductive metal on the other side

17663 All®. Ptd Page 5 1236324 V. Description of the Invention (2) Layers 1 2 c, 1 3 c. As shown in Figure 1A, an insulation made of fiber or thermosetting resin (such as epoxy resin, phenol polyester, etc.) is sandwiched between the circuit board units 1 1, 12, 2, and 13 respectively. The layer 14 serves as an adhesive layer for the circuit board units 11, 12, and 13 to be superposed and adhered to each other. Here, the resin polymerization reaction commonly used in the industry is taken as an example. The initial state of the resin that has not been polymerized from the manufacturer is commonly referred to as A-stage. When the polymerization reaction has started but has not yet reached curing, it is called Cure. B-stage or incomplete polymerization stage, as shown in Fig. 1A, the insulation layer 1 to 4 that has not been cured (Cure) is incomplete in B-stage Polymer material layer. As shown in FIG. 1B, the intersecting and overlapping circuit board units 11, 12, 13 are laminated to form a multilayer bonding board through the steps of laminating and heat pressing. At this time, the heat-pressed insulation layer 14 has been fully polymerized (C-stage), and a plurality of through-holes can be drilled using drilling technology (Dn 1 1 1 ng). 15 and plate a conductive metal layer (such as element symbols 1 2 c, 1 3 c) on the surface of the through-hole 15 hole wall 〇. As shown in FIG. 1C, the outermost conductive metal layer 12c On 13c, circuit patterning (P a 11 erning) is performed to make circuit layers 1 2 b, 1 3 b, and each circuit board unit 1 1, 1 2, 1 3 can be electrically connected through a through hole 15, and A multilayer circuit board 10 having six wiring layers is produced. However, since the pressing process is performed at a high temperature, and the insulating layer 14 is baked and cured during processing, it will be difficult to control because the insulating layer 14 shrinks.

17663 Quan 懋 .ptd Page 6 1236324 V. Description of the invention (3) The precise dimensions of the circuit board 10 will not only cause problems of stress and warpage during the lamination process, but also make subsequent processes fail to run smoothly, making product production difficult. 0 At the same time, due to the shrinkage of the insulating layer 14, in subsequent processes (such as exposure), problems such as hole deviation will occur in the inner layer circuits, which will affect the alignment accuracy, and the more the outer layer, the more difficult it is to perform the process such as exposure . In addition, multi-layer circuit boards manufactured by compression bonding require thicker insulating layers, which makes the overall thickness of the device thicker. In addition to not being conducive to the pursuit of light, thin and short development trends, it is thicker and is not baked and cured (N ο η-cure) of the insulating layer 14 will cause the shrinkage in the subsequent process to become more serious. As shown in Figs. 2A to 2E, they are process schematic diagrams of a method for making a multilayer board by a Bui Id-up method, such as US Patent Nos. 6, 3 2 3, 4 3 5 and 6, 4 Case No. 28, 9 4 2 is the application of this method. As shown in FIG. 2A, first, a core substrate 21 is prepared. The core substrate 21 is composed of a resin core layer 2 1 1 having a predetermined thickness and a copper foil pattern formed on the surface of the core layer 2 1 1 2 1 2 constitutes. At the same time, a plurality of conductive vias 2 1 3 are formed in the resin core layer 2 1 1, thereby electrically connecting the copper foil patterns 2 1 2 on the surface of the resin core layer 2 1 1. As shown in FIG. 2B, the core substrate 2 L is subjected to a build-up process, β is provided with a dielectric layer 22 on the surface of the core substrate 21, and a plurality of copper layers are connected to the dielectric layer 22 to communicate with the copper. Blind hole 23 of foil pattern 2 1 2 As shown in FIG. 2C, a metal conductive film is formed on the exposed surface of the dielectric layer 2 (including the hole wall of the blind hole 23) by electroless plating or sputtering. 24, and a patterned plating resist layer 25 is formed on the metal conductive film 24, so that

17663 Quan.ptd Page 7 1236324 V. Description of the invention (4) The plating resist layer 25 is formed with a large number of openings 2 5 0 and a part of the conductive film where a patterned circuit layer is to be formed is exposed. As shown in FIG. 2D, a patterned circuit layer 2 6 is formed in the opening 2 5 0 of the plating resist layer 25 by electroplating, and the circuit layer 2 6 can be electrically connected through the blind hole 2 3 To the copper foil pattern 2 1 2, and then etching to remove the plating resist layer 2 5 and a part of the conductive film 24 covered thereon, so as to form a layered structure 20a ° as shown in FIG. 2E. Similarly, On the outermost surface of the first build-up structure 20 a, a second build-up structure 20 b must be repeatedly formed using the same method to gradually build up a layer of a multilayer circuit board 20. Among them, the dielectric layer materials selected in this layer-adding process are generally classified into fiber-impregnated resin materials and non-fiber resin-type materials. The fiber-impregnated resin material may be, for example, bismaleimide / triamine (BT, Bisaleimide triazine) plus glass fiber or mixed epoxy resin and glass fiber (FR 4), etc., instead of a resin type material of fiber It can be, for example, ABF (Ajinmo to buildup film) manufactured by Ajinomoto Co., Ltd., in which the ABF is soft and needs to be carried on a film (Carrier 1 ayer). ^ However, non-fiber resin-based materials cannot support the subsequent build-up structure because they cannot be as reliable as fiber-impregnated resin materials. Moreover, regardless of the fiber-impregnated resin material and the non-fiber resin-based material, the structure of the layer-adding process in the subsequent processing still has the problem of shrinkage and alignment caused by the dielectric layer composed of pre-cured or uncured material. Therefore, improperly selected insulation or dielectric material / structure will cause shrinkage and alignment problems

17663 全懋 .ptd Page 8 1236324 V. Description of the invention (5) The whole becomes obsolete. Therefore, the problem of the edge layer or the dielectric layer to solve the problem is reduced. [Content of the invention] In view of the above products, The loss is very much the problem mentioned above. The material / structure has a low yield rate, and those who have produced the problem have already realized what they have learned. Provide a structure that can reduce the shrinkage rate of the insulating layer to form a circuit board. In order to achieve the structure and use of the main polymer materials have been completed, the connected or fully polymerized circuit, including the material layer, should be fully polymerized. Coarse and semi-constructed materials are laminated on one of the layers to form a thinner layer. Polymerized materials are used to create multiple circuits and use the exposed and fully insulated surfaces of the materials to sandwich the material layer. The optional process is a method of minimizing the known technology of the circuit board unit in between. The system provides the insulating layer for other purposes, the layer forms the layer of the electrically-conductive material, fully polymerized, fully polymerized, the layer structure is placed on these, and the option will strengthen the combined force. The board is tied to such serious. How to avoid the shrinkage risks caused by conventional techniques, such as the shrinkage risk caused by alignment, and the alignment tolerance and exposure latitude (a problem to be explored before Latitude. Disadvantages, the main purpose of the present invention is the structure of the circuit board insulation layer and the use of a method to maintain alignment The accurate circuit forms the circuit board of the present invention and the two material layers. The material layer can form a method of exposing incompletely incompletely aggregated road boards, respectively, and the latter is more suitable than the polymer materials such as polymer materials. Material and material manufacturing method. Insulation of the circuit is formed in these incomplete. The surface layer of the layer of the winding material layer and the structure of the insulation layer of the board have been completely polymerized, and the end is opened to perform activities such as unfinished. : Providing a patterned circuit board unit

17663 Quan 懋 .ptd Page 9 1236324 V. Description of the invention (6) The insulating layer structure is used as the insulating layer; the laminated circuit board units are laminated into a multi-layer bonded board through lamination and hot pressing steps; A plurality of through-holes are set, and a conductive metal layer is plated on the surfaces of the walls of the through-holes to perform steps such as circuit patterning on the outermost conductive metal layer. The through-holes are electrically connected to obtain a multilayer circuit board. The obtained multilayer circuit board includes a plurality of circuit board units, and each of the circuit board units is separated by the aforementioned insulation layer structure. The insulation layer structure is to fill the circuit layer of each circuit board unit with its incomplete polymer material layer. Gaps, and the fully polymerized material layer and each circuit board unit are separated by the incompletely polymerized material layers. In other embodiments, the multilayer circuit board may optionally include a core substrate. The core substrate is a pre-processed double-layer or multi-layer circuit board, so that a layer of a multi-layer circuit board is gradually formed on the surface of the core substrate. And the core substrate is formed with the aforementioned insulation layer structure, wherein the insulation layer structure fills the circuit layer gap between the layered structures with its incompletely polymerized material layer, and the completely polymerized material layer and the core substrate The build-up structure is separated by these layers of incomplete polymer material. Wherein, the core substrate can also be made by applying the aforementioned insulating layer structure. -The circuit board insulation layer structure of the present invention can be applied to the manufacture of single-layer, double-layer, or multi-layer circuit boards and core substrates, and can be optionally applied to circuit boards by pressing, layering, and other appropriate methods. The former is manufactured to minimize the shrinkage of the insulating layer structure in the subsequent processes, and to maintain the alignment of the subsequent processes.

17663 Quan 懋 .ptd Page 10 1236324 V. Explanation of the invention (7) In this way, the circuit board insulation layer structure of the present invention and the method for forming the circuit board by using the insulation layer can effectively avoid the insulation layer or the dielectric of the conventional technology The lack of electrical layer materials / structures due to shrinkage and alignment problems can further improve process yield, productivity and exposure latitude. The following is a description of specific embodiments of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied by other different specific embodiments, and various details in this specification can also be modified and changed based on different viewpoints and applications without departing from the spirit of the present invention. [Embodiments] The following examples are intended to further illustrate the viewpoints of the present invention in detail, but do not limit the scope of the present invention in any way. Figures 3 to 5C are drawings according to a preferred embodiment of the present invention. As shown in the figure, the insulation layer structure 3 of the present invention is applied to the manufacture of circuit boards, and mainly includes a fully polymerized material layer 31 and two incompletely polymerized layers formed on the upper and lower surfaces of the fully polymerized material layer 31 respectively. Material layers 33, 35. It should be noted here that the insulation layer structure 3 can be applied to the manufacture of single-layer, double-layer and multi-layer circuit boards, and can be applied by pressing, layer-adding method and other appropriate methods. For the manufacture of the circuit board, this embodiment only exemplifies one of the implementation manners, but the present invention is not limited thereto, and will be described together. As shown in Figures 3 and 4, the fully polymerized material layer 31 is finished.

17663 Quan 懋 .ptd Page 1.1 1236324 V. Description of the invention (8) Fully polymerized materials, and can be, for example, epoxy resin (Epoxy resin), phenol polyester, polyethylamine (Polyinide) , Cyanate ester, glass fiber, bismaleimide / imide / triazine (βτ, B is ma 1 eimi de triazi ne) or mixed epoxy resin and glass fiber material. Among them, the fully polymerized material layer 31 can also be made of fiber-reinforced (F i ber-r e n f oc r d) or particle-reinforced composite materials to increase strength. In addition, the fully polymerized material layer 31 can be selected on the surface by plasma plasma, reactive ion etching (RIE), ion metal plasma (IMP) processes, etc. An activation or roughening process is performed to make the surface of the fully polymerized material layer 3 1 produce a chemical bond (C hemica 1 b ο nd) or present a rough structure, so as to strengthen the fully polymerized material layer 3 1 and The bonding force between these 3, 3, 5 layers of incompletely polymerized material. The incompletely polymerized material layers 3 3, 3 5 are composed of incompletely polymerized materials, for example, those in a semi-cured colloidal state. The incompletely polymerized material layers 3 3, 3 5 may also be, for example, epoxy resin, phenol polyester, polyimide, cyanate ester, glass fiber, and dicis-butene. Bismaleimide triazine (BT) or organic material composed of epoxy resin and glass fiber. However, it should be noted that the constituent materials of the incompletely polymerized material layers 3 3, 3 5 and the fully polymerized material layer 31 are not limited to the same; in other words, the incompletely polymerized material layers 3 3, 3 5 and the fully polymerized material layer 3 1 may be selected from the same or different materials. Of which these are not fully assembled

17663 Quan 懋 .ptd Page 12 1236324 V. Description of the invention (9) The material layer 3 3, 3 5 is thinner than the fully polymerized material layer 3 As shown in Figure 3, when the structure of the insulating layer is to be formed At 3 o'clock, the fully polymerized material layer 31 can be sandwiched between the incompletely polymerized material layers 3 3 and 35, for example. One end of the fully polymerized material layers 3 3 and 3 5 starts to be bonded, and an insulation layer structure 3 as shown in FIG. 4 is obtained. Generally speaking, the insulation layer structure 3 can be selected, for example, in a rolled state, and it can be used only by tearing off the tape during use. Wherein, the bonding method and the use method of the insulating layer structure 3 are not limited to those described in this embodiment, but may have other changes and modifications. Since the insulating layer structure 3 is applied to a manufacturer who completes a circuit board by pressing, for example, the insulating layer structure 3 is formed first. However, it should be noted that, in other embodiments, the insulating layer structure 3 can also be applied to, for example, layering or other processes suitable for forming a circuit board unit or a core substrate, but not limited thereto. Meanwhile, as shown in FIG. 3, the insulating layer structure 3 may optionally be formed with an upper film 37 and / or a lower film 39 at its outermost layer. For example, the upper film 37 may be formed on the upper surface of the incomplete polymer material layer 33, and the lower film 39 may be formed on the lower surface of the incomplete polymer material layer 35, and The upper film 37 and / or the lower film 3 9 may be one of a metal layer, a protective layer, or a carrier layer, respectively. When the upper-layer film 37 and / or the lower-layer film 39 are metal layers, they may be, for example, copper foil. When the upper-layer film 37 and / or the lower-layer film 39 are used as the protective layer, they are used as insulation for winding the insulating layer structure 3.

17663 Quan 懋 .ptd Page 13 1236324 V. Description of the invention (10) Do not stick to other adhesive films. When the upper film 37 and / or the lower film 39 is a carrier layer, it can be, for example, a peelable organic film, such as a polypropylene (PP) film or a polyethylene terephthalate (polyester), PET. )film. In this embodiment, the upper film 37 is selected by using a metal layer or a carrier layer as an example, and the lower film 37 is selected by using a protective layer as an example, but is not limited thereto. For example, The upper film 37 can be selected as a protective layer or other appropriate film layer, and the lower film 39 can be selected as a metal layer, a supporting layer, or other appropriate film layer. 5A to 5C will illustrate the application of the preferred embodiment of the insulating layer structure 3 in the present invention in detail. It should be noted here that these drawings are simplified schematic diagrams, which only illustrate the basic structure of the present invention in a schematic manner, so they only show the components related to the present invention, and the circuit board units and other displayed The structure is not drawn according to the shape and size ratio during actual implementation. The shape and size ratio during actual implementation is an optional design, and its composition layout may be more complicated. Please refer to FIG. 5A. First, three circuit board units 5, 6, 7 made of, for example, copper foil and an insulating substrate are provided. A circuit layer 51 is formed on each of the circuit board units 5, 6, and 7. Γ 61, 63, 71 and conductive metal layers 5 3, 7 3, and the insulating layer structure 3 is arranged between each of the circuit board early elements 5, 6 and each of the circuit board early elements 6, 7 as an adhesive layer (A dhesive 1 ayer) for the circuit board units 5, 6, 7 to be superimposed on each other and used as insulation. In this embodiment, the circuit board units 5, 6, and 7 are selected as an example for constructing a multi-layer (six-layer) circuit board, but are not limited thereto. For example,

17663 Quan.ptd Page 14 1236324 V. Description of the invention (11) It can also be a single-layer or double-layer circuit board, or a core substrate that has been pre-processed. Among them, the pre-processing process of these circuit board units 5, 6, 7 / core substrates is a well-known technology in the industry, and it is not a technical feature of this case, so it will not be repeated. As shown in Fig. 5B, the circuit board units 5, 6, and 7 which are alternately stacked are laminated into a multilayer bonded board through the lamination and hot pressing steps. At this time, the heat-pressed insulating layer structure 3 is completely polymerized, and the whole is in a C-stage state. Among them, the manufacturing process of the lamination and hot-pressing steps is a conventional technology, so it will not be described in detail here. Because the insulation layer structure 3 includes a fully polymerized material layer 3 1 sandwiched between the incompletely polymerized material layers 3 3, 3 5 and an incompletely polymerized material layer 3 3, 3 5, and the thickness of the fully polymerized material layer 31 is much thicker than the incompletely polymerized material layers 3 3, 35. In the hot pressing step, the fully polymerized material layer 31 does not shrink, and the Due to the thinner thickness of the incompletely polymerized material layers 3, 3, 5, the shrinkage that can be generated is also limited. Therefore, the application of the insulating layer structure of the present invention has no risk of too low process yield and shrinkage due to shrinkage. At the same time, these are not completely bonded to each of the circuit board units 5, 6, and 7. The polymer material layers 3 3, 3 5 can be used to control these incomplete polymer material layers 3 3, The thickness of 3 5 is to fill the gaps of the circuit layers 5 1, 6 1, 7 1 of the circuit board units 5, 6, 7 with the incompletely polymerized material layers 3 3, 3 5. As shown in the dashed circle in FIG. 5B, the insulation layer structure 3 sandwiched between the circuit board unit 5 and the circuit board unit 6 is filled with the incomplete polymer material layer 3 3, 3 5 The circuit layer 5 of the unit 5, 6 has a gap of 1, 6 1 and the

17663 全懋 .ptd Page 15 1236324 V. Description of the invention (12) The fully polymerized material layer 3 1 and each of the circuit board units 5, 6, 7 are separated by the incompletely polymerized material layer 3 3, 3 5 open. Referring to FIG. 5C, a plurality of through-holes 9 are drilled by using a drilling technique, and a conductive metal layer (not shown) is plated on the surface of the through-holes 9 hole wall to conduct electricity in the outermost layer. Line patterning is performed on the metal layer, and each of the circuit board units 5, 6, and 7 is electrically connected through the through-holes 9, so that a multi-layer circuit board with six circuit layers 3 is produced. . In this embodiment, the application of the insulating layer structure 3 of the present invention to the process of manufacturing a circuit board is described in a press-fit manner, but it should be noted that the insulating layer structure 3 can also be applied to the build-up process. For example, a core substrate can be prepared first. The core substrate is a pre-processed double-layer or multilayer circuit board. The insulating layer structure 3 of the present invention is formed on the surface of the core substrate as a dielectric layer. After a series of processes, Layers are gradually added to form a multilayer circuit board. In other words, the application of the insulation layer structure 3 of the present invention to the circuit board manufacturing process is not limited to the lamination method, but can be applied to the build-up process or other appropriate processes. In addition, the insulation layer structure fills the circuit layer gaps between the circuit board units / layer structures with its incompletely polymerized material layer, and the fully polymerized material layer and each of the circuit board unit / core substrate The circuit board unit / additional structure is separated by these layers of incomplete polymer material. In the conventional technology, the insulating layer or the dielectric layer is usually a thicker film repair layer, and the film layer made of pre-cured or uncured material causes the overall thickness of the device to become thicker and causes shrinkage. . In the present invention, an insulating layer structure 3 including a thin layer of incompletely polymerized material 3, 3, 5 and a layer of completely polymerized material 3 1 can be formed, so that the shrinkage rate can be minimized, 俾

17663 Quan 懋 .ptd Page 16 1236324 V. Description of the Invention (13) Solving the shortcomings of conventional technology. At the same time, because the fully polymerized material layer 31 is a fully polymerized film layer without shrinking, and because the thickness of the incompletely polymerized material layers 33 and 35 is thin, the shrinkage rate can be minimized. The insulating layer structure 3 does not have the shrinkage problem of the conventional technology. Therefore, in the subsequent process (for example, exposure), there is no problem such as hole deviation in the inner layer circuit. Therefore, the accuracy of the alignment can be maintained by applying the insulating layer structure of the present invention, and there is no problem that it is more difficult to perform an exposure process such as an outer layer portion. In addition, the insulating layer structure of the present invention can be used as an insulating layer portion of a core substrate, so that the thickness of the core substrate can be reduced without a problem of shrinkage, thereby reducing the overall thickness of the device. Therefore, the present invention mainly consists of a fully polymerized material layer and two incompletely polymerized material layers formed on the upper and lower surfaces of the fully polymerized material layer, respectively, to form an insulating layer structure, and the insulating layer structure can be applied to a core substrate or a circuit board build-up layer. In the manufacturing process, 俾 can effectively reduce the process problems caused by shrinkage of the conventional technology, and there is no shrinkage risk and alignment problems in the conventional technology, which can improve the process yield, productivity, and exposure latitude. In addition, the insulating layer structure of the present invention can be used as an insulating layer and a dielectric-layer, and can also be directly used as a core substrate, which not only provides better alignment and shrinkage than the insulating layer and dielectric layer in the conventional technology. The effect of shrinkage rate is more widely used. The above-mentioned embodiments are merely illustrative for explaining the principle of the present invention and its effects, and are not intended to limit the present invention. Anyone skilled in the art can modify and change the above embodiments without departing from the spirit and scope of the present invention.

17663 Quan 懋 .ptd Page 17 1236324 V. Description of Invention (14). Therefore, the scope of protection of the rights of the present invention should be as described in the patent application scope described later.

17663 懋 .ptd page 18 1236324

Brief description of the diagram 21 Core substrate 22 Dielectric layer 23 Blind hole 24 Conductive film 25 Plating resist layer 31 Completely polymerized material layer 33, 35 Incompletely polymerized material layer 37 Upper film 39 Lower film 21 1 Resin core layer 212 Copper drop pattern 213 Conductive through hole 250 Opening Page 20 17663 Full 懋 .pt.d

Claims (1)

1236324 VI. Scope of patent application 1. A circuit board insulation layer structure, comprising: a fully polymerized material layer composed of a fully polymerized material; and two incompletely polymerized material layers composed of an incompletely polymerized material, The systems are formed on the upper and lower surfaces of the fully polymerized material layer, respectively. 2. If the circuit board insulation layer structure of the first patent application scope is applied, an upper layer film may be formed on the outermost layer of the insulation layer structure. 3. For the circuit board insulation layer structure of the second scope of the patent application, wherein the upper film is one selected from the group consisting of a metal layer, a protective layer, and a carrier layer. 4. For the circuit board insulation layer structure of the scope of the patent application, the upper film is copper foil. 5. For the circuit board insulation layer structure of the second patent application range, wherein the upper film is a removable organic film. 6. If the insulation layer structure of the circuit board in item 1 of the scope of patent application is applied, a lower layer film may be formed on the outermost layer of the insulation layer structure. 7. For the circuit board insulation layer structure of claim 6 in the patent scope, wherein the lower film is one selected from the group consisting of a metal layer, a protective layer, and a carrier layer. 8. For the circuit board insulation layer structure of the patent application item 6, wherein the lower layer film is copper foil. 9. For the structure of the insulating layer of a circuit board as claimed in item 6 of the patent application scope, wherein the lower film is a removable organic film. 1 0. The circuit board insulation layer structure according to the first patent application scope, wherein, the 17663 Quan 懋 .ptd Page 21 1236324 VI. The scope of patent application has been completely polymerized material layer is selected from the group consisting of epoxy resin (E ρ ο Xy resi η), S polyester, polyimide, and cyanate (Cyanate ester), glass fiber, bismaleimide / imide / nitrogen trap (B butma, B isma 1 eimidetriazine), and organic materials composed of mixed epoxy resin and glass fiber materials One. 1 1. The circuit board insulation layer structure according to item 1 of the scope of patent application, wherein the fully polymerized material layer is composed of a fiber-reinforced (F i be r-r e i n f o r c e d) composite material to improve strength. 12. The circuit board insulation layer structure according to item 1 of the scope of patent application, wherein the completely polymerized material layer is selected from the group consisting of particle-reinforced (Particle-reinf ◦ r c e d) composite materials to improve the strength. 1 3. The structure of the insulation layer of a circuit board according to item 1 of the scope of patent application, wherein the incompletely polymerized material layer is a semi-cured colloid. Among them, each (Epoxy, cyanoester (14. If the circuit board insulation layer structure of the first patent application scope, the incompletely polymerized material layer is selected from epoxy resin), polyester, and polyimide (Polyimide ) Cyanate ester), glass fiber, bismaleic acid imide / triazine (BT, -Bismaleimide triazine), and organic materials composed of epoxy resin and glass fiber One. 15. The circuit board insulation layer structure as described in the first item of the patent application scope, wherein the incompletely polymerized material layer is thinner than the completely polymerized material layer. 1 6. —A method for manufacturing a circuit board insulation layer structure, including: __ 17663 Quan 懋 .ptd Page 22 1236324 VI. Scope of patent application sandwiching a fully polymerized material layer between two incompletely polymerized material layers; and the upper and lower surfaces of the fully polymerized material layer along the The fully polymerized material layer is to be joined, and the joining is started from the fully polymerized material layer and one end of the incompletely polymerized material layer. 17. The method for manufacturing a circuit board insulation layer structure according to item 16 of the scope of patent application, wherein the incompletely polymerized material layers are thinner than the completely polymerized material layer. 18. The method for manufacturing an insulation layer structure of a circuit board according to item 16 of the scope of patent application, wherein the insulation layer structure is in a rolled state. 19. If the method of manufacturing a circuit board insulation layer structure according to item 16 of the patent application scope includes the activation of the fully polymerized material layer (Act i vat e) to strengthen the fully polymerized material layer and the incomplete Step of bonding force between layers of polymeric material. 20. If the method of manufacturing a circuit board insulation layer structure according to item 16 of the application for a patent, the method further includes roughening the fully polymerized material layer to strengthen the gap between the fully polymerized material layer and the incompletely polymerized material layer. Steps of bonding force. 2 1. A multi-layer circuit and board manufacturing method, including: providing a plurality of circuit board units with patterned circuit layers; and forming an insulation layer structure between the circuit board units as item 1 of the scope of patent application as an insulation layer Compressing the intersecting circuit board units into a multilayer bonding board through lamination and hot pressing steps; and 17663 Quan 懋 .ptd Page 23 1236324 VI. Patent application scope Drilling a plurality of through-holes, and plating a conductive metal layer on the surface of the through-hole hole wall to perform on the outermost conductive metal layer The circuit is patterned, and the circuit boards are electrically connected through the through-holes to obtain a multilayer circuit board. 2 2. A multi-layer circuit board comprising a plurality of circuit board units, each of which is separated by an insulation layer structure such as the one in the scope of patent application, characterized in that the insulation layer structure The fully polymerized material layer fills the gaps between the circuit layers of the early elements of the circuit board, and the fully polymerized material layer and the circuit board units are separated by the incompletely polymerized material layers. 2 3. A multi-layer circuit board includes a core substrate, which is a pre-processed double-layer or multi-layer circuit board. A multi-layer circuit board is formed by gradually increasing the surface of the core substrate. : The core substrate is formed with an insulation layer structure as described in item 1 of the scope of the patent application. The insulation layer structure fills the circuit layer gaps between the build-up structures with its incompletely polymerized material layer, and the completely polymerized material layer and The build-up structure on the core substrate is separated by the incompletely polymerized material layers. 2 2 4. The multilayer circuit board of claim 22 or item 23, wherein the fully polymerized material layer is selected from the group consisting of epoxy resin (E ρ ο X yresi η), polyester, Polyimide, Cyanate ester, glass fiber, bismaleimide / triazine (BT, Bisma 1 eimidetriazine), and mixed epoxy resin and glass fiber materials One of the groups of organic materials illl! 17663 Full 懋 .ptd Page 24 1236324 6. Scope of patent application. 25. The multilayer circuit board according to item 22 or 23 of the scope of patent application, wherein the fully polymerized material layer is composed of a fiber-reinforced (F i be r-r e i n f o r c e d) composite material to improve the strength. 2 6. The multilayer circuit board according to item 22 or item 23 of the scope of patent application, wherein the fully polymerized material layer is selected from the group consisting of particle reinforced (P artic 1 e-reinforced) composite materials to improve strength. 27. The multilayer circuit board according to item 22 or item 23 of the scope of patent application, wherein the incompletely polymerized material layers are semi-cured colloids. 2 8. If the multilayer circuit board of the scope of the application for the patent No. 22 or 23, wherein each of the incompletely polymerized material layers is respectively selected from the group consisting of epoxy resin, polyester, and polyethylamine (Polyimide), Cyanate ester, glass fiber, bismaleic acid imide / triazine (BT, Bisaleimide triazine) and organic materials composed of epoxy resin and glass fiber One of the groups. 29. If the multilayer circuit board of item 22 or 23 of the scope of patent application is applied, the incompletely polymerized material layers are thinner than the fully polymerized material layer / 0.30. The insulation layer structure includes: a fully polymerized material layer composed of a fully polymerized material; and two incompletely polymerized material layers composed of an incompletely polymerized material, respectively formed on the fully polymerized material layer Upper and lower surfaces. 17663 懋 .ptd Page 25