1236152 狹、發明說明 【發明所屬之技術領域】 本發明係關於一種半導體裝置以及其製造方法，特別 是關於一種可緩和發生於實際動作領域最外周之溝渠底部 的電場集中，並抑制耐壓惡化之半導體裝置及其製造方 法。 【先前技術】 第12圖顯示以溝渠構造之N通道型功率MOSFET(金 屬氧化半導體場效電晶體）為例之習知半導體裝置。 在N+型石夕半導體基板21上設置由N_型外延層所構成 之汲極領域22，在其表面設置p型通道層24。通道層24 係在I個貝際動作領域均以相同深度形成，在實際動作領 域外的通道層24周端部，則設有確保耐壓用之p +型領域 24a ° 舌又罝貝牙通道層丨、本 ' 田24且到達至汲極領域22之溝渠2: 以閘極氧化膜3 1覆芸、、#、、巨。， /、 现溝朱27之内壁，並設置由充填至 渠27之多晶石夕所構成 再成的閘極電極33。在鄰接溝渠27的 道層24表面形成有Ν i源極領域3 5，在彼此相鄰的兩 元之源極領域35間的 ^1236152 Narrow, description of the invention [Technical field to which the invention belongs] The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a method for mitigating the concentration of an electric field occurring at the bottom of a trench at the outermost periphery of an actual operation field and suppressing the deterioration of withstand voltage Semiconductor device and manufacturing method thereof. [Prior Art] Fig. 12 shows a conventional semiconductor device using a trench structure of an N-channel power MOSFET (metal oxide semiconductor field effect transistor) as an example. A drain region 22 made of an N_-type epitaxial layer is provided on the N + -type stone evening semiconductor substrate 21, and a p-type channel layer 24 is provided on the surface. The channel layer 24 is formed at the same depth in one shell motion area. At the peripheral end of the channel layer 24 outside the actual motion area, there is a p + -type field 24a for ensuring pressure resistance. Layer 丨, Ben 'field 24 and channel 2 to the drain region 22: Cover the gate electrode with the gate oxide film 3 1. The inner wall of the trench 27 is provided, and a gate electrode 33 composed of polycrystalline stone filled in the trench 27 is provided. N i source regions 35 are formed on the surface of the channel layer 24 adjacent to the trench 27, and between the two source regions 35 adjacent to each other ^
]通道層24表面上形成p +型主俨 領域。另外在通道層24 且I 、 則由源極領域3 5沿著溝渠27泌 通道領域（無圖示）。以 / ’ Λ層間絕緣膜36覆蓋閘極電極 設置接觸源極領域35 ,、； u 士 电柽33, 。 以及主體接觸領域34之源極電 參照第13圖至楚A p + -type main 俨 region is formed on the surface of the channel layer 24. In addition, at the channel layer 24 and I, the channel region (not shown) is passed from the source region 35 to the channel 27. The gate electrode is covered with an interlayer insulating film 36, and a contact source region 35 is provided. And the source voltage of the main contact area 34. Refer to Figure 13 to Chu
圖’係顯示以漢渠構造之N 315154 5 37 1236152 型功率MOSFET為例之習知半導體裝置製造方法。 在第13圖中，係在型半導體基板21上積層N_型 外延層並形成汲極領域22。在實際動作領域外之預定通道 層24周端部植入擴散高濃度之p型雜質，以形成型領 域24a。此外，又於整面以摻雜量1〇IS注入硼等雜質後y 擴散形成P型的通道層24。 第1 4圖至第1 5圖係顯示形成溝渠之步驟。 、在第。14圖中，藉由CVD(化學氣相成長）法全面形成厚 度為數千A之NSG(N，doped SiHcate⑴㈣)的cvd氧化 膜25,並以光阻膜所形成之料覆蓋除了作為溝渠開口部 ^以外的B，猎由乾钱刻切部分之c Μ氧化膜^， 形成通道領域24外露之溝渠開口部26。 在第15圖中，以cvd 1[外腺oc a &Figure ′ shows a conventional method for manufacturing a semiconductor device using an N 315154 5 37 1236152 power MOSFET structure of the Hanqu structure as an example. In FIG. 13, an N_-type epitaxial layer is laminated on a semiconductor substrate 21 to form a drain region 22. A p-type impurity having a high concentration is diffused and implanted at a peripheral end portion of a predetermined channel layer 24 outside the actual operation field to form a type field 24a. In addition, boron and other impurities are implanted at a doping amount of 10IS over the entire surface to form a P-type channel layer 24 after y diffusion. Figures 14 to 15 show the steps for forming a trench. In the first. In FIG. 14, a cvd oxide film 25 of NSG (N, doped SiHcate⑴㈣) with a thickness of several thousand A is fully formed by a CVD (chemical vapor growth) method, and is covered with a material formed by a photoresist film except for a trench opening. ^ Other than B, the CM oxide film ^ cut from the dry money to form the trench openings 26 exposed in the channel area 24. In FIG. 15, cvd 1 [
乳化膜25作為遮罩並藉由CF 系或HBr系氣體對溝渠開 ^ 卞開邛26的矽半導體基板進行乾 餘刻，以形成貫穿通道層24 泪0 1 且，木度達到汲極領域22的溝 木2 7。 仃假氧化而於溝渠27内壁與通 層24表面形成氧化膜仏 飿刻…m)，並去除乾餘刻時所造成 、劳之後藉由|虫刻去除 之诒 π λ、日日 亥虱化膜與CVD氧化膜25 之後，形成閘極氧化膜3丨。 # ^ ^ ^ ^ A _ 王面進行熱氧化以形 子度約數百Α之閘極氧化膜3 1。 第丨7圖係形成埋設於溝竿 在整面上附著無推雜的多晶：層”之極電極33。亦即 以實現高電導率化，並形成閑直入擴散高濃度的 ^極33。之後在無遮罩 315154 6 1236152 情況下對附著於整面之多晶 ^ ^ ^ 07 曰進仃乾Μ刻，並殘留埋設 於溝木27内之閘極電極33 〇 弟18圖係藉由光阻藤 旦1〇,5雜工扯 尤戶膜所構成的遮罩選擇性地以摻雜 里 離子植入哪，並於形成Ρ 4荆—山 ,^ r 於开/成P +型之主體接觸領域34後， 去除光阻膜PR。 預定的源極領域 離子植入砷，並 N+型源極領域 之後，以新的光阻膜pR作為遮罩使 35以及閘極電極33露出，以摻雜量1〇】5 在與溝渠27鄰接的通道層表面24上形成 3 5後，去除光阻膜。 μ 後，藉* CVD 法使 BPSG(B〇r〇n phospho·仙灿 GUSS)層附著於整面，以形成層間絕緣膜36。之後，以光 阻膜作為遮罩至少在閘極電極33上殘留層間絕緣膜36。 之後以濺鐘裝置使銘全面附著，以形成與源極領域Μ以及 主體接觸領域34接觸之源極電極37。藉此，可在實際動 作領域中配置多數個MOSFET28。 、如此，在習知溝渠構造之MOSFET中，設於實際動作 領域之溝渠27以及M〇SFET28的深度幾乎全部均一。（例 如’筝照專利文獻1)。 在6亥溝渠構造的高耐壓M0SFET中，於源極電極與汲 極電極之間’施加以汲極電極為正電壓之電源電壓的狀態 下，對閘極電極施加閾值電壓以上之驅動電壓時，會在沿 著溝渠的通道層形成通道領域，電流即透過通道領域產生 流動，而使MOSFET呈現導通狀態。 另一方面’於源極電極與汲極電極之間，施加以汲極 7 315154 1236152 電極為正電壓之電源電壓的 4 0狀L下，當施加於閘極電極的 驅動電壓在閾值電壓以下時， μ t 子M0SFET會呈現關斷狀態。 (專利文獻1) 曰本特開平9-2705 12號公報（第1〇頁，第23 【發明内容】 (發明所欲解決之課題） 在習知溝渠構造的高耐壓m〇sfet中，在關斷狀態 ί血層曰如第12圖虛線所示從反向偏壓的通道層μ 與沒極領域22界面之⑼接合處開始擴展。將此耗盡層設 定為施加驅動電壓V。時的耗盡層。因為㈣領域22之Ν_ 外延層的雜質濃度& ρ型通道層24之雜質濃度低，因此 大多數的耗盡層會向沒極領域22方向延伸並保持沒極電 壓。 在此狀心下，因為最外周溝渠2 7 &之底部邊緣，與實 際動作領域内之溝退？ 7 + t μ叙> 再木27之底部邊緣相比較具有最大的電 場強度， 故在此會發生電場集中。 以下說明其原因。 首先，各溝渠底部邊緣的電場強度Ε可以下列公式表 E = VO/d 在上述公式中，d為從各溝渠的底部邊緣到最接近的 及極領域側的耗盡層端之距離，如帛12圖所示，在最外周 溝渠27a中距離& dn，在實際動作領域的溝渠27中則為 8 315154 1236152 dl2。 卜在/及極7員域22擴展的耗盡層’雖與鄰接之耗 :層連成-體，但擴展於通道層24的耗盡層 有絕緣膜的溝渠27内部，故可藉由溝渠27分離：在實； =領域中，由於係藉由各溝渠27分離且通道層μ㈣ 貝浪度比及極領域22 <雜質濃度高，故耗盡層往通道声 24方向擴展的情況較少’而是往極極領域22方向大幅擴 展。另-方面在最外周溝渠27a的外側，直至p+型領域 為止，係以20/zm程度的距離充分隔離，由於沒有溝 、的限制因此耗盡層在通道層24側會比實際動作領 域更奋易擴展。此外，在固定之施加電壓v〇 #情況下， 擴展取大之部分的耗盡層的寬度d〇係在實際動作領域内 以及其外圍皆為大致均一的寬度。 亦即，在最外周溝渠27a的外側，耗盡層容易往通道 層24側擴展的部分，耗盡層往汲極領域33側的擴展係比 貝際動作領域内少。因此，底部邊緣至耗盡層的距離會比 $渠27窄（dl2>dll)。另外，在實際動作領域内，由於溝 呆2 7係以等間隔配置，且耗盡層呈均等擴展，所以只有最 外周的溝渠2 7 a到耗盡層的距離d 11較短。 亦即’各溝渠的底部邊緣之電場強度E係以最外周溝 渠27a最強，而在此產生電場集中。因此，會使汲極源極 間（在IGBT中則為集極射極間）的耐壓惡化，且高溫時會發 生額定值下滑的問題。 具體來說’第19圖為表示集極射極間耐壓（Vces)與 9 315154 1236152 溫度（Ta)的特性圖。根據本圖，因為電場隼 勿木甲，周圍溫度 在75度以上時VCES值會下降，而成為負的溫度特性。因 此無法改善特性，I因電場集中而產生之集極射極間的耐 壓惡化情形也會造成相當大的問題。 (解決課題之手段） 本發明係鑑於上述課題而創作者，第1樣態係具備 有：設於基板表面之雜質領域；設於該雜質領域周端部之 南濃度雜質領域；貫穿前述雜質領域之多數個溝渠構造的 第1電晶體；以及在前述第i電晶體外周與前述高濃度雜 質領域接近，且設置在比前述第丨電晶體更深之位置的第 2電晶體。 第2樣態係具備有配列多數個第1電晶體單元的實際 動作領域’該第1電晶體單元係由：設於半導體基板表面 之第1雜質領域；設於前述第1雜質領域周端部之高濃度 雜質領域；貫穿前述第1雜質領域之溝渠；至少覆蓋前述 溝渠内之絕緣膜；由埋設於前述溝渠内之半導體材料、及 鄰接設置於前述溝渠之第2雜質領域所構成； 具備有在前述實際動作領域最外周與前述高濃度雜 質領域接近’且設置於比前述第1電晶體更深之位置的第 2電晶體。 第3樣態係具備有配列多數個第1電晶體單元的實際 動作領域’单元係由·设於作為沒極領域之一導電型半導 體基板表面之逆導電型雜質領域的通道層；設於前述通道 層周端部之高濃度雜質領域；貫穿前述通道層之溝渠；至 315154 10 1236152 少覆蓋前述溝渠内之絕緣膜；由埋設於前述溝渠内之半導 體材料所構成之電極；及由在前述通道層表面與前述溝渠 鄰接設置之一導電型源極領域所構成， 且具備有在前述實際動作領域最外周與前述高濃度 雜質領域接近，且設置於比前述第1電晶體更深之位置的 第2電晶體。 另外，本發明之特徵為前述第2電晶體與前述高濃度 雜質領域的間隔距離，係比前述第1電晶體彼此間的間隔 距離短。 另外，本發明之特徵為：前述第2電晶體係設置於比 前述高濃度雜質領域更淺之位置。 另外，本發明之特徵為構成前述第2電晶體之前述溝 渠開口寬度係比構成前述第1電晶體之前述溝渠的開口寬 度寬。 另外，本發明之特徵為在前述第1電晶體的外周以及 為前述第2電晶體的内周，設有比前述第2電晶體淺但比 前述第1電晶體深之第3電晶體。 另外，本發明之特徵為：構成前述第3電晶體之前述 溝渠開口寬度，係比構成前述第1電晶體之前述溝渠開口 寬度寬，而比構成前述第2電晶體之前述溝渠開口寬度 窄。 第4樣態係使用開口寬度不同的遮罩，並藉由於同一 步驟中在第1溝渠與該第1溝渠外周形成比該第1溝渠更 深之第2溝渠。 11 315154 1236152 第5樣態係具備有：在半導體基板表面形成第1雜質 領域之步驟；形成貫穿前述第1雜質領域之多數個第1溝 渠的步驟；同時在該第1溝渠最外周形成比該第1溝渠更 深之第2溝渠的步驟；在前述第1以及第2溝渠内壁形成 、、、巴緣膜之步驟；在前述第1以及第2溝渠埋設半導體材料 之步驟；及與前述第1以及第2溝渠相鄰接而形成第2雜 質領域的步驟。 第6樣態本發明為具備有 型半導體基板表面形成逆導電 前述通道層之多數個第1溝渠 最外周形成比該第1溝渠更深 第1以及第2溝渠内壁形成閘 設於前述第1以及第2溝渠之 步驟；及在前述通道層與前述 成一導電型源極領域的步驟。 另外’本發明之特徵為在 步驟中，前述第2溝渠係形成 開口0 型通道層之步驟；形成貫穿 的步驟；同時在該第1溝渠 之第2溝渠的步驟；在前述 極絕緣膜之步驟；形成由埋 半導體材料所構成之電極的 第1與第2溝渠相鄰接而形 刖述第1以及第2溝渠形成 比别述第1溝渠更寬之遮罩 另外，本發明之特徵為在前 步驟中’纟前述第i溝渠外周以及第2編 形成比前述第i溝渠深但比前述第二溝渠… 另外，本發明之特徵為前述第3溝=之第3溝葬 度，係比前述第i溝渠之遮罩開 f的遮罩開口 渠之遮罩開口寬度窄。 見没見’比前述第2 315154 12 1236152 【實施方式】 以下以溝渠構造之N通道型功率M〇SFet為例詳細說 明本發明之實施例。 首先，參照第1圖至第8圖，說明本發明第丨實施例 之半導體裝置。 第1圖為本實施形態之半導體裝置之剖視圖。具有第 1電晶體8以及第2電晶體8a之半導體裝置，係由：半導 體基板1、2、通道層4、高濃度雜質領域4a、溝渠7、7a、 閘極氧化膜11、閘極電極1 3、源極領域1 5與金屬電極][7 所構成。 千导體基板係在 外延層以形成汲極領域2。 、通道層4為選擇性地在汲極領域2表面植入p型硼 的擴散領域。在與該通道層4之溝渠7鄰接的領域上， 道領域（無圖示）。通道層4係在配置有m〇sfet8、 :只際動作領域全面形成相同的深度，且在實際動作領 之通道層4周端部，設有用以確保耐壓之p +型領域4习 溝渠7、乃係貫穿實際動作領域的通道層4且^ 極領域9 A j運. a 2，一般而言係在半導體基板上圖案化為格子狀； :條狀。實際動作領域内設有多數個溝渠7， · 二木7更深之溝渠7a。另外，溝渠7a的開口寬The emulsified film 25 is used as a mask, and the silicon semiconductor substrate of the trench opening CF is opened by CF-based or HBr-based gas. The silicon semiconductor substrate is etched to form a penetrating channel layer 24. Tear 0 1 and the woodiness reaches the drain region 22 Ditch wood 2 7.仃 oxidized to form an oxide film on the inner wall of the trench 27 and the surface of the through-layer 24 engraved ... After the film and the CVD oxide film 25, a gate oxide film 31 is formed. # ^ ^ ^ ^ A _ The king surface is thermally oxidized to form a gate oxide film 31 having a degree of about several hundred A. FIG. 7 shows the formation of a pole electrode 33 buried in a trench rod and adhering non-doped polycrystals: layers. That is to say, to achieve high conductivity, and to form a high-concentration pole electrode 33 with a high concentration of free-standing diffusion. After that, without masking 315154 6 1236152, the polycrystals attached to the entire surface ^ ^ ^ 07 said that it was dry and carved, and the gate electrode 33 buried in the trench 27 was left. The picture of 18 is by light The mask formed by the hindrance of the vineyard 10,5 is selectively implanted with doped ions, and is formed in the form of P 4 Jing-Shan, ^ r is contacted by the body of the P / type. After the area 34, the photoresist film PR is removed. After arsenic is implanted in the predetermined source area and the N + type source area is used, a new photoresist film pR is used as a mask to expose 35 and the gate electrode 33 to be doped. Amount 10] 5 After forming 3 5 on the channel layer surface 24 adjacent to the trench 27, the photoresist film was removed. After μ, a BPSG (Boron phospho · Sincan GUSS) layer was attached to the substrate by a CVD method. The entire surface is formed to form an interlayer insulating film 36. After that, a photoresist film is used as a mask to leave at least the interlayer insulating film 36 on the gate electrode 33. Thereafter, a bell-type device is used. The inscription is fully attached to form the source electrode 37 in contact with the source region M and the main contact region 34. In this way, a plurality of MOSFETs 28 can be arranged in the actual operation field. In this way, in the MOSFET of the conventional trench structure, The depth of the trench 27 and the MOSFET 28 provided in the actual operation field is almost uniform. (Eg, "Zheng Zhao Patent Document 1"). In the high-withstand voltage MOSFET with a structure of the 6th Hai trench, between the source and drain electrodes 'In a state where the drain electrode is applied with a positive voltage and a driving voltage greater than a threshold voltage is applied to the gate electrode, a channel area is formed in the channel layer along the trench, and current flows through the channel area, and The MOSFET is turned on. On the other hand, between the source electrode and the drain electrode, a driving voltage of 40 Ω with a drain voltage of 7 315 154 1236152 applied to the positive electrode is applied to the gate electrode. When the voltage is below the threshold voltage, the μ t-sub M0SFET is turned off. (Patent Document 1) Japanese Patent Application Laid-Open No. 9-2705 No. 12 (Page 10, page 23) [Summary of the Invention] (Problems to be Solved by the Invention) In the high withstand voltage m0sfet of the conventional trench structure, in the off state, the blood layer is reversely biased from the channel layer μ and the infinite region as shown by the dotted line in FIG. 12. The junction of the osmium at interface 22 is expanding. This depletion layer is set to the depletion layer at the time when the driving voltage V is applied. Because the impurity concentration of the N_ epitaxial layer in the ytterbium region 22 & p-type channel layer 24 has a low impurity concentration, Therefore, most of the depletion layer will extend toward the electrodeless region 22 and maintain the electrodeless voltage. Under this circumstance, because the bottom edge of the outermost peripheral trench 2 7 & is receding from the actual action area? 7 + t μs > The bottom edge of Zaiki 27 has the largest electric field strength in comparison, so electric field concentration will occur here. The reason is described below. First, the electric field intensity E at the bottom edge of each ditch can be expressed by the following formula: E = VO / d In the above formula, d is the distance from the bottom edge of each ditch to the closest and polar region side depletion layer end, such as 帛As shown in Fig. 12, the distance & dn in the outermost trench 27a is 8 315154 1236152 dl2 in the trench 27 in the actual operation area. Although the depletion layer extended in / and the pole 7 member field 22 is connected to the adjacent power consumption layer, the depletion layer is integrated into a body, but the depletion layer that extends in the channel layer 24 has an insulation film inside the trench 27. 27 separation: in reality; = In the field, since the channel 27 is separated and the channel layer μ㈣ is more rugged than the polar region 22 < impurity concentration, the depletion layer is less likely to expand in the direction of channel sound 24. 'Rather, it has expanded significantly in the direction of pole area 22. On the other hand, on the outside of the outermost ditch 27a, up to the p + type area, it is fully isolated at a distance of about 20 / zm. Because there are no grooves and restrictions, the depletion layer will be more aggressive on the channel layer 24 side than the actual action area. Easy to expand. In addition, in the case of a fixed applied voltage v0 #, the width do of the larger depletion layer, which is taken as a larger portion, is substantially uniform in the actual operation area and its periphery. That is, on the outer side of the outermost trench 27a, the depletion layer tends to expand toward the channel layer 24 side, and the depletion layer extends to the drain region 33 side less than in the bay area. Therefore, the distance from the bottom edge to the depletion layer is narrower than $ 27 (dl2> dll). In addition, in the actual operation field, since the trenches 27 are arranged at equal intervals and the depletion layer expands evenly, only the outermost trench 27a to the depletion layer has a short distance d11. That is, the electric field intensity E at the bottom edge of each trench is the strongest at the outermost trench 27a, and an electric field concentration occurs here. As a result, the withstand voltage between the drain and source (in the case of IGBT, the collector and emitter) deteriorates, and the problem of reduced ratings occurs at high temperatures. Specifically, FIG. 19 is a characteristic diagram showing a collector-emitter withstand voltage (Vces) and a temperature (Ta) of 9 315 154 1236152. According to this figure, because the electric field does not require wood armor, the VCES value decreases when the surrounding temperature is above 75 degrees, and becomes a negative temperature characteristic. Therefore, the characteristics cannot be improved, and the deterioration of the withstand voltage between the collector and the emitter due to the concentration of the electric field also causes a considerable problem. (Means for Solving the Problem) The present invention was created by the present invention in view of the above-mentioned problems. The first aspect includes: an impurity field provided on the surface of the substrate; a south concentration impurity field provided at the periphery of the impurity field; A first transistor having a plurality of trench structures; and a second transistor that is close to the high-concentration impurity region on the periphery of the i-th transistor and is located deeper than the first transistor. The second aspect is provided with an actual operation area in which a plurality of first transistor units are arranged. The first transistor unit is composed of a first impurity region provided on a surface of a semiconductor substrate and a peripheral end portion of the first impurity region. A high-concentration impurity region; a trench penetrating the aforementioned first impurity region; at least an insulating film covering the aforementioned trench; a semiconductor material buried in the aforementioned trench; and a second impurity region disposed adjacent to the aforementioned trench; A second transistor which is close to the high-concentration impurity region on the outermost periphery of the actual operation region and is disposed deeper than the first transistor. The third aspect is provided with a practical operation field including a plurality of first transistor units. The cell is provided with a channel layer provided on the surface of a conductive semiconductor substrate, which is one of the conductive semiconductor substrates. The area of high-concentration impurities at the peripheral end of the channel layer; the trenches running through the aforementioned channel layer; to 315154 10 1236152 covering the insulating film in the aforementioned trench; an electrode composed of a semiconductor material buried in the aforementioned trench; and an electrode formed in the aforementioned channel The surface of the layer is formed of a conductive type source region adjacent to the trench, and includes a second region which is close to the high-concentration impurity region at the outermost periphery of the actual operation region and is located deeper than the first transistor. Transistor. In addition, the present invention is characterized in that the distance between the second transistor and the high-concentration impurity region is shorter than the distance between the first transistors. In addition, the present invention is characterized in that the second transistor system is provided at a position shallower than the high-concentration impurity region. Further, the present invention is characterized in that the width of the opening of the trench constituting the second transistor is wider than the width of the opening of the trench constituting the first transistor. Further, the present invention is characterized in that a third transistor which is shallower than the second transistor but deeper than the first transistor is provided on the outer periphery of the first transistor and the inner periphery of the second transistor. In addition, the present invention is characterized in that the width of the trench openings constituting the third transistor is wider than the width of the trench openings constituting the first transistor and narrower than the width of the trench openings constituting the second transistor. In the fourth aspect, a mask with a different opening width is used, and a second trench deeper than the first trench is formed on the periphery of the first trench and the first trench in the same step. 11 315154 1236152 The fifth aspect includes: a step of forming a first impurity region on the surface of the semiconductor substrate; a step of forming a plurality of first trenches penetrating the first impurity region; and forming a ratio on the outermost periphery of the first trench. The step of the second trench deeper in the first trench; the step of forming a thin film on the inner walls of the first and second trenches; the step of burying a semiconductor material in the first and second trenches; and the steps of the first and second trenches A step in which the second trench is adjacent to form a second impurity region. A sixth aspect of the present invention is to provide a plurality of first trenches on the surface of a semiconductor substrate having a reverse conductivity. The first trenches are formed deeper than the first trenches. The inner walls of the first and second trenches are formed on the first and second trenches. 2 steps of trenches; and steps of forming a conductive source region between the aforementioned channel layer and the aforementioned. In addition, the present invention is characterized in that in the step, the aforementioned second trench is a step of forming an open 0-type channel layer; a step of forming a penetration; a step of simultaneously forming a second trench of the first trench; and a step of the aforementioned polar insulating film The first and second trenches forming an electrode made of a buried semiconductor material are adjacent to each other and the first and second trenches form a wider mask than the other first trenches. In addition, the present invention is characterized in that In the previous step, the outer periphery of the i-th trench and the second formation are deeper than the i-th trench but larger than the second-ditch ... In addition, the present invention is characterized by the third trench = the third trench burial degree, which is higher than the foregoing The mask opening of the i-th trench has a narrow mask opening width. See if you can't see the above 2nd 315154 12 1236152 [Embodiment] The following describes the embodiment of the present invention in detail with the N-channel power MOSFet of the trench structure as an example. First, a semiconductor device according to a first embodiment of the present invention will be described with reference to Figs. 1 to 8. FIG. 1 is a cross-sectional view of a semiconductor device according to this embodiment. A semiconductor device having a first transistor 8 and a second transistor 8a is composed of a semiconductor substrate 1, 2, a channel layer 4, a high-concentration impurity region 4a, a trench 7, 7a, a gate oxide film 11, and a gate electrode 1 3. Source area 15 and metal electrode] [7. The thousand-conductor substrate is attached to an epitaxial layer to form a drain region 2. The channel layer 4 is a diffusion region in which p-type boron is selectively implanted on the surface of the drain region 2. The area adjacent to the trench 7 of the channel layer 4 is a channel area (not shown). The channel layer 4 is formed with the same depth in the field of motion. It is equipped with p + type fields 4 to ensure pressure resistance at the end of the periphery of the channel layer of the actual action. 4 , Is the channel layer 4 that runs through the actual action field and the pole field is 9 A. The a 2 is generally patterned into a grid pattern on a semiconductor substrate;: stripe. There are many ditches 7 in the actual action area, and the deeper ditch 7a of Ermu 7 is. In addition, the opening of the trench 7a is wide
木7寬。藉此，如後述一般，可同時形成 X 溝渠7、7 丁小风木度不同έ a。但是，該溝渠7a只須比溝渠7深即可， 其他步驟中藉由改變蝕刻條件等來形成。 /、 315154 13 1236152 閘極氧化膜n至少係設於與通 7a内壁，卄啦人庄广去； 相接的溝渠7、 並配a驅動電壓設定為數百A的 氧化膜11 Λ绍鎊摇 ^ y 又0因為閘極 為絶緣膜，而形成由設置於溝渠7、7 電極1 3與丰導#其π + a内之閘極 一干V脰基板所夾持之M〇s構造。 閘極電極13係由埋設於溝渠7、7a 在該多晶矽中導a古田— < 夕日日石夕所構成， 中V入有用以貫現低電阻化之p 極電極i 3孫&細s ^ m 主亦隹貝。該閘 (無圖示），並盘設於半導，其国之閘極連結電極 处。 …^+¥體基板上^極料電極相連 源極領域15為在鄰接溝渠7、〜之通道層4表面植 N+型雜質後之擴散領域，與覆蓋實際動作 電極，妾觸。另外，在鄰接之源極領域15間的= 表面。又置P +型雜質擴散領域之主體接觸領域丨4，以實 現基板電位之穩定化。 貝 層間絕緣膜1 6為使源極電極1 7與閘極電極1 3絕緣， 置寸至 >、品覆盖閘極電極1 3，而將其中一部分留於溝 渠開口部。 / 源極電極1 7係對鋁等進行濺鍍而圖案化為所希望的 形狀，並覆蓋於實際動作領域上，而與源極領域15以及主 體接觸領域1 4相接觸。 藉此’可在實際動作領域内藉由溝渠7配置多數個第 1M0SFET8，第2M〇SFET8a係藉由溝渠7a配置於第 1M0SFET8的外周。第2M〇SFET8a係設置成比第1電晶 體8深且比p +型領域乜淺。 14 315154 1236152 此外，如後所詳述一般，第2MOSFET8a係與P +型領 域4a接近配置。具體來說，第2MOSFET8a與P +型領域 4a間的間隔距離W2，係比第1M0SFET8彼此間的間隔距 離，或是第1M0SFET8與第2MOSFET8a的間隔距離（也就 是單元節距）W1短。另外，P +型領域4a與第2MOSFET8a 亦可相接。 在該溝渠構造的高耐壓MOSFET中，係於源極電極與 汲極電極之間，在施加以汲極電極為正電壓之電源電壓的 狀態下，對閘極電極施加閾值電壓以上的驅動電壓時，在 沿著溝渠形成的通道層上會形成通道領域，電流係透過通 道領域進行流動，而MOSFET則形成導通狀態。 另一方面，在源極電極與汲極電極之間，在施加以汲 極電極為正電壓之電源電壓的狀態下，當施加於閘極電極 的驅動電壓在閾值電壓以下時，MOSFET會呈現關斷狀 態。 本發明之特徵，係在第1M0SFET8的外周設置比第 1M0SFET8深且比P +型領域4a淺之第2MOSFET8a，並與 P +型領域4a形成接近配置。 在上述溝渠構造的高耐壓MOSFET中，耗盡層係在關 斷狀態下，如第1圖虛線所示從反向偏壓之通道層4與汲 極領域2界面之PN接合處進行擴展。以此耦盡層作為施 加驅動電壓Vo時之耗盡層。汲極領域2之N-型外延層， 相較於P型通道層4其雜質濃度較低，故大多數之耗盡層 會往汲極領域2方向延伸，並保持汲極電壓。 15 315154 1236152 在本κ施形中’除了設置第2M〇SFET8a並與p +型 領域4a接近配置之外其他構成要素皆與先前相同。此時如 施加相同的驅動電壓Vo _，耗盡層會如第12圖所示—般 擴展，耗盡層整體的厚度也會形成與先前相同之如。 但是，在本實施形態中，第2M〇SFET8a係比第 1MOSFET8 深，比 P +形作 p j ^ 、 木 1領域4a淺，且與P +型領域4a接 近配置。由於通道層4係與p +型領域化相連接，且料型 領域4 a較深之故，耗盡芦合一 層曰如圖所不一般沿著P +型領域 4 a與〉及極領域2的界面擴展。力 — ，、展在此，精由將第2MOSFET8a 與P +型領域4a的間隔距離貿2今宏Λ甘从Λ 一 ζ °又疋成其他MOSFET間的 間隔距離W1以下，從；)：盖#铱0 λ, a 划“ 構成4 2M〇SFET8a之溝渠7a的底 部邊緣擴展到汲極領域2的鉍 一 耗盡層會以往P +型領域4a下 推之形悲擴展。藉此，在保接乂 “等有/、先則相同之耗盡層厚声 d〇的實際動作領域周端部 又 |攸構成第2M〇SFET8a之溝渠 7a的底部邊緣到擴張到汲極領域2之耗盡声 - d2，會比先前的d j j (參 孤曰、、，、距離 b…、弟12圖）更大。亦即， 不之最外周溝渠7a之底邻、套絡从+ 图所 小於弈乂夕” 邊緣的電場強度E2(，/d2)會 小於先別之最外周溝渠27a P 1 1 1 Ν Α ^邊、緣的電場強产Wood 7 wide. As a result, as will be described later, X trenches 7 and 7 can be formed at the same time. However, the trench 7a only needs to be deeper than the trench 7. In other steps, the trench 7a is formed by changing the etching conditions. / 、 315154 13 1236152 The gate oxide film n is at least installed on the inner wall of the pass 7a, and the Doraren Village is wide; the trench 7 is connected, and the oxide film 11 with a driving voltage set to several hundred A is shaken. ^ y and 0 because the gate electrode is an insulating film, a Mos structure sandwiched between a gate electrode and a dry V 脰 substrate provided in the trenches 7, 7 electrodes 13 and Feng Dao # its π + a is formed. The gate electrode 13 is formed by buried in the trenches 7 and 7a in the polycrystalline silicon to conduct an ancient field-< Xi Ri Ri Shi Xi, the middle electrode is useful to realize the low resistance of the p pole electrode i 3 grand & fine s ^ m Lord also 隹 shellfish. The gate (not shown) is arranged on the semiconductor, and its gate is connected to the electrode. … ^ + ¥ on the body substrate ^ electrode materials are connected The source field 15 is a diffusion field where N + -type impurities are planted on the surface of the channel layer 4 adjacent to the trenches 7, to contact the actual working electrode. In addition, the surface between 15 adjacent source regions = surface. The main contact area of the P + -type impurity diffusion area is also set to stabilize the substrate potential. In order to insulate the source electrode 17 from the gate electrode 13, the interlayer insulating film 16 is set to > and covers the gate electrode 13 while leaving a part of it at the trench opening. / The source electrode 17 is patterned into a desired shape by sputtering aluminum, etc., and covers the actual operation area, and contacts the source area 15 and the main body contact area 14. In this way, a plurality of first MOSFETs 8 can be arranged through the trench 7 in the actual operation field, and the second MOSFET 8a is arranged on the outer periphery of the first MOSFET 8 through the trench 7a. The 2MOSFET 8a is provided deeper than the first transistor 8 and shallower than the p + -type region. 14 315154 1236152 In addition, as will be described in detail later, the second MOSFET 8a is arranged close to the P + -type area 4a. Specifically, the separation distance W2 between the second MOSFET 8a and the P + -type region 4a is shorter than the separation distance between the first MOSFET 8a, or the separation distance (that is, the cell pitch) W1 between the first MOSFET 8a and the second MOSFET 8a. The P + -type region 4 a may be connected to the second MOSFET 8 a. In this trench-structured high-withstand voltage MOSFET, a driving voltage equal to or higher than a threshold voltage is applied to a gate electrode while a source voltage having a positive voltage is applied to the drain electrode between the source electrode and the drain electrode. At this time, a channel area is formed on the channel layer formed along the trench, a current flows through the channel area, and the MOSFET is turned on. On the other hand, between the source electrode and the drain electrode, in a state where a power supply voltage with the drain electrode being a positive voltage is applied, when the driving voltage applied to the gate electrode is below the threshold voltage, the MOSFET will turn off. Off state. A feature of the present invention is that a second MOSFET 8a that is deeper than the first MOSFET 8 and shallower than the P + -type region 4a is provided on the outer periphery of the first MOSFET 8 and forms a close arrangement with the P + -type region 4a. In the above-mentioned trench structure high-withstand voltage MOSFET, the depletion layer is extended from the PN junction at the interface of the reverse-biased channel layer 4 and the drain region 2 as shown by the dotted line in FIG. 1. This decoupling layer is used as a depletion layer when the driving voltage Vo is applied. The N-type epitaxial layer in the drain region 2 has a lower impurity concentration than the P-type channel layer 4, so most of the depletion layer will extend in the direction of the drain region 2 and maintain the drain voltage. 15 315154 1236152 In this κ configuration, except that the 2MMOSFET 8a is provided and is close to the p + type field 4a, the other components are the same as before. At this time, if the same driving voltage Vo _ is applied, the depletion layer will expand as shown in FIG. 12, and the thickness of the entire depletion layer will be the same as before. However, in this embodiment, the second MOSFET 8a is deeper than the first MOSFET 8 and is formed to be pj ^, which is shallower than the P1 region 4a, and is arranged close to the P + type region 4a. Because the channel layer 4 is connected to the p + type field, and the material type field 4 a is deep, the depletion layer is depleted. As shown in the figure, the P + type field 4 a and> and the pole field 2 are not generally used. Interface expansion. Force— ,, here, the reason is to make the distance between the second MOSFET 8a and the P + type field 4a, and the current distance between the second MOSFET Λgan from Λ-ζ ° and the distance between other MOSFETs below W1, from;): cover # Iri0 λ, a stroke "The bottom edge of the trench 7a constituting 4 2MOSFET 8a extends to the drain region 2 of the bismuth-depletion layer. Then, "the first and last of the same depletion layer is thick and the sound is the same. The end of the actual action area | Yo | constitutes the bottom edge of the trench 7a of the 2MMOSFET 8a to the drain sound that expands to the drain area 2. -d2 will be larger than the previous djj (Shen Gu Yue, ,,, distance b ..., brother 12). That is, the electric field strength E2 (, / d2) at the bottom edge of the outermost peripheral trench 7a, the envelope from the + figure is less than that of Yixianxi, will be smaller than the outermost peripheral trench 27a P 1 1 1 Ν Α ^ Strong electric fields at edges and edges
El(—Vo/dll)，而得以緩和 — 又 間的耐壓惡化，並大 卩f i汲極源極 第2圖顯示具體之隹托自“ ^月的問碭。 (VCES-Ta #^±) 〇 ^ A _ 〃門圍 k 度的特性 性，虛線為先前技術之特性.^ 件的特 议何之特性。根據此圖係藉 之構造，使周圍溫度（丁 ) 用本％明 )保持在^額定溫度《150度的 315154 16 1236152 範圍内而V C E S為正的溫度特性。相較於先前周圍溫度在 7 5度以上就會成為負的溫度特性，其特性已有大幅的改 善。 另外’在本發明實施形態中係以MOSFET為例進行說 明，但在IGBT中，本發明之構造也適用並可獲得同樣的 效果。 接者利用第3圖至弟8圖說明本發明之半導體裝置势 造方法。 本發明之半導體裝置製造方法，係包括：在形成汲極 項域之‘電型半導體基板表面形成逆導電型通道層之步 驟；形成貫穿通道層之多數個第丨溝渠，同時在第丨溝渠 外周形成比第1溝渠更深之第2溝渠的步驟；纟第i以及 第2溝渠内壁形成閘極絕緣膜之步驟；形成由埋設於第^ 以及第2溝渠之半導體材料所構成之電極的步驟；在通道 層與第卜第2溝渠相鄰接而形成導電型源極領域之步驟。 :月第1步驟如第3圖所#，係在作為汲極領域 之‘電型半導體基板表面形成逆導電型的通道層4。 在型碎晶半導體基板】積層沐型外延層^形成这 極=2。在貫際動作領域外之預定通道層4周端部，相 ° ’辰度P型雜質’以擴散形成P+型領域4a。接著，全 面以摻雜量〗0”植入卿等雜質後，擴散形成p型通道層4 , 為1GBT柃，右在P +型矽半導體基板設置Ν空 以二層，再於其上積層N，外延層而形成集極領域，㈣ 以同一步驟實施後序步驟。 315154 17 1236152 如弟4圖至第— ^这& ^ ^ 圖所示，本發明之第2步驟係形成貫 穿通道層之多數個第1、、#、、巨 ^ 1 ,.E 4乐，並於第1溝渠最外周同時形 成比第1溝糸深之第2溝渠。 本步驟為本發明之牲 、政’係使用溝渠開口部之開口寬 度不同的遮罩而在同一+’ 與第2溝渠7a。-驟中形成深度不同的第 第4圖中，係全面藉由CVD法形成厚度為數千人的 NSG(Non-doped Silicatp η 、， iicateGlassw CVD氧化膜5。然後，於 形成溝渠開口冑26以外的部分覆蓋由光阻膜所形成之遮 罩，並藉由乾蚀刻去除部分之CVD氧化膜5，以形成通道 領域4露出之溝渠開口部 ' 6a此時，若為同一蝕刻條 件，則利用開口部寬度越大溝準 再木冰度越冰的特性，並使用 具有貫際動作領域最外周之第2、、盖、;巨 弟2溝朱開口部6a的開口寬度 大於Μ際動作領域内之第1溝準間 再木開口部6之開口寬度之圖 案的遮罩進行曝光。具體而言，假 攸&弟1溝渠開口部6為 〇·5 // m左右，則第2溝渠開口部 1 oa則為1.0# m左右。另 外，弟2溝渠形成第2溝渠開口部6a，值亡 、 1 ，俾充分接近P+型 領域4a近。亦即，使第2溝渠開 木開口 4 6a與P +型領域4a 的間隔距離W2，比實際動作領域m〇sfet的單元節距， 亦即第1溝渠開口部6彼此間或是第】、、备 '&牙i屏渠開口部6與第 2溝渠開口部6a間的間隔距離wi短。 ^ 在第5圖中，係以CVD氧化腺$盔、命贸 兀胰5為遮罩並藉由CF系 或HBr系氣體蝕刻第i、第2溝渠 什木同口邵6、6a之矽半導 體基板，以形成溝渠7、7a。此時，如前述一般因最外周 315154 18 1236152 之開口寬度較寬，故會形成比第！溝渠7更深之第2溝渠 7 a。亦即 人的姓刻會形成兩種深度不同的溝渠7、7 a。 藉此，在之後的步驟中於溝渠内埋設閘極電極Η時，可緩 和實際動作領域最外周之間搞婆 ’ ^閘極電極（溝渠7a)底部邊緣的 場集中現象。 一般而言，如欲形成深度不同的溝渠必須增加用以 變更勉刻條件等之步驟，本發明中係藉由使用變更開口寬 度的遮罩而在同一步驟φ n 士 〆哪T冋日守形成珠度不同的溝渠。亦 即，只要變更溝渠蝕刻 庶7立丨m 4、， J W &卓圖案，便可利用先前的製程 來緩和溝渠7a底部邊緣的電場集中現象。 本發明之第3步驟如第6圖所示，係在第！、第2溝 渠7、7a内壁形成閘極絕緣膜。 進行假氧化以在第彳、、箠$ 卜卜、必 罘1溝木7、弟2溝渠7a内壁與通道 層4表面形成氧化膜丨盔 腰U，、圖不），並去除乾蝕刻時所造成的 養虫刻彳貝傷，之後，再葬山 丹精由钱刻去除該氧化膜與CVD氧化膜 5 〇 、 接著王面進行熱氧化，並對應驅動電壓而形成例如 厚度為700A之閘極氧化膜u。 如第7圖辦； 丄心 、 ’、’本备明之第4步驟係形成由埋設於第 乂及第2溝渠之半導體材料所組成之電極。 .ψ…、t雜之多晶矽層附著於全面，植入鼓擴散高濃度 的破以達到g it + + w %率化，並形成閘極電極13。之後在無遮 罩之十月況下蝕刻附英 ,、胃 附者灰王面之多晶矽層，而留下埋設於第 1溝渠7、箆9、、装^ 溝7 a之閘極電極1 3。 315154 19 1236152 如第8圖所示，本發明之第5步驟係在通道層4與第 卜第,2漢渠7'7a相鄰接而形成一導電型源極領域15。 首先’為使基板電位糝定介 钇疋化稭由光阻膜所構成的遮 罩選擇性地以摻雜量丨〇 1 5離子植 丁 m入朋荨雜質，並於形成P + 型主體接觸領域1 4後，去除光阻膜。 之後，使用新的光阻膜，並以可露出預定之源極領域 15與閘極電極13的方式加以覆蓋，並以摻雜量f離子 植入神，而在與第i、第2溝渠7、7a鄰接之通道層4表 面形成N+型源極領域15後，去除光阻膜。 接著藉由CVD法於全面附著BPSG(Boron Phosphorus SiHcate Glass)層，以形成層間絕緣膜μ。之 後’以光阻膜為遮|並至少在閘極電極13上留下層間絕緣 膜16。之後藉由濺鍍裝置使鋁附著於全面，形成與源極領 域1 5以及主體接觸領域丨4接觸之源極電極1 7。 接著，芩照第9圖至第11圖說明本發明之第2實施 例。第2實施例係設置位於第1M0SFET8之外周且第 2M〇SFET8a 之内周的第 3M〇SFET8b。第 3MOSFET8b 係 比第1M0SFET8深，而比第2M〇SFET8a淺。 第9圖係第2實施例之構造。 第2實施例之溝渠型功率MOSFET係由半導體基板 1、2、通道層4、溝渠7、7a、7b、閘極氧化膜丨丨、閘極 電極1 3、源極領域1 5與金屬電極1 7所構成。 另外’由於溝渠7、7a、7b以外的構成要素係與第i 實施例相同，故省略詳細說明。 20 315154 1236152 在半導體基板1上的没極領域2表面設置通道層4， 並在通道層4的周端部設置P +型領域4a。 溝渠7係貫穿通道層4到達汲極領域2，一般而言係 在半導體基板上以格子狀或是條紋狀圖案化。 在本實施形態中，位於實際動作領域最外周附近 數周的溝渠，係設置成越向最外周溝渠深度越深的形態 例如，相較於實際動作領域内的第丨溝渠7，實際動作領 域最外周的第2溝渠7a較深。此外’比第2溝渠乃淺， 而比第1溝渠7深之第3溝渠7b係設在第i溝渠7的外周 且第2溝渠7a的内周.亦即，溝渠係在實際動作領域最外 周附近’即在本實施形態之最外周與其内側之2周中，形 成深度逐漸變深的構造。該等深度之例子可列舉，第丨溝 渠7 =約2.5"m ’第3溝渠7b=約2 5至3#m，第2溝渠 約3# m左右。關於第2溝渠〜，係與第i實施形態相 同，比P +型領域4a淺且與P +型領域钧形成接近配置。 另外’第3溝渠7b的開口寬度係比第丄溝竿7寬， 比第2溝渠〜窄。藉此如後述一般，可同時形成深度不同 =7、”。但是，在此只要溝渠7,比溝渠7深， 且溝渠7a比溝渠7b深即可，亦可在其他步驟中 更 蝕刻條件而形成。 亚在所有的溝渠 化膜11， 1 3係延伸 )，而與設 、， U '土丁汉置閘 並埋設多曰曰曰石夕以形成閘極電⑮13。該閘極 到包圍半導體基板周圍<閘極連結電極阼 於半導體基板上之閘極焊墊電極(無圖示)相 315154 21 1236152 在鄰接溝渠7、7b、7a的通道層4表面植入N+型雜質， 並設置與覆蓋實際動作領域之金屬源極電極1 7相接觸之 源極領域1 5。此外，在鄰接之源極領域1 5間的通道層4 表面，設置p +型雜質擴散領域之主體接觸領域14，以使 基板電位穩定化。 層間絕緣膜1 6為使源極電極1 7與閘極電極丨3間絕 緣，至少必需覆蓋閘極電極1 3，而於溝渠開口部留下其中 一部分。 源極電極17係藉由進行鋁等之濺射而圖案化為所希 望的形狀。並覆蓋實際動作領域上，與源極領域15以及主 體接觸領域1 4相接觸。 藉此，在實際動作領域内可藉由溝渠7配置多數個第 1M0SFET8,第2MOSFET8a則是藉由溝渠7a配置於第 1M0SFET8的外周。另外，在第1M〇SFET8外周且為第 2MOSFET8a内周的部分，配置有比第1M〇SFET8深但是 比苐 2MOSFET8a8 淺的弟 3M〇SFET8b。第 2MOSFET8a 係 比第1電晶體8深，而比P +型領域4a淺。 另外’第2MOSFET8a係與P +型領域4a形成接近配 置。具體而言’第2MOSFET8a與p +型領域4a的間隔距離 W2 ’係設定成比其他M0SFET8之間（或是第ι與第 3M0SFET)的間隔距離W1短。第2M〇SFET8a亦可與p + 型領域4a相接。 在本實施例中，係以虛線表示在關斷狀態下，從施加 驅動電壓Vo時形成反向偏壓的通道層與汲極領域界面的 315154 22 1236152 PN接合處開始擴展的耗盡層。耗盡層的擴展以及耗盡層的 寬度do與先前相π 从 j相同，故從第3電晶體8b之底部邊緣 盡層的距離d3备疳占」 、 θ形成dl>d3>d2。亦即電場強度E3也會形 成E2<E3<E1 ’而得以使電場強度的變化緩和。 藉此可抑制汲極源極間的耐邀惡化，並大幅降低高溫 時所發生之額定值下滑的問題。 另外，本發明之實施例係以MOSFET為例進行說明， 但亦適詩IGBT，並可獲得相同的效果。 ，接著以第1 〇圖、第11圖以及第9圖說明第2實施例 之半導體裝置的势造方、、土 ^ . 、 、 I&方法。另外，除了第2步驟之溝渠形 成步驟以外均血H〗每 弟 員轭例相同，故省略其詳細說明。 第乂驟·係在作為汲極領域2之一導電型半導體美 板表面形成逆導電型通道層4，而在通道層4的周端= 成Ρ +型領域4a。 另外纟IGBT的情況下，若在p +型料導體基板設 N型外延層’再於其上積層N•型外延層以形成集極領域 的話，即可在同一步驟中實施後序步驟。 ★第2步驟：同時形成逐漸往實際動作領域最外周變深 之第1、第3、第2溝渠的步驟（第1〇、JM)。 本步驟係本發明之特徵，係使用溝渠開口部之開口寬 度不同的遮罩在同-步驟内形成第1溝渠7、第2溝準7a、 第3溝渠7b。 /' 在第1〇圖中’係全面藉由CVD法形成膜厚為數千a 之NSG(Non_doped s】】lcate GIass)的cvd氧化膜。之後在 315154 23 1236152 形成溝渠開口部以外 並藉由乾㈣去除，“分覆蓋由光阻膜所形成之遮罩， 露出之溝渠開口部。：=C:、氧化膜’以形成通道領域4 開口部寬度越大則溝.日二右為同一姓刻條件，則可利用 J屏木珠度越深的特性，使用 作領域最外周之第2、、盖$ 使用具有貫際動 圍之第3溝渠開口寬 ：度比配置於其内 口宽产比阶罢认* 大而弟3溝呆開口部6b之開 見又比配置於更内周 之圖案的遮罩進行眠光。“之開口寬度大 早适仃曝先。（6<6b<6a) 具體而言，將笛，、 0 38 〃如 溝渠開口部6的開口寬度例如形成 、 溝渠開口寬度6b开^成ο 5 // m，π 將第2溝準關口卹A y /风，而 、σ a形成0·%// m左右的寬度。另外，形 成弟2溝渠開口部6a侫 卫… 接近。亦即，第m溝"付與Ρ+型領域4a充分 近， 第2溝-開口部6…，領域4a會彼此接 離W1小^距離W21比其他溝渠開口部彼此的間隔距El (—Vo / dll), which can be eased—and the breakdown voltage is worsened, and the source of the fi sink is shown in Figure 2. Figure 2 shows the details of the problem. (VCES-Ta # ^ ± ) ○ ^ A _ The characteristic of k-door circumference k degrees, the dashed line is the characteristic of the prior art. ^ The characteristic of the special proposal. According to the structure of this figure, the surrounding temperature (Ding) is maintained at this%) The temperature characteristics of VCES are positive within the range of 315154 16 1236152 of ^ rated temperature "150 degrees. Compared with the previous ambient temperature above 75 degrees, it will become negative temperature characteristics, its characteristics have been greatly improved. In addition ' In the embodiment of the present invention, the MOSFET is used as an example for explanation, but in the IGBT, the structure of the present invention is also applicable and the same effect can be obtained. Next, the semiconductor device of the present invention will be described using FIG. 3 to FIG. 8. Method. A method for manufacturing a semiconductor device according to the present invention includes the steps of forming a reverse conductive channel layer on the surface of an electrical semiconductor substrate forming a drain region; forming a plurality of trenches penetrating through the channel layer, and simultaneously The outer periphery of the trench is formed more than the first trench Step of deeper second trench; step of forming gate insulating film on inner wall of i and second trench; step of forming electrode composed of semiconductor material buried in second and second trench; in channel layer and second substrate The second trench is adjacent to form a conductive source region. The first step is as shown in FIG. 3, and a channel layer 4 of a reverse conductivity type is formed on the surface of the semiconductor substrate that is a drain region. On-type broken-crystal semiconductor substrate] Laminated Mu-type epitaxial layer ^ forms this pole = 2. At the end of the 4th channel of the predetermined channel layer outside the interstitial action area, the phase "P-type impurity" diffuses to form the P + -type area 4a . Then, after implanting impurities such as Q 0 ”at full doping level, p-type channel layer 4 is diffused to form 1GBT 柃. On the right side of the P + type silicon semiconductor substrate, two layers of N-space are set, and then stacked on top. N, the epitaxial layer forms a collector region, and the subsequent steps are performed in the same step. 315154 17 1236152 As shown in Figures 4 to ^ This & ^ ^, the second step of the present invention is to form a plurality of first, #, and giant ^ 1, .E 4 music through the channel layer, A second trench deeper than the first trench is simultaneously formed on the outer periphery of the first trench. This step is the same as the second trench 7a in the same + 'and the second trench 7a. -In the fourth figure with different depths formed in the step, the NSG (Non-doped Silicatp η, iicateGlassw CVD oxide film 5 with a thickness of thousands) is formed by CVD. Then, the trench openings 26 and 26 are formed. The part is covered with a mask formed by a photoresist film, and part of the CVD oxide film 5 is removed by dry etching to form a trench opening portion exposed in the channel area 4 '6a At this time, if the same etching conditions are used, the opening is used The larger the width of the part is, the more the grooves are more ice-cold, and the 2nd, the cover, which has the outermost circumference of the inter-action area, is used. The mask of the pattern of the opening width of the 1 trench quasi-wooden opening 6 is exposed. Specifically, if the opening 1 of the trench 1 is about 0.5 m //, the second trench opening 1 oa is about 1.0 # m. In addition, the second ditch forms the second ditch opening 6a, which is close to the P + type area 4a. That is, the second ditch opens the wooden opening 4 6a and P +. The separation distance W2 of the type area 4a is larger than the unit of the actual operation area m〇sfet The pitch, that is, the first trench openings 6 are each other or the first], and the distance between the second trench opening 6a and the second trench opening 6a is short. ^ In FIG. 5 The silicon semiconductor substrates are etched with CVD oxide gland, helmet 5 and pancreatic pancreas 5 and are etched by CF or HBr series gas. The silicon semiconductor substrates of the 6th and 6th channels of Shimu Tongkou are formed to form trench 7 7a. At this time, as mentioned above, because the opening width of the outermost periphery 315154 18 1236152 is wider, a second trench 7a which is deeper than the first! Trench 7 will be formed. That is, a person's last name will form two different depths. Channels 7 and 7a. With this, when the gate electrode Η is buried in the channel in the subsequent steps, the field concentration phenomenon at the bottom edge of the gate electrode (channel 7a) can be alleviated. In general, if you want to form trenches with different depths, you must add steps to change the engraving conditions. In the present invention, by using a mask that changes the width of the opening, in the same step φ n Trenches with different sphericity are formed. That is, as long as the trench etch is changed, 7 m, m, J W & Zhuo pattern can use the previous process to alleviate the electric field concentration phenomenon at the bottom edge of the trench 7a. As shown in Figure 6, the third step of the present invention is to form a gate on the inner wall of the second and seventh trenches 7 and 7a. Electrode insulation film. False oxidation is performed to form an oxide film on the inner wall of the first, second, and seventh trenches and the surface of the channel layer 4 (helmet waist U, not shown), and removed Insect engraved shellfish wounds caused by dry etching. After that, the salvia miltiorrhiza was removed by money engraving to remove the oxide film and CVD oxide film 50. Then the king surface was thermally oxidized and formed into a thickness of 700 A according to the driving voltage, for example. Of the gate oxide film u. As shown in Figure 7; the fourth step of 丄, ’, and 本 is prepared to form an electrode composed of a semiconductor material buried in the 乂 and 2 trenches. The polycrystalline silicon layer of .ψ, t is attached to the whole surface, and the implanted drum diffuses a high-concentration break to achieve the g it + + w% ratio, and forms the gate electrode 13. After that, the polycrystalline silicon layer of Fu Ying, the stomach king's gray king surface was etched under the unmasked October condition, and the gate electrode buried in the first trench 7, 箆 9, and ^ trench 7 a was left 1 3 . 315154 19 1236152 As shown in FIG. 8, the fifth step of the present invention is to form a conductive source region 15 on the channel layer 4 adjacent to the second and second channels 7'7a. First, in order to determine the substrate potential, a mask made of a yttrium hafnium straw made of a photoresist film is selectively doped at a doping amount of 0.15 ions, which is then implanted into a net impurity, and is contacted with a P + -type body. After field 1 4, remove the photoresist film. After that, a new photoresist film is used and covered so that the predetermined source region 15 and the gate electrode 13 are exposed, and is implanted into the god with a doping amount f ion. After the N + -type source region 15 is formed on the surface of the channel layer 4 adjacent to 7a, the photoresist film is removed. Then, a BPSG (Boron Phosphorus SiHcate Glass) layer is fully adhered by CVD to form an interlayer insulating film μ. After that, the photoresist film is used as a mask | and at least the interlayer insulating film 16 is left on the gate electrode 13. After that, aluminum is adhered to the entire surface by a sputtering device to form source electrodes 17 in contact with the source region 15 and the main body contact region 4. Next, a second embodiment of the present invention will be described with reference to Figs. 9 to 11. The second embodiment is provided with a 3MMOSFET 8b located outside the 1MMOSFET8 and an inner circumference of the 2MOSFET8a. The third MOSFET 8b is deeper than the first MOSFET 8a and shallower than the second MOSFET 8a. Fig. 9 shows the structure of the second embodiment. The trench-type power MOSFET of the second embodiment is composed of a semiconductor substrate 1, 2, a channel layer 4, a trench 7, 7a, 7b, a gate oxide film, a gate electrode 1, 3, a source region 15, and a metal electrode 1. 7 composition. In addition, since the constituent elements other than the trenches 7, 7a, and 7b are the same as those of the i-th embodiment, detailed description is omitted. 20 315154 1236152 A channel layer 4 is provided on the surface of the non-polar region 2 on the semiconductor substrate 1, and a P + type region 4a is provided on the peripheral end portion of the channel layer 4. The trench 7 passes through the channel layer 4 and reaches the drain region 2. Generally, the trench 7 is patterned on a semiconductor substrate in a grid or stripe pattern. In this embodiment, the trenches located several weeks near the outermost periphery of the actual action area are arranged in a form where the depth of the trench is deeper toward the outermost periphery. For example, compared to the seventh trench in the actual action area, the actual action area is the most The second ditch 7a on the periphery is deep. In addition, 'the trench is shallower than the second trench, and the third trench 7b deeper than the first trench 7 is provided on the outer periphery of the i-th trench 7 and the inner periphery of the second trench 7a. That is, the trench is the outermost periphery of the actual operation area. In the vicinity, that is, a structure that gradually becomes deeper in the outermost periphery and the inner two weeks of this embodiment. Examples of such depths can be enumerated, the first trench 7 = about 2.5 " m ', the third trench 7b = about 25 to 3 # m, and the second trench about 3 # m. The second trench ˜ is the same as the i-th embodiment in that it is shallower than the P + type field 4a and is close to the P + type field. In addition, the opening width of the third trench 7b is wider than that of the second trench 7 and narrower than that of the second trench 7b. As a result, as described later, it is possible to form different depths at the same time = 7, ". However, as long as the trench 7 is deeper than the trench 7 and the trench 7a is deeper than the trench 7b, it can also be formed in other steps under more etching conditions. (All of the trenching films 11 and 13 are extended in all of the trenching membranes), and the U, T, U, Dingdinghan gates and buryes Shi Xi to form the gate electrode 13. This gate is to surround the semiconductor substrate. Phase of the gate pad electrode (not shown) surrounding the gate connection electrode on the semiconductor substrate 315154 21 1236152 N + type impurities are implanted on the surface of the channel layer 4 adjacent to the trenches 7, 7b, 7a, and set and covered In the actual operation area, the metal source electrode 17 is in contact with the source area 15. In addition, on the surface of the channel layer 4 between the adjacent source areas 15, a main contact area 14 in the p + -type impurity diffusion area is provided. The substrate potential is stabilized. In order to insulate the source electrode 17 from the gate electrode 3, the interlayer insulating film 16 must cover at least the gate electrode 13 and leave a part of the trench opening. Source electrode 17 Is patterned by sputtering of aluminum, etc. The desired shape covers the actual operation area and contacts the source area 15 and the main body contact area 14. This allows the first 7MOSFET 8 and the second MOSFET 8a to be arranged in the actual operation area through the trench 7. The trench 7a is disposed on the outer periphery of the first MOSFET 8. The outer periphery of the first MOSFET 8 and the inner periphery of the second MOSFET 8a are provided with a younger 3 MOSFET 8b that is deeper than the first MOSFET 8 but shallower than the MOSFET2MOSFET 8a8. The second MOSFET 8a is the first 1 transistor 8 is deeper and shallower than P + -type region 4a. In addition, the second MOSFET 8a is in close proximity to P + -type region 4a. Specifically, the distance between the second MOSFET 8a and p + -type region 4a is set to W2. It is shorter than the distance W1 between other MOSFETs 8 (or ι and 3 MOSFETs). The 2 MOSFET 8a can also be connected to the p + -type field 4a. In this embodiment, it is indicated by a dotted line in the off state , The depletion layer that starts to expand at the 315154 22 1236152 PN junction that forms the reverse biased channel layer and drain domain interface when the driving voltage Vo is applied. The expansion of the depletion layer and the width of the depletion layer do are the same as the previous phase π Same from j Therefore, to make the distance d3 from the bottom edge of the third transistor 8b Preparation rickets accounted layer ", θ formed dl > d3 > d2. That is, the electric field strength E3 also forms E2 < E3 < E1 ', so that changes in the electric field strength can be eased. This can suppress the deterioration of the resistance between the drain and the source, and greatly reduce the problem of the rating drop that occurs at high temperatures. In addition, the embodiment of the present invention is described by taking a MOSFET as an example, but it is also suitable for an IGBT, and the same effect can be obtained. Next, the semiconductor device according to the second embodiment will be described with reference to FIG. 10, FIG. 11 and FIG. 9, and I & In addition, except for the ditch formation step of the second step, the uniform blood H is the same for each member, so the detailed description is omitted. The first step is to form a reverse-conductivity-type channel layer 4 on the surface of the conductive semiconductor plate, which is one of the drain regions 2, and to form a P + -type region 4a at the peripheral end of the channel layer 4. In the case of IGBT, if an N-type epitaxial layer is provided on the p + -type conductor substrate and an N • -type epitaxial layer is laminated thereon to form a collector region, subsequent steps can be performed in the same step. ★ Step 2: Steps (No. 10, JM) of forming the first, third, and second ditches that gradually deepen toward the outermost periphery of the actual action area. This step is a feature of the present invention, and the first trench 7, the second trench 7a, and the third trench 7b are formed in the same step by using masks having different opening widths of the trench openings. / 'In Fig. 10', a cvd oxide film with NSG (Non_doped s]] lcate GIass with a film thickness of several thousand a is formed by a CVD method. After that, 315154 23 1236152 was formed outside the trench opening and removed by drying. "Sub-cover the mask formed by the photoresist film and expose the trench opening .: = C :, oxide film 'to form the channel area 4 opening The larger the width of the part, the more the groove. The second and right are the same name, and the deeper the degree of J screen wood can be used, it is used as the second outermost area of the field, and the third is the third one with the continuous range. The width of the trench opening: the width is greater than the width of the inner opening. The opening of the opening 3b of the ditch 3 is more sleepy than the mask arranged on the inner periphery. "The width of the opening It is suitable to be exposed early in the morning. (6 < 6b < 6a) Specifically, the opening width of the groove opening portion 6 is formed, for example, the opening width of the groove opening portion 6 is formed, and the opening width of the groove opening portion 6b is opened to ο 5 // m. A y / wind, and σ a form a width of about 0 ·% // m. In addition, the opening 2a of the ditch 2a is formed close to the guard. That is, the m-th trench " is provided with the P + -type field 4a is sufficiently close, the second trench-opening 6 ..., the field 4a will be closer to each other from W1, and the distance W21 will be smaller than the interval between the openings of other trenches.
/、在第11圖中’係以CVD氧化膜作為遮罩，並利用CF 6手b 乂 t ΗΒΓ系氣體對第1、第2、第3溝渠開口部6、6a、 7 7夕半導體基板進行乾蝕刻，同時形成深度不同的溝渠 合/ 7b。此時，如前述—般，因開口寬度會逐漸變寬， ;巨-成比第1 /冓* 7更深的第3溝渠7b，以及比第3溝 :?更深的第2溝渠7a。亦即，可以一次的蝕刻形成3/ In Figure 11, 'The CVD oxide film is used as a mask, and the CF substrate bt ΗΒΓ system gas is used for the semiconductor substrates 6, 6a, 7 and 6 of the trench openings 1, 6 and 7. Dry etching, simultaneously forming trenches with different depths / 7b. At this time, as mentioned above, the width of the opening will gradually become wider; the third trench 7b which is deeper than the first / 冓 * 7 and the second trench 7a which is deeper than the third trench:? That is, it can be formed in one etching 3
又不同的溝渠7、7a、7b。之後，如在溝渠埋設閘極 冤極 1 3 B ^ P可使貫際動作領域最外周的閘極電極（溝渠7a) 底部邊緣的電場集中變化緩和。 315154 24 1236152 ^ 般而言’如欲形成深度不同的溝渠，必須增加用以 :更蝕刻條件等之步驟，但是在本發明中係藉由階段性地 矣侣小開Q官玲： 1 + 見度 而在同一步驟中同時形成深度不同的溝 ^亦即，可提供一種只要變更溝渠蝕刻的遮罩圖案，即 σ運用先别之製程緩和溝渠7 &底部邊緣之電 導體裝置之製造方法。 的丰 v驟：係全面進行熱氧 ;睹广 ......i N他·實切电縻形成合 、，約700 A之閘極氧化膜11。（參照第ό圖） :4步驟：係形成由埋設於溝渠之多矽晶層所構成戈 甲1極電極13。（參照第7圖） 第5步驟·係在通道層4鄰接溝渠7形成一導 極領域1 5，並形成ρ +型轉 “ 定化。（參照第8圖）⑯接觸《4,以使基板電位穩 全面IT又形成層間絕緣膜16。之後藉由減鍍裝置使紹 觸之j二以形成與源極領幻5以及主體接觸領域Η接 原極電極17,而獲得如第9圖所示之最後構造。 可有:二：=藉由使Μ〇贿的深度形成階段性變化， '·友和電场集中。此日夺，階段性地加深 =M〇SFET8部分的遷移領域係如前述-般，二 使開口部變寬而在同一步驟中形成m p 曰 渠。亦即，可盘务义"形成冰度不同的溝 程來形成，因此在:同，藉由一次的溝渠形成製 此在製程上可階段性地形成到j m 限。但是，立目的芒” r ①成到先娀影的界 的右疋在緩和電場集中，則只需達到第2 貝知例所示之2階段程度即可。 這到弟2 315154 25 1236152 另外，本實施型態係顯示於第1以及第2MOSFET8、 8a之間進行第3MOSFET8b之一周配置的情形，但亦可配 置成複數周。另外，設置成複數周時，第3MOSFET8b之 深度無須全部相同，只要是具有比第1M0SFET8深且比第 2MOSFET8a淺的深度，亦可設置成於其中階段性加深的形 式。 (發明之功效） 根據本發明，第2MOSFET8a之溝渠深度係比第 1M0SFET8深，且與P +型領域4a接近配置，因此可緩和 實際動作領域之周端部之溝渠底部邊緣的電場集中。藉由 抑制電場集中可實現抑制汲極源極間（JGBT則為集極射極 間）之耐壓惡化的半導體裝置。 亦即，可抑制汲極源極間（IGBT則為集極-射極間）的 耐壓惡化，並大幅減少高溫時所產生之額定值下滑的問 題。 另外，根據本製造方法，可在同一蝕刻步驟中同時形 成深度不同的溝渠。亦即，不需增加製造步驟，即可利用 與先前相同的製程緩和底部邊緣的電場集中。亦即，具有 可輕易地提供一種可抑制汲極源極間（IGBT則為集極射極 間）的耐壓惡化，並抑制高溫時所產生之額定值下滑之導體 裝置之製造方法的優點。 另外，係在第1M0SFET8與第2MOSFET8a之間，設 置具有兩FET之間之深度的第3M〇SFET8b，並針對實際 動作領域最外周附近之複數周溝渠進行階段性加深，如此 26 315154 1236152 -來’相較於只將最外周加深的情形，更能夠緩和電場集 :。此製程亦可藉由階段性地將最外周與外周的溝渠開口 見度擴大，@形成在同—溝渠形成步驟中逐漸加深的溝 渠。 【圖式簡單說明】 第1圖係本發明之半導體裝置之剖視圖。 第2圖係本發明之半導體裝置之特性圖。 第3圖係本發明之半導體裝置製造方法之剖視圖。 第4圖係本發明之半導體裝置製造方法之剖視圖。 第5圖係本發明之半導體裝置製造方法之剖視圖。 第6圖係本發明之半導體裝置製造方法之剖視圖。 第7圖係本發明之半導體裝置製造方法之剖視圖。 第8圖係本發明之半導體裝置製造方法之剖視圖。 第9圖係本發明之半導體裝置之刳視圖。 第1 〇圖係本發明之半導體裝置製造方法之剖視圖。 第11圖係本發明之半導體裝置製造方法之剖視圖。 第1 2圖係習知半導體裝置之剎視圖。 第13圖係習知半導體裝置製造方法之剖視圖。 第1 4圖係習知半導體裝置製造方法之剖視圖。 第1 5圖係習知半導體裝置製造方法之剖視圖。 第1 6圖係習知半導體裝置製造方法之剖視圖。 第1 7圖係習知半導體裝置製造方法之剖視圖。 第1 8圖係習知半導體裝置製造方法之剖視圖。 第1 9圖係習知半導體裝置之特性圖。 27 315154 1236152 1、 21 N+型矽晶半導體基板 2、 2 2 沒極領域 4、2 4 通道層 4a、24a P +型領域 5、25 CVD氧化膜 6、6a、6b、26 溝渠開口部 主體接觸領域1 5、 層間絕緣膜 17 27a 7 第1溝渠 7b 第3溝渠 8a 第 2M0SFET 11、3 1 閘極氧化膜 14、34 16 ' 36 27 溝渠 28 MOSFET 3 7 源極電極 7a 第2溝渠 8 第 1M0SFET 8b 第 3M0SFET 13、33 閘極電極 35 源極領域 金屬電極（源極電極） 最外周溝渠 3 2 多晶矽層 315154 28Also different trenches 7, 7a, 7b. After that, if a gate electrode is buried in the trench, 1 3 B ^ P can ease the concentration change of the electric field at the bottom edge of the outermost gate electrode (ditch 7a) in the inter-operation area. 315154 24 1236152 ^ In general, if you want to form trenches with different depths, you must add steps to: more etching conditions, etc., but in the present invention, step by step to open Q Guanling: 1 + see At the same time, trenches with different depths are simultaneously formed in the same step. That is, a method for manufacturing an electrical conductor device for mitigating the bottom edge of the trench 7 & using a separate process can be provided by changing the mask pattern of trench etching. Feng's step V: the thermal oxygen is carried out in full; seeing the wide range of ... ... the actual electrode formation of the gate oxide film, about 700 A. (Refer to the figure): 4 steps: forming a 1-pole electrode 13 composed of a polysilicon layer buried in a trench. (Refer to Fig. 7) Step 5: A conductive region 15 is formed on the channel layer 4 adjacent to the trench 7 and a ρ + type transition is formed. (Refer to Fig. 8) ⑯ contact "4 to make the substrate The potential is stabilized and IT forms an interlayer insulating film 16. Then, the second electrode is formed by a plating reduction device to form the source electrode 17 and the source electrode 17 in contact with the main body, and the result is shown in FIG. 9 The final structure can be: Two: = By making the depth of the M0 bribery form a stepwise change, the 'Youhe electric field is concentrated. Today, the stage is deepened = M0SFET8 part of the migration field is as described above- Generally, the second step is to widen the opening to form a channel in the same step. That is, it can be formed by forming trenches with different ice degrees. Therefore, in the same way, this is done by one trench formation. In the manufacturing process, it can be formed to the jm limit in stages. However, the right awning "r ①" that reaches the boundary of the first shadow is relaxed in the concentration of the electric field, and it only needs to reach the second stage as shown in the second example. Just fine. This is 2 315154 25 1236152 In addition, the present embodiment is shown in the case where the third MOSFET 8b is arranged in one cycle between the first and second MOSFETs 8 and 8a, but it may be arranged in multiple weeks. In addition, when it is set to a plurality of weeks, the depth of the third MOSFET 8b does not need to be all the same, as long as it has a depth deeper than the first MOSFET 8 and shallower than the second MOSFET 8a, it may be set in a stepwise deepening form. (Effect of the Invention) According to the present invention, the trench depth of the second MOSFET 8a is deeper than that of the first MOSFET 8 and is close to the P + -type region 4a. Therefore, the electric field concentration at the bottom edge of the trench at the periphery of the actual operation field can be reduced. By suppressing the concentration of the electric field, a semiconductor device that suppresses deterioration of the breakdown voltage between the drain and source (JGBT is the collector and emitter) can be realized. In other words, it is possible to suppress the deterioration of the withstand voltage between the drain and the source (the collector to the emitter is the IGBT), and to significantly reduce the problem of a drop in the rating caused by the high temperature. In addition, according to this manufacturing method, trenches having different depths can be simultaneously formed in the same etching step. That is, the electric field concentration at the bottom edge can be mitigated using the same process as before without adding manufacturing steps. That is, there is an advantage in that a manufacturing method of a conductor device that can easily suppress a deterioration in withstand voltage between a drain source (an IGBT is a collector and an emitter) and suppress a drop in a rated value generated at a high temperature is provided. . In addition, a 3M SFET8b with a depth between the two FETs is provided between the 1M0SFET8 and the 2MOSFET8a, and the periodical deepening is performed for a plurality of ditches around the outermost periphery of the actual operation area, so 26 315154 1236152-come ' Compared to the case where only the outermost periphery is deepened, the electric field set can be eased more. This process can also expand the visibility of the trench openings on the outermost and outer periphery in stages, and form the trenches that are gradually deepened in the same-ditch formation step. [Brief Description of the Drawings] FIG. 1 is a cross-sectional view of a semiconductor device of the present invention. Fig. 2 is a characteristic diagram of the semiconductor device of the present invention. Fig. 3 is a sectional view of a method for manufacturing a semiconductor device according to the present invention. Fig. 4 is a sectional view of a method for manufacturing a semiconductor device according to the present invention. Fig. 5 is a sectional view of a method for manufacturing a semiconductor device according to the present invention. Fig. 6 is a sectional view of a method for manufacturing a semiconductor device according to the present invention. Fig. 7 is a sectional view of a method for manufacturing a semiconductor device according to the present invention. Fig. 8 is a sectional view of a method for manufacturing a semiconductor device according to the present invention. Fig. 9 is a front view of the semiconductor device of the present invention. FIG. 10 is a cross-sectional view of a method for manufacturing a semiconductor device according to the present invention. Fig. 11 is a sectional view of a method for manufacturing a semiconductor device according to the present invention. Fig. 12 is a view showing a brake of a conventional semiconductor device. FIG. 13 is a cross-sectional view of a conventional method for manufacturing a semiconductor device. FIG. 14 is a sectional view of a conventional method for manufacturing a semiconductor device. FIG. 15 is a cross-sectional view of a conventional method for manufacturing a semiconductor device. FIG. 16 is a cross-sectional view of a conventional method for manufacturing a semiconductor device. FIG. 17 is a cross-sectional view of a conventional method for manufacturing a semiconductor device. FIG. 18 is a sectional view of a conventional method for manufacturing a semiconductor device. FIG. 19 is a characteristic diagram of a conventional semiconductor device. 27 315154 1236152 1, 21 N + type silicon semiconductor substrate 2, 2 2 Non-polar area 4, 2 4 Channel layer 4a, 24a P + type area 5, 25 CVD oxide film 6, 6a, 6b, 26 Trench opening body contact Field 1 5. Interlayer insulation film 17 27a 7 1st trench 7b 3rd trench 8a 2M0SFET 11, 3 1 Gate oxide film 14, 34 16 '36 27 trench 28 MOSFET 3 7 source electrode 7a 2nd trench 8 1M0SFET 8b 3M0SFET 13, 33 Gate electrode 35 Source area metal electrode (source electrode) Outer peripheral trench 3 2 Polycrystalline silicon layer 315154 28