TWI231968B - Methods of fabricating a deep trench capacitor and a dynamic random access memory - Google Patents

Abstract

A method of fabricating a deep trench capacitor is provided. A substrate having a patterned mask layer exposing a deep trench in the substrate thereon is provided. Also, a bottom electrode is formed in the substrate around the bottom of the deep trench, and a capacitor dielectric layer is formed on the surface of the deep trench. A first conductive layer is filled in the bottom of the deep trench. A sacrificed layer is formed on the substrate and at least covering the surface of the mask layer. The substrate at the sidewalls of the deep trench exposed by the sacrificed layer and the first conductive layer is partially removed. A collar oxide layer is formed on the sidewalls of the deep trench exposed by the first conductive layer. A second conductive layer and a third conductive layer covering the second conductive layer are formed in the deep trench sequentially.

Description

1231968 V. Description of the invention (1) '-[Technical field to which the invention belongs] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a deep trench capacitor (Deep Trench Capacitor) and dynamic random storage. 1. memory access

Memory, DRAM). [Prior technology] /: f conductor enters, and the sub-micron (Deep Sub-Micron) process L2 L t 3 gradually shrinks' to the previous dynamic random access memory: structure 1, which means that it represents a capacitor Space is getting smaller and smaller. Another ^ T i a 2 Ϊ 5 application software is gradually growing, so the required memory ί: t ϊ ί is getting bigger and bigger. For such a small size, but the memory capacity needs to be shown as follows: The method of manufacturing capacitors of the previous dynamic random access memory must be changed to meet the trend. Dynamic random access memory can be mainly divided into two according to the structure of its capacitor. One of them is a random access memory with a stack capacitor, and the other is a deep trench capacitor with a deep trench capacitor. ) Of dynamic random access memory. However, regardless of the form of the dynamic random access memory, in the case of shrinking semiconductor devices, more and more difficulties are encountered in the manufacturing process. & Fig. 1D is a schematic cross-sectional view illustrating a manufacturing process of a conventional machine access memory with a deep trench capacitor. Please refer to FIG. VII. The manufacturing method is to first provide a substrate 100, and the surface of the substrate 100 is sequentially formed with a patterned osmium layer 102 and a mask layer 104. Next, using patterning

Page 7 1231968 V. Description of the Invention (2) The cushion layer 102 and the mask layer 104 are used as an etching mask to form a deep trench 106 in the substrate 100. Then, a lower electrode 108 is formed in the substrate 100 at the bottom of the deep trench 106, and a capacitive dielectric layer 1 10 and a polycrystalline silicon layer 1 12 are sequentially formed at the bottom of the deep trench 100. After that, a collar oxide layer 114 is formed on the surface of the mask layer 104 and the deep trench 106 not covered by the polycrystalline silicon layer 112. Next, please refer to FIG. 1B, perform an anisotropic silver engraving process, remove the collar oxide layer 1 1 4 on the top of the mask layer 104 and the polycrystalline silicon layer 1 12, and leave only the deep trench 1 〇 The collar oxide layer 11 4 a on the 6 side wall. Next, a deep polysilicon layer η 6 is filled in the deep trench 10 6. Then, referring to FIG. 1C, the polycrystalline silicon layer 丨 6 outside the deep trench 10 106 and a portion located in the deep trench 10 6 is removed to form a polycrystalline silicon layer 1 6a. Thereafter, the collar oxide layer 14a which is not covered by the polycrystalline silicon layer 116a is removed to form the collar oxide layer 14b. Next, a polycrystalline silicon layer 1 1 8 is filled in the deep trench 10 06, wherein the polycrystalline silicon layers 112, 116a, and 118 are electrically connected to each other to serve as the upper electrode of the capacitor. Next, referring to FIG. 1D, a shallow trench isolation structure process is performed to form a shallow trench isolation structure in the substrate 100 adjacent to the polycrystalline silicon layer 118, and to form a polycrystalline silicon layer 118a and a shallow trench isolation structure 122. The system defines the active area. At the same time, the thermal process in the process of forming the shallow trench isolation structure will diffuse the dopants in the polycrystalline silicon layer 118a to the substrate 100, and form a buried doped band 120 (Buried Strap, BS). After removing the pad layer 102 and the mask layer 104, an active element 124 is formed on the substrate 100 in the active region, and the active element 124 is composed of the gate structure 126, the source region 128a, and the electrode. Region 128b, wherein the drain region usb is formed by a buried doped band

13237twf.ptd Page 8 1231968 V. Description of the invention (3) 120 is electrically connected to the upper electrode. However, using the dynamic random access memory obtained by the above method,

The buried doped band 120, the lower electrode 108, the polycrystalline silicon layer 116, and the collar oxide layer 114b form a vertical parasitic electrical crystal in the substrate 100. This parasitic transistor system has the same function as a general transistor. When the input voltage is greater than the threshold voltage (Threshold Vo It age, Vt) of the parasitic transistor, the parasitic transistor will be turned on and the leakage current of the memory element will be generated. problem. In addition, it is known that in order to prevent the parasitic transistor from being turned on, the collar oxide layer of the parasitic transistor must be made larger than a certain length and thickness in order to make it have a sufficiently large initial voltage value. However, the above-mentioned restrictions on the length and thickness of the collar oxide layer often limit the storage capacitance and impedance performance of deep trench capacitors. [Summary of the Invention] In view of this, an object of the present invention is to provide a method for manufacturing a deep trench capacitor, so as to improve the storage efficiency of the deep trench capacitor. Another object of the present invention is to provide a method for manufacturing a dynamic random access memory, so as to increase the initial voltage value of a parasitic transistor in the dynamic random access memory to prevent the problem of leakage current. The invention provides a method for manufacturing a dynamic random access memory. This method first provides a substrate, and a patterned mask layer has been formed on the substrate to expose a deep trench in the substrate. A lower electrode is formed in the substrate at the bottom of the trench, and a capacitor dielectric layer is formed on the surface of the deep trench. Then, a first conductive layer is filled in the bottom of the deep trench. Then, a sacrificial layer is formed on the substrate, and the sacrificial layer covers at least the cover layer

13237twf.ptd Page 9 1231968 V. Description of the invention (4) The surface, and the sacrificial layer has a different etching selection ratio from the substrate. Thereafter, a portion of the thickness of the substrate located at the sidewall of the deep trench and not covered by the sacrificial layer and the first conductive layer is removed. Next, a collar oxide layer is formed on the side wall of the deep trench that is not covered by the first conductive layer. Then, a second conductive layer is filled in the deep trench to cover the first conductive layer. Then, a part of the collar oxide layer and the second conductive layer in the deep trench are removed, so that the upper surfaces of the collar oxide layer and the second conductive layer are lower than the upper surface of the substrate. Then, a third conductive layer is filled in the deep trench to cover the second conductive layer, wherein the first conductive layer, the second conductive layer and the third conductive layer are used together as the upper electrode. Then, the mask layer is removed. Then, an active element is formed on the substrate, and the active element is composed of a gate structure, a source region, and a drain region, wherein the drain region is electrically connected to the upper electrode. Since the present invention has partially removed the thickness of the substrate located at the side wall of the deep trench and not covered by the sacrificial layer and the first conductive layer, a thicker collar oxide layer can be formed at the side wall there, thereby improving the dynamic random storage. The initial voltage value of the parasitic transistor in the memory is taken to solve the problem of conventional leakage current. In addition, when the conductive layer is filled in later, since the height-to-width ratio of the conductive layer will not increase due to the thickening of the collar oxide layer, the conductive layer can also completely fill the deep trench. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, preferred embodiments are described below in detail with the accompanying drawings, as follows. [Embodiment] FIGS. 2A to 2F are schematic cross-sectional views illustrating a manufacturing process of a dynamic random access memory according to a preferred embodiment of the present invention. Please refer to Figure 2 A,

13237twf.ptd Page 10 1231968 V. Description of the invention (5) The manufacturing method of the dynamic random access memory is to first provide a substrate 2 007 and a patterned mask layer 2 0 4 has been formed on the substrate 200. In order to expose the position = deep trench 20 in the substrate 200, the material of the mask layer 204 is, for example, gasification, and the formation method is, for example, chemical vapor deposition (Chemical Vapor Deposition, CVD) process. In a preferred embodiment, 'before forming the mask layer 204, the method further includes forming a stack on the substrate 2000, and the material of the stack layer 200 is, for example, oxidized stone. The method is, for example, an oxidation process. In addition, a method for forming the cushion layer 200 and the cover layer 204 is, for example, to comprehensively form a cushion layer go? On the substrate 2000, and then to form the cover layer 204 on the substrate, and then to cover the cover. The curtain layer 2 04 and the cushion layer 2 02 are formed by micro = H and remaining etching processes. In addition, the method for forming the J stem on the substrate 200 bis is formed by, for example, performing an etching process with a patterned mask layer 20 04 and a cushion layer, and the etching process performed on it is, for example, a dry process. Etching process. 2 0 8. The moxibustion towel forms a D electrode in the substrate 2000 at the bottom of the deep trench 20. If the deep trench is a doped region, for example, the formation method is illustrated. Then, a doped insulating layer is formed on the side wall of the inlet ( The process of 1 in the substrate 200 is not shown, so that the dopants in the doped insulating layer are diffused to those skilled in the art. The detailed production of the lower electrode 2 0 8 is familiar, and then the heart is no longer The dielectric layer 20.1, the layer 204, and the surface of the deep trench 206 form a conformal silicon, silicon nitride, or gas. The material of the capacitor dielectric layer 2 10 is, for example, an oxide, and it is formed. Big & fossils and their combinations or other suitable dielectric methods such as thermal oxidation process, chemical vapor deposition

Page 11

! 231968 5. Invention Description (6) Process or other suitable process. Capacitor trench Λ2 ° 6Γ; "ί into conductive layer 212, covering the part of the mixed KG. / /, 'The material of the layer 212 is, for example, polycrystalline stone, is a suitable conductive material, and its formation method, such as = ML % (ln-Sltu) doped ions, # ;; i = r forms a layer of replacement ... layers (not shown, the top part of the Λ deep trench 2 0 6 is doped with polycrystalline stones) Dry etching process. For example, please refer to FIG. 2B to remove the capacitors that are not covered by the conductive layer 212 and to form a capacitor dielectric layer 210a. The removal method is, for example, dry-type etching. Process or wet etching process. The "n / a" surface of the substrate and the deep trench not covered by the conductive layer 212 = 2 0 6 forms a sacrificial material layer 214 on the surface, and the thickness of the sacrificial material layer 214 gradually decreases at the bottom ZAfjΛ206. Wherein, the material of the sacrificial material layer = 4 includes a material having a different etching selection ratio from the substrate 200, such as silicon oxide, silicon nitride, silicon oxynitride, or other suitable materials, and its formation method In a preferred embodiment, the method for forming the sacrificial material layer 214 is, for example, at 6 ° C. 〇〇〜80 〇〇〇degree, 〇5〜〇. 5〜66.7 Pa) pressure, a low pressure chemical vapor deposition process' formed, wherein the reaction gas used in this process is, for example, tetraethyl stone Tetra-Ethyl-Ortho-Silicate (TEOS). In addition, in another preferred embodiment, the method for forming the sacrificial material layer 2 丨 4 is performed by, for example, a plasma enhanced chemical vapor deposition process, wherein

! 231968 5. Description of the invention (7) Nitrous oxide (n2〇), the reaction gas used in the process is, for example, ammonia-containing gas (NH3) and other gases. CUi according to FIG. 2C 'Remove part of the sacrificial material layer 214, and the sacrificial material layer 214 on the surface of the layer 204 to form a sacrificial extension 14 P. In this step, for the removed sacrificial material; Λ None A special limitation is that it only needs to cover the surface of the mask layer 204 with the sacrificed sacrifices 2-3 to ^. In other words, in a comparative example, the remaining sacrificial layer 214a covers most of the surface of the mask layer 204, and a small portion will cover the side wall of the deep trench 206 (see FIG. 2C). As shown). Alternatively, in another preferred embodiment, the guaranteed sacrificial layer 21 4a covers only the surface of the mask layer 204. In addition, the method of removing the sacrificial material layer 2 1 4 is to perform a wet etching process, and the etchant used in the wet etching process is, for example, dilute hydrogen acid (Diluted HF, DHF) or Buffered hydrofluoric acid (Buffer HF, BHF). Since the thickness of the sacrificial material layer 214 at the top of the deep trench 206 is greater than the thickness of the bottom of the deep trench 206, when the sacrificial material layer 214 in the deep trench 206 has been gradually removed, the surface of the mask layer 204 is still covered with Sacrificial layer 2 1 4 a 〇 Next, part of the thickness of the substrate 200 located at the sidewall of the deep trench 206 and not covered by the sacrificial layer 214 a and the conductive layer 212 is removed to reduce the aspect ratio of the top of the deep trench 206. The method for removing a part of the thickness of the substrate 200 is, for example, a wet etching process, and the etchant used in this process includes ammonium hydroxide (NH4OH) or tetramethyl ammonium hydroxide (Tetra-Methyl-Ammonium Hydroxide). , TMAH). Due to sacrifice

13237twf.ptd Page 13 1231968 V. Description of the invention quot The material of the layer 214a and the material of the substrate 200 have different selection ratios. Therefore, when removing a part of the thickness of the substrate 200, the sacrificial layer 2 丨 can protect the structure it covers. After μ °, please refer to FIG. 2D to remove the sacrificial layer 214a. The method of removing the sacrificial layer 214a includes performing an etching process, which is, for example, a dry etching process Γ followed by a deep trench 20 covered by the conductive layer 2 1 2 A collar oxide layer 2′6 ′ is formed on the 6 sidewall. The material of the collar oxide layer 2 1 6 is, for example, silicon oxide, and the forming method thereof is, for example, firstly performing a chemical vapor deposition process to form a conformal collar oxide material layer (not shown), and then removing it. A deep trench 2 0 6 is formed by a conductive oxide layer on top of the conductive 7 2 1 2. The method for removing a part of the oxide material layer is, for example, performing an anisotropic etching process. 7Yes, because in the above step of removing the thickness of the part of the substrate 200, the height of the deep trenches there has been reduced. Width ratio, so although the thickness of the thinner layer 2 1 6 is formed here, and the height-to-width ratio is increased slightly, but the filling of the conductive layer is not suitable. In addition, in another preferred embodiment, the collar oxide layer 2 1 6 can be directly formed without removing the sacrificial layer 21 after the thickness of the part of K J is 2000. Then, a conductive layer 218, 2 ^ 2 is filled in the deep trench 206, and the conductive layer 218 is electrically connected to the conductive layer 212. Among them, the formation method of the inner material ^ and the 关 目 is related to the conductive layer 212 and the conductive layer 212 is described in detail, so it is not conductive ^ 2. In this step ’, although a thick collar oxide layer is formed on the deep trenches 216, 216, p, +, and #f.

1231968 V. Description of the invention (9) Reduce the aspect ratio of the deep trench there, so when the conductive layer 218 is filled, the conductive layer 2 1 8 can completely fill the deep trench 2 0 6 without being in it. A 孑 L hole is formed. Next, referring to FIG. 2E, the collar oxide layer 216 and the conductive layer 218 in the deep trench 206 are partially removed, so that the upper surface of the collar oxide layer 216a and the conductive layer 218a is lower than the upper surface of the substrate 200. The method for removing a part of the collar oxide layer 2 1 6 and the conductive layer 2 1 8 in the deep trench 206 is, for example, first removing a part of the conductive layer 218 ′ so that the upper surface of the remaining conductive layer 218 & is lower than the substrate 2 〇〇 the upper surface, and then remove the collar oxide layer 216 not covered by the conductive layer 218a 'to form the collar oxide layer 2 1 6 a. Thereafter, a conductive layer 220 is filled in the deep trench 220a to cover the conductive layer 218a ', and the conductive layer 22o is used together with the conductive layers 218 & and 212 as an upper electrode. The material and related formation method of the conductive layer 2 2 0 are similar to those of the conductive layer 2 12, and the conductive layer 2 丨 2 has been described in detail in the foregoing content, so it will not be repeated here. Next, please refer to FIG. 2F 'to perform a shallow trench isolation structure process so that a shallow trench isolation structure 224 is formed in the substrate 200 of the conductive layer 220a adjacent to it, and an active area is defined. At the same time, the thermal process in the process of forming the shallow trench isolation structure will cause the dopants in the conductive layer 220 to diffuse into the substrate 2000 to form the buried doped band 222. Then, after removing the pad layer 202 and the mask layer 204, an active element 226 is formed on the substrate 200 in the active region, and the active element 2 2 6 is composed of the gate structure 2 2 8 and the source region. 23a and drain region 230i), wherein the drain region 230b is electrically connected to the upper electrode electrical layers 220, 218a, and 212) through a buried doped strip 222.

1231968 V. Description of the invention (ίο) Although the dynamic random access memory obtained by the above manufacturing method still exists in the substrate, it is composed of a buried doped band, a lower electrode, an upper electrode and a collar oxide layer. Vertical parasitic transistor. However, since the thickness of the collar oxide layer in the parasitic transistor is thick, the initial voltage value of the parasitic transistor can be increased, thereby solving the problem of leakage current of the conventional memory element. In addition, the present invention can increase the initial voltage value of the parasitic transistor by forming a thicker collar oxide layer to avoid conduction in the channel region (the region of the substrate 200 between the buried doped strip 222 and the lower electrode 208) Therefore, the length of the channel region of this parasitic transistor can be shortened moderately, which will effectively increase the capacitance of the capacitor. In other words, it is possible to increase the contact area between the conductive layer 212 and the capacitor dielectric layer by forming a higher conductive layer 212 in the deep trench, thereby increasing the capacitance of the capacitor. Although the present invention has been disclosed in the preferred embodiment as above, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and retouching without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be determined by the scope of the attached patent application.

13237twf.ptd Page 16 1231968 Brief Description of Drawings Figures 1A to 1D are cross-sectional schematic diagrams of the manufacturing process of a conventional dynamic random access memory. 2A to 2F are schematic cross-sectional views illustrating a manufacturing process of a dynamic random access memory according to a preferred embodiment of the present invention. [Illustration of drawing marks] 1 00, 2 0 0: substrate 1 02, 2 0 2: cushion layer 1 0 4, 2 0 4: mask layer 1 0 6, 2 0 6: deep trench 108, 208: lower electrode 1 1 0, 2 1 0, 2 1 0 a: Inter-gate dielectric layer 1 1 2, 1 1 6 1 6 a 1 1 8 1 1 8 a Polycrystalline silicon layers 114, 114a, 114b, 216 , 216a: collar oxide layer 120, 222: buried doped tape 1 2 2, 2 2 4: shallow trench isolation structure 124, 226: active element 1 2 6, 2 2 8: gate structure 128a, 230a: source Polar regions 128b, 230b: Drain regions 212, 218, 218a, 2 2 0, 2 2 0 a: Conductive layer 2 1 4: Sacrificial material layer 214a: Sacrificial layer

13237twf.ptd Page 17

Claims (1)

1231968 6. Scope of patent application 1. A method for manufacturing a deep trench capacitor, comprising: providing a substrate on which a patterned masking layer has been formed to expose a deep trench in the substrate; and A lower electrode is formed in the substrate at the bottom of the deep trench, and a capacitive dielectric layer is formed on the surface of the deep trench; a first conductive layer is filled in the bottom of the deep trench; a sacrificial layer is formed on the substrate, And the sacrificial layer covers at least the surface of the mask layer, and the sacrificial layer has a different etching selectivity ratio from the substrate; removing the ones located at the sidewall of the deep trench and not covered by the sacrificial layer and the first conductive layer A part of the thickness of the substrate; forming a collar oxide layer on the side wall of the deep trench not covered by the first conductive layer; filling a second conductive layer in the deep trench to cover the first conductive layer; removing the A portion of the collar oxide layer and the second conductive layer in the deep trench, so that the upper surfaces of the collar oxide layer and the second conductive layer are lower than the upper surface of the substrate; and in the deep trench Fill a third conductive layer covering the second conductive layer. 2. The method for manufacturing a deep trench capacitor as described in item 1 of the patent application scope, wherein the sacrificial layer further includes covering an upper sidewall of the deep trench. $ 3. The method for manufacturing a deep trench capacitor as described in item 1 of the patent application, wherein the method for forming the sacrificial layer includes: 13237twf.ptd Page 18 In the military burial ground I, the sacrificial layer surface and the deep surface two sacrificial material layers not covered by the first conductive layer, and the sacrificial layer located on the side wall of the deep trench # I 铭 咚 Γ ^ # 深 沟沟 gradually thinner from the top to the bottom; and two. The sacrificial material layer is divided to retain at least the sacrificial material layer on the cover surface. 1231968 VI. Scope of patent application Drainage materials Curtain layer 4. · If applied, the method for manufacturing deep trench capacitors described in item 3 of the scope of benefit, No.8. The method for forming the sacrificial material layer includes performing a low-pressure chemical vapor deposition process or a plasma enhanced chemical vapor deposition process. 5. The method of manufacturing a deep trench capacitor according to item 3 of the scope of the patent application, wherein the method of removing a part of the sacrificial material layer includes a further etching process. / 6 · The method for manufacturing a deep trench capacitor as described in item 5 of the scope of the patent application, wherein the money engraving agent used in the wet after-etching process includes diluted hydrofluoric acid (Diluted HF, DHF) or buffered hydrofluoric acid. Acid (Buffer HF, BHF) ° 7 · The method for manufacturing a deep trench capacitor as described in item 1 of the patent application scope, wherein the material of the sacrificial layer includes silicon oxide, silicon nitride, or stone nitride. 8 · The method for manufacturing a deep trench capacitor according to item 1 of the scope of patent application, wherein a method of removing a portion of the thickness of the substrate located at the sidewall of the deep trench and not covered by the sacrificial layer and the first conductive layer This includes performing a wet etching process. 9 · The method for manufacturing a deep trench capacitor as described in item 8 of the scope of patent application, wherein the etchant used in the wet etching process includes hydroxide 1231968 VI. Scope of patent application Syrian or tetramethyl nitroxide oxidation record. 1 0. The method for manufacturing a deep trench capacitor as described in item 1 of the patent application scope, further comprising removing the sacrificial layer before forming the collar oxide layer. 11. A method for manufacturing a dynamic random access memory, comprising: providing a substrate on which a patterned mask layer has been formed to expose a deep trench in the substrate, and at the bottom of the deep trench A lower electrode is formed in the substrate, and a capacitive dielectric layer is formed on the surface of the deep trench; a first conductive layer is filled in the bottom of the deep trench; a sacrificial layer is formed on the substrate, and the sacrificial layer Covers at least the surface of the mask layer, and the sacrificial layer has a different etching selectivity ratio from the substrate; removes the portion of the substrate located at the sidewall of the deep trench and not covered by the sacrificial layer and the first conductive layer Thickness; forming a collar oxide layer on the side wall of the deep trench not covered by the first conductive layer; filling a second conductive layer in the deep trench to cover the first conductive layer; removing a portion of the deep trench The collar oxide layer and the second conductive layer so that the upper surfaces of the collar oxide layer and the second conductive layer are lower than the upper surface of the substrate; a third conductive layer is filled in the deep trench, and Covering the second conductive layer, wherein the first conductive layer, the second conductive layer and the third conductive layer are 13237twf.ptd Page 20 1231968 6. The scope of the patent application is commonly used as an upper electrode; the cover layer is removed; and an active element is formed on the substrate. The active element consists of a gate structure and a source electrode. And a drain region, wherein the drain region is electrically connected to the upper electrode. 12. The method for manufacturing a dynamic random access memory according to item 11 of the scope of patent application, wherein the sacrificial layer further includes an upper sidewall covering the deep trench. 1 3. The method for manufacturing a dynamic random access memory as described in item 11 of the scope of patent application, wherein the method for forming the sacrificial layer includes: on the surface of the cover layer and the surface not covered by the first conductive layer. A sacrificial material layer is formed on the surface of the deep trench, and the thickness of the sacrificial material layer on the side wall of the deep trench is gradually thinned from the top to the bottom of the deep trench; and a part of the sacrificial material layer is removed to keep at least the mask located on the cover The sacrificial material layer on the surface of the curtain layer. 14. The method for manufacturing a dynamic random access memory as described in item 13 of the scope of patent application, wherein the method for forming the sacrificial material layer includes performing a low-pressure chemical vapor deposition process or a plasma-enhanced chemical gas. Phase deposition process. 15. The method for manufacturing a dynamic random access memory as described in item 13 of the scope of patent application, wherein the method of removing a portion of the sacrificial material layer includes performing a wet etching process. 16. The method for manufacturing a dynamic random access memory according to item 15 of the scope of patent application, wherein the etchant used in the wet etching process includes 13237twf.ptd Page 21 1231968 6. Scope of patent application Diluted hydrofluoric acid or buffered hydrofluoric acid. 17 · The method for manufacturing a dynamic random access memory as described in item 11 of the scope of patent application, wherein the material of the sacrificial layer includes silicon oxide, silicon nitride, or oxynitride. 1 8. The method for manufacturing a dynamic random access memory according to item 11 of the scope of patent application, wherein the substrate located at the sidewall of the deep trench and not covered by the sacrificial layer and the first conductive layer is removed. Partial thickness methods include performing a wet etching process. 19. The method for manufacturing a dynamic random access memory as described in item 18 of the scope of the patent application, wherein the etchant used in the wet etching process includes a hydroxide or a tetrafluorene hydroxide. 2 0. The method for manufacturing a dynamic random access memory according to item 11 of the scope of patent application, wherein before the formation of the collar oxide layer, the method further includes removing the sacrificial layer. 2 1. The method for manufacturing a dynamic random access memory as described in item 11 of the scope of patent application, wherein after the third conductive layer is filled, a thermal process is further performed to make the third conductive layer The dopant diffuses into the substrate to form a buried doped band (Buried Strap, BS), and the drain region is electrically connected to the upper electrode through the buried doped band. 13237twf.ptd Page 22