TW200539379A - Methods of fabricating a deep trench capacitor and a dynamic random access memory - Google Patents

Abstract

A method of fabricating a deep trench capacitor is provided. A substrate having a patterned mask layer exposing a deep trench in the substrate thereon is provided. Also, a bottom electrode is formed in the substrate around the bottom of the deep trench, and a capacitor dielectric layer is formed on the surface of the deep trench. A first conductive layer is filled in the bottom of the deep trench. A sacrificed layer is formed on the substrate and at least covering the surface of the mask layer. The substrate at the sidewalls of the deep trench exposed by the sacrificed layer and the first conductive layer is partially removed. A collar oxide layer is formed on the sidewalls of the deep trench exposed by the first conductive layer. A second conductive layer and a third conductive layer covering the second conductive layer are formed in the deep trench sequentially.

Description

200539379 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a deep trench capacitor and a dynamic machine access Z ft body. (Dynamie Random Access Memory 'DRAM). [Prior art] During the process of entering and submicron (Deep sub-Micron) of M semiconductor, the size of the το piece is gradually reduced. For the conventional dynamic random access memory structure, it also represents a capacitor. Space is getting smaller and smaller. On the other hand, “Due to the gradual increase of computer application software, the required memory capacity is becoming larger and larger. 1 For such a situation that the size becomes smaller but the memory capacity needs to be increased,” it is not the same as the previous dynamic random access. The manufacturing method of memory capacitors must be changed to meet the needs of the trend. Dynamic random access memory can be divided into two types according to its capacitor structure. One is a dynamic random access memory with a stack capacitor, and the other is a deep trench capacitor. Dynamic random access memory. However, no matter what type of dynamic random access memory is, as the size of semiconductor components is shrinking, more and more difficulties are encountered in the manufacturing process. 1A to 1D are schematic cross-sectional views illustrating a manufacturing process of a conventional dynamic random access memory with a deep trench capacitor. Referring to FIG. 1A, this manufacturing method first provides a substrate 100, and a patterned pad layer 102 and a mask layer 104 are sequentially formed on the surface of the substrate 100. Next, using patterning

13237twf.ptd Page 7 200539379 V. Description of the invention (2) The gauze layer 102 and the mask layer 104 are used as the remaining mask to form a deep trench 106 in the base 100. Then, a lower electrode 108 is formed in the substrate 100 at the bottom of the deep trench 106, and a capacitive dielectric layer 1 10 and a polycrystalline silicon layer 1 12 are sequentially formed at the bottom of the deep trench 106. Thereafter, a collar oxide layer 114 is formed on the surface of the mask layer 104 and the surface of the deep trench 106 not covered by the polycrystalline silicon layer 112. Next, referring to FIG. 1B, an anisotropic etching process is performed to remove the collar oxide layer 1 1 4 on the top of the mask layer 104 and the polycrystalline silicon layer 1 1 2 while leaving only the deep trench 1 0 6 A collar oxide layer 1 1 4a on the sidewall. Then, a deep polysilicon layer 116 is filled in the deep trench 106.

Then, referring to FIG. 1C, the polycrystalline silicon layer 116 outside the deep trench 106 and a portion located in the deep trench 106 is removed to form a polycrystalline silicon layer. Thereafter, the collar oxide layer 114a, which is not covered by the polycrystalline silicon layer 116a, is removed to form the collar oxide layer 1 1 4b. Then, a polycrystalline silicon layer is filled in the deep trench 10 6. The polycrystalline silicon layer 1 1 2, 1 1 6a and 1 1 8 are electrically connected to each other to serve as the upper electrode of the capacitor. . Next, referring to FIG. 1D, a shallow trench isolation structure process is performed to form a shallow trench isolation structure 122 in the substrate 100 adjacent to the polycrystalline silicon layer 118 and to form a polycrystalline silicon layer 1 1 8 a, and the shallow trench isolation structure 1 2 2 Define the active area. At the same time, the thermal process in the process of forming the shallow trench isolation structure will diffuse the dopants in the polycrystalline silicon layer 118a into the substrate 100 to form a buried doped band 120 (Buried Strap, BS). Then, after removing the plutonium layer and the mask layer 104, an active element 124 'is formed on the substrate 100 in the active region, and the active element 124 is formed by the gate structure 126, the source region 128a, and the non-electrode region 128b. Structure, in which the drain region 128b is embedded

200539379 V. Description of the invention (3) 120 is electrically connected to the upper electrode. However, in the dynamic random access memory obtained by the above method, the buried doped band 120, the lower electrode 108, the polycrystalline silicon layer 116, and the collar oxide layer 114b will form a vertical in the substrate 100. A vertical parasitic transistor. This parasitic transistor system has the same function as a general transistor. When the input voltage is greater than the threshold voltage (Threshold Vo It age, Vt) of the parasitic transistor, the parasitic transistor will be turned on and the leakage current of the memory element will be generated. problem. In addition, it is known that in order to prevent the parasitic transistor from being turned on, the collar oxide layer of the parasitic transistor must be made larger than a certain length and thickness in order to make it have a sufficiently large initial voltage value. However, the above-mentioned restrictions on the length and thickness of the collar oxide layer often limit the storage capacitance and impedance performance of deep trench capacitors. _ [Content of the invention] In view of this, the object of the present invention is to provide a method for manufacturing a deep trench capacitor, so as to improve the storage efficiency of the deep trench capacitor. Another object of the present invention is to provide a method for manufacturing a dynamic random access memory, so as to increase the initial voltage value of a parasitic transistor in the dynamic random access memory to prevent the problem of leakage current. The invention provides a method for manufacturing a dynamic random access memory. This method first provides a substrate, and a patterned mask layer has been formed on the substrate to expose a deep trench in the substrate. A lower electrode is formed in the substrate at the bottom of the trench, and a 4-capacitor dielectric layer is formed on the surface of the deep trench. Then, a first conductive layer is filled in the bottom of the deep trench. Then, a sacrificial layer is formed on the substrate, and the sacrificial layer covers at least the cover layer

13237twf.ptd Page 9 200539379 V. Description of the invention (4) The surface, and the sacrificial layer and the substrate have different selection ratios. Thereafter, a portion of the thickness of the substrate located at the sidewall of the deep trench and not covered by the sacrificial layer and the first conductive layer is removed. Next, a collar oxide layer is formed on the side wall of the deep trench that is not covered by the first conductive layer. Then, a second conductive layer is filled in the deep trench to cover the first conductive layer. Then, a part of the collar oxide layer and the second conductive layer in the deep trench are removed, so that the upper surfaces of the collar oxide layer and the second conductive layer are lower than the upper surface of the substrate. Then, a third conductive layer is filled in the deep trench to cover the second conductive layer, wherein the first conductive layer, the second conductive layer and the third conductive layer are used together as the upper electrode. Then, the mask layer is removed. Then, an active element is formed on the substrate, and the active element is composed of a gate structure, a source region, and a non-electrode region, and the drain region is electrically connected to the upper electrode. Since the present invention has first removed a part of the thickness of the substrate located at the side wall of the deep trench and not covered by the sacrificial layer ^ ^, a thicker collar oxide layer can be located in the side there, thereby improving this dynamic random storage. Take the memory $, the initial voltage value of the parasitic transistor to solve the problem of the conventional leakage current ^ and 'when the conductive layer filled in there subsequently' will be oxidized due to the height and width of the place The thickness of the layer is increased, so the conductive layer can also completely fill the deep trench. It can be clearly shown that the above and other objects, features, and advantages of the present invention can be more clearly described as follows. Preferred embodiments are described below in conjunction with the accompanying drawings' for detailed [implementation] (錤 随 ^ ^ 到 到FIG. 2F is a schematic cross-sectional view illustrating a manufacturing process of a mobile memory according to a preferred embodiment of the present invention. Please refer to FIG. 2A.

200539379 V. Description of the invention (5) The manufacturing method of the dynamic random access memory is to first provide a substrate 200, and a patterned mask layer 204 has been formed on the substrate 200 to expose the substrate 200. In the deep trench 206, the material of the cover layer 204 is, for example, silicon nitride, and the formation method thereof is, for example, a Chemical Vapor Deposition (CVD) process. In the example of one-year-old Wei, before the formation of the mask layer 204, it further includes a substrate, a pad, 2 0 2 /, and a material of the pad 2 0 2 is, for example, silicon oxide. It is a thermal oxidation process. In addition, the formation of the cushion layer 200 and the mask layer 204 is, for example, a comprehensive formation of the plutonium layer 200 before the substrate 200, and after the 塾 ΛΛΥ / Λ layer 204: The layer m and the samarium layer 202 are formed by micro, micro, and micro processes. In addition, the 20% method located on the substrate 2 00: 2: is used as a channel. For example, the patterned mask layer 204 and the cushion layer process are formed by a dry / engraving process to form the substrate. The rest of the moment 208. In Λ, the bottom electrode at the bottom of Λ 12 0 6 is used to form the lower electrode. For example, the deep trench 20 is a doped region, and its formation method is exemplified.) Then, the side wall of the j is formed to form a layer of doped. Heterogeneous insulating layer (not shown in the substrate 200, but ^, 1 makes the dopant in the doped insulating layer diffuse to the know of the person skilled in the art; Chengzhi. The detailed production of the lower electrode 208 is familiar: ΐ :, I will not repeat them here. The dielectric layer 2 1 〇. Covers the middle layer of the curtain, 2 = the surface of this deep trench 206 forms a conformal electro-silicon, silicon nitride, nitrogen, and negative π. The material is, for example, an oxidized reading material, and the combination of the second method of forming the method or other suitable dielectric material methods such as thorium for thermal oxidation process, chemical vapor deposition

200539379

5. Description of the invention (6) Process or other suitable processes. Capacitance layer. Deep groove / medium 2. 々: 々 conductive layer 212, which is covered with in-situ doped ion square 々, a method of forming, for example, a layer of dopant on substrate 200 屛 屛 1 deep trench 206 using chemical vapor deposition Outside and deep groove quasi 2, Xi Yue (not shown), remove the layer to form it. The lambda-doped, t-doped polycrystalline stone is subjected to a dry etching process. The method of removing the silicon layer is, for example, introducing a capacitor to remove a capacitor not covered by the conductive layer 212, and performing a dry etching process or a wet etching process. Removal method, for example, Ji Jizhi's formation of a sacrificial material layer 214 on the surface of the cover layer 204 and the surface of the non-conductive sound π J2 0 6 and Atsugi 21-4, which is covered by the sacrificial material θ material layer, gradually moves from the bottom of / Λ22ϊ to the bottom. Thin. Among them, the sacrificial material core and the substrate 20 have different material selection ratios, such as silicon oxide, silicon nitride, silicon oxynitride, or other suitable materials, and the formation method thereof is a preferred implementation. In the example, the method for forming the sacrificial material layer 2 丨 4 is, for example, performing low-pressure chemical vapor deposition at a pressure of 600 to 800 degrees Celsius and 0.05 to 0.5 torr (6.67 to 66.7 Pa). It is formed by a process, wherein the reaction gas used in this process is, for example, Tetra-Ethyl-Ortho-Silicate (TEOS). In addition, in another preferred embodiment, the method for forming the sacrificial material layer 2 1 4 is, for example, a plasma enhanced chemical vapor deposition process.

13237twf.ptd Page 12 200539379 V. Description of the invention (7) Nitrous oxide (n2〇) The reaction gas used in this process is, for example, gas containing sintered ammonia (nh3). Then, referring to FIG. 2C, a part of the sacrificial material layer 2 丨 4 is removed, and the sacrificial material layer 214 located on the surface of the mask layer 20 04 is kept, and is shaped to the animal layer 2 1 4a. In particular, in this step, there is no particular limitation on the thickness of the layer 214, as long as the retained & ^^ layer 21 4a covers at least the surface of the mask layer 204. In other words, in the preferred embodiment, in addition to the majority of the surface of the mask layer 204, the remaining sacrificial layer 21 "will cover the upper side wall of the deep trench 206 (as shown in Figure 2C). (Shown). Alternatively, in another preferred embodiment, the sacrificial layer 21 4a remaining only covers the surface of the mask layer 2 04. In addition, the method for removing a portion of the sacrificial material layer 2 1 4 described above is, for example, It is a wet etching process, and the etchant used in this wet etching process is, for example, diluted hydrofluoric acid (DHF) or buffered hydrofluoric acid (Buffer HF, BHF). Because the sacrificial material layer 214 is The thickness at the top of the deep trench 206 is greater than the thickness at the bottom of the deep trench 206. Therefore, when the sacrificial material layer 214 in the deep trench 206 has been gradually removed, the surface of the mask layer 204 is still covered with the sacrificial layer. 214a 0 Next, remove part of the thickness of the substrate 200 located at the side wall of the deep trench 20 and not covered by the sacrificial layer 214a and the conductive layer 212 to reduce the aspect ratio of the top of the deep trench 206. Among them, the substrate 2 is removed 〇〇 Part of the thickness method is, for example, wet etching And the use of this process the etchant include ammonium hydroxide (NH4OH) or tetramethylammonium hydroxide (Tetra-Methyl-Ammonium Hydroxide, TMAH). Since the sacrificial

13237twf.ptd Page 13 200539379 Description of the invention (8) The material of the layer 2i4a and the material of the substrate 2 0 have different etching selection ratios. Therefore, when removing a part of the thickness of the substrate 2 0, the sacrificial layer "can protect its Structure covered. After that, referring to FIG. 2D, the sacrificial layer 21 ″ is removed. The removal method includes performing an etching process, such as a dry etching process. Subsequently, a collar oxide layer 2 1 6 is formed on the side wall of the deep trench 2 0 6 which is not covered by the conductive layer 2 1 2. The material of the collar oxide layer 2 1 6 is, for example, oxidized stone, and the method of forming the plutonium is, for example, first performing a chemical vapor deposition process to form a collar oxide material layer on the top of the 2 4 2 . The method for removing a part of the collar oxide material layer is, for example, performing an anisotropic etching process. In particular, 'the aspect ratio of the deep trench there has been reduced in the above-mentioned step of removing the thickness of the substrate 200', although a thicker collar oxide layer 216 is formed here, the height and width of the trench are increased slightly Ratio, but will not affect the subsequent filling of the conductive layer. In addition, in another preferred embodiment, after removing part of the thickness of the substrate 200, the collar oxide layer 2 1 6 can be directly formed without removing the sacrificial layer 214a. Then, a conductive layer 218 is filled in the deep trench 206 to cover the conductive layer 212, and the conductive layer 218 is electrically connected to the conductive layer 212. Among them, the material of the conductive layer 218 and the related formation method are similar to the conductive layer gig, and the conductive layer 2 1 2 has been described in detail in the foregoing content, and will not be described again here. In addition, in this step, although a thick collar ^ ^ 216 is formed on the side wall of the deep trench 20 that is not covered by the conductive layer 2 1 2, the thickness is increased by τ in the step of removing the thickness of the substrate 200 described above. Has been

13237twf.ptd Page 14 200539379 V. Description of the invention (9) Reduce the aspect ratio of the deep trench there, so when the conductive layer 218 is filled, the conductive layer 218 can completely fill the deep trench 206 without A hole is formed in it. Next, referring to FIG. 2E, a part of the collar oxide layer 216 and the conductive layer 218 in the deep trench 206 is removed, so that the upper surfaces of the collar oxide layer 216a and the conductive layer 218a are lower than the upper surface of the substrate 200. The method for removing a part of the collar oxide layer 216 and the conductive layer 218 in the deep trench 206 is, for example, first removing a part of the conductive layer 218 so that the upper surface of the remaining conductive layer 21 8a is lower than the upper surface of the substrate 200. After that, the collar oxide layer 216 not covered by the conductive layer 218a is removed to form a collar oxide layer 2 1 6 a.

Thereafter, a conductive layer 220 is filled in the deep trench 220a to cover the conductive layer 218a, and the conductive layer 220 is used as the upper electrode together with the conductive layers 218a and 212. The material and related formation method of the conductive layer 220 are similar to the conductive layer 2 1 2, and the conductive layer 2 丨 2 has been described in detail in the foregoing content, so it will not be repeated here. Next, referring to FIG. 2F, a shallow trench isolation structure process is performed to form a shallow trench isolation structure 224 in the substrate 200 adjacent to the conductive layer 220a, and define an active area. At the same time, the thermal process in the process of forming the shallow trench isolation structure will cause the dopants in the conductive layer 220 to diffuse into the substrate 2000 to form the buried doped band 222. Next, after removing the pad layer 202 and the cover layer 204, an active element 2 2 6 is formed on the substrate 2000 in the active area, and the active element 2 2 6 is formed by the gate structure 2 2 8 The structure of the source region 2 3 0a and the drain region 2 3 0b = the middle drain region 2 3 0b is formed by the buried doped band 2 2 2 and the power-on layers 220, 218a, and 212) Electrical connection. guide

200539379 V. Description of the invention (ίο) Although the dynamic random access memory obtained by the above manufacturing method still exists in the substrate, it is composed of a buried doped tape, a lower electrode, an upper electrode and a collar oxide layer. Vertical parasitic transistor. However, since the thickness of the collar oxide layer in the parasitic transistor is thick, the initial voltage value of the parasitic transistor can be increased, thereby solving the problem of leakage current of the conventional memory element. In addition, the present invention can increase the initial voltage value of the parasitic transistor by forming a thicker collar oxide layer to avoid conduction in the channel region (the region of the substrate 200 between the buried doped strip 222 and the lower electrode 208) Therefore, the length of the channel region of this parasitic transistor can be shortened moderately, which will effectively increase the capacitance of the capacitor. In other words, it is possible to increase the contact area between the conductive layer 212 and the capacitor dielectric layer by forming a higher conductive layer 212 in the deep trench, thereby increasing the capacitance of the capacitor. Although the present invention has been disclosed in the preferred embodiment as above, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and retouching without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be determined by the scope of the attached patent application.

13237twf.ptd Page 16 200539379 Brief Description of Drawings Figures 1A to 1D are schematic cross-sectional views of the manufacturing process of a conventional type of dynamic random access memory. FIGS. 2A to 2F are schematic diagrams of a manufacturing process of a dynamic random access memory according to a preferred embodiment of the present invention. [Schematic mark description] 1 00 > 200 substrate 1 02 \ 202 cushion layer 104 , 204 mask layer 106 ^ 206 deep trench 108 > 208 lower electrode 110 '210, • 21 0 a: inter-gate dielectric layer 112, 116, '11 6 a 118, 1 18 Ά · polycrystalline silicon layer 114, 1 14a > 1 14b,, 21 6 21 6 a: collar oxide layer 120 > 222 buried doped tape 122 ~ 224 shallow trench isolation structure 124, 226 active element 126 ^ 228 gate structure 128a ^ 230 a Regions 128b, 2 3 0 b: Drain region 212 > 218, 21 8 a 220, 220 3 · Conductive layer 2 1 4: sacrificial material layer 214a: sacrificial layer

13237twf.ptd Page 17

Claims (1)

200539379 VI. Application Patent Scope 1. A method for manufacturing a deep trench capacitor, comprising: providing a substrate on which a patterned mask layer has been formed to expose a deep trench in the substrate, and A lower electrode is formed in the substrate at the bottom of the deep trench, and a capacitive dielectric layer is formed on the surface of the deep trench; a first conductive layer is filled in the bottom of the deep trench; a sacrificial layer is formed on the substrate, And the sacrificial layer covers at least the surface of the mask layer, and the sacrificial layer has a different etching selectivity ratio from the substrate; removing the ones located at the sidewall of the deep trench and not covered by the sacrificial layer and the first conductive layer Part of the thickness of the substrate; I forming a collar oxide layer on the side wall of the deep trench not covered by the first conductive layer; filling a second conductive layer in the deep trench to cover the first conductive layer; Remove the collar oxide layer and the second conductive layer in a part of the deep trench, so that the upper surfaces of the collar oxide layer and the second conductive layer are lower than the upper surface of the substrate, and A third conductive layer is filled in the trench to cover the second conductive layer. 2. The method for manufacturing a deep trench capacitor as described in item 1 of the patent application scope, wherein the sacrificial layer further includes covering an upper sidewall of the deep trench. $ 3. The method for manufacturing a deep trench capacitor as described in item 1 of the patent application, wherein the method for forming the sacrificial layer includes: 13237twf.ptd Page 18 200539379 6. The scope of the application for a patent is to form a layer of material on the surface of the cover. The thickness of the surface of the removed portion is sacrificed. 4. If the method is applied, it learns vapor deposition. Etching process 6 · As claimed, its hydrofluoric acid (Dil BHF). 7. If applied, it is siliconized. 8. If the method is applied, the first conductive wet etching method is used. 9. If the method is applied, the sacrifice material on the surface of the curtain layer is divided into the sacrifice material layer. Removal section of the standard. Please request the wet-typed HF in the patent standard. Remove the bit-layer coverage in the patent standard. In the patent, the wet type and the deep trench layer not covered by the first conductive layer, and the sacrificial ^ trench at the sidewall of the deep trench are gradually thinned toward the bottom; and a material layer is provided to keep at least the The method for forming the material layer of the deep trench capacitor described in item 3 of the mask layer 0 includes performing a low-voltage-plasma-reinforced chemical vapor deposition process. The method of manufacturing the deep trench capacitor described in item 3 of the sacrificial material layer includes performing a wet etching process of the deep trench capacitor described in item 5 in which the etchant used includes a diluted 'DHF) Or buffer hydrofluoric acid (Buffer HF, the material for the formation of the deep trench capacitors described in item 1 includes silicon oxide, silicon nitride, or the deep trench capacitors described in item 1) A method for forming a part of the thickness of the side wall of the deep trench without the sacrificial layer and the substrate includes performing an etching process for the deep trench capacitor described in item 8 including an hydroxide 200539379 6. Scope of patent application Ammonium or tetramethylammonium hydroxide. 1 0. The method for manufacturing a deep trench capacitor as described in item 1 of the patent application scope, further comprising removing the sacrificial layer before forming the collar oxide layer. 1 1. A method for manufacturing a dynamic random access memory, comprising: providing a substrate on which a patterned mask layer has been formed to expose a deep trench in the substrate, and in the deep trench A lower electrode is formed in the substrate at the bottom, and a capacitive dielectric layer is formed on the surface of the deep trench; a first conductive layer is filled in the bottom of the deep trench; a sacrificial layer is formed on the substrate, and the sacrificial layer is formed. The layer system covers at least the surface of the mask layer, and the sacrificial layer has a different etching selection ratio from the substrate; removing the substrate located at the side wall of the deep trench and not covered by the sacrificial layer and the first conductive layer Partial thickness; forming a collar oxide layer on the side wall of the deep trench not covered by the first conductive layer; filling a second conductive layer in the deep trench to cover the first conductive layer; removing the deep trench Part of the collar oxide layer and the second conductive layer, so that the upper surfaces of the collar oxide layer and the second conductive layer are lower than the upper surface of the substrate; filling a third conductive layer in the deep trench, Cover the second conductive layer, wherein the first conductive layer, the second conductive layer and the third conductive layer system 13237twf.ptd Page 20 200539379 6. The scope of the patent application is commonly used as an upper electrode to remove the mask layer; and an active element, a structure, a source region and a drain region are formed on the substrate. ~ The active element is electrically connected by an electrode on the gate. In the manufacturing method of the drain region and the 12-item, such as the scope of application for patent application, wherein the sacrificial layer moves the random access memory sidewall. The ruler covers the upper part of the deep trench. 3. The manufacturing method of the js & body as described in the patent application scope, wherein the dynamic random access memory surface formed by the sacrificial layer is formed as a sacrificial material layer and is located in the Use = to move the sacrificial material layer to at least; leave the cut = the sacrificial material layer on the surface of the 3 curtain layer. 1 4 · The manufacturing method of dynamic random access memory as described in item 13 of the scope of patent application, wherein the method of forming the sacrificial material layer includes performing a low pressure chemical vapor deposition process or a plasma enhanced chemistry Vapor deposition process. 1 5. The method for manufacturing a dynamic random access memory as described in item 13 of the scope of the patent application, wherein the method of removing a part of the sacrificial material layer includes performing a wet post-etching process.丨 16 · The method for manufacturing a dynamic random access memory as described in item 15 of the scope of patent application, wherein the etchant used in the wet etching process includes 13237twf.ptd Page 21 200539379 6. Scope of patent application Diluted hydrofluoric acid or buffered hydrofluoric acid. 1 7. The method for manufacturing a dynamic random access memory according to item 11 of the scope of patent application, wherein the material of the sacrificial layer includes silicon oxide, silicon nitride or silicon oxynitride. 1 8. The method for manufacturing a dynamic random access memory according to item 11 of the scope of patent application, wherein the substrate located at the sidewall of the deep trench and not covered by the sacrificial layer and the first conductive layer is removed. Partial thickness methods include performing a wet etching process. 19. The method for manufacturing a dynamic random access memory according to item 18 of the scope of the patent application, wherein the etchant used in the wet etching process includes ammonium hydroxide or tetramethylammonium hydroxide. 2 0. The method for manufacturing a dynamic random access memory according to item 11 of the scope of patent application, wherein before the formation of the collar oxide layer, the method further includes removing the sacrificial layer. 2 1. The method for manufacturing a dynamic random access memory as described in item 11 of the scope of patent application, wherein after the third conductive layer is filled, a thermal process is further performed to make the third conductive layer The dopant diffuses into the substrate to form a buried doped band (Buried Strap, BS), and the electrodeless region is electrically connected to the upper electrode through the buried doped band. 13237twf.ptd Page 22