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TWI225693B - Multi-chips package - Google Patents

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Publication number
TWI225693B
TWI225693B TW092109529A TW92109529A TWI225693B TW I225693 B TWI225693 B TW I225693B TW 092109529 A TW092109529 A TW 092109529A TW 92109529 A TW92109529 A TW 92109529A TW I225693 B TWI225693 B TW I225693B
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Taiwan
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chip
scope
patent application
item
chip package
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TW092109529A
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TW200423326A (en
Inventor
Sung-Fei Wang
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Advanced Semiconductor Eng
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Priority to TW092109529A priority Critical patent/TWI225693B/zh
Priority to US10/747,189 priority patent/US6879031B2/en
Publication of TW200423326A publication Critical patent/TW200423326A/zh
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Publication of TWI225693B publication Critical patent/TWI225693B/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
    • H01L2225/06586—Housing with external bump or bump-like connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06589—Thermal management, e.g. cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Wire Bonding (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Description

1225693
(一）、【發明所屬之技術領域】 本發明是有關於一種多晶片封裝體，特別是有 種能夠防止連接晶片與載板間之凸塊破壞的多晶片封奘 (二）、【先前技術】 隨著微小化以及高運作速度需求的增加，多晶片封裝 體在許多電子裝置越來越吸引人。多晶片封裝體可藉由^ 兩個或兩個以上之晶片組合在單一封裝體中，來提升系統 之運作速度。此外，多晶片封裝體可減少晶片間連接線路 之長度而降低訊號延遲以及存取時間。 最吊見的多晶片封裝體為並排式（side - by - side)多晶 片封裝體’其係將兩個以上之晶片彼此並排地安裝於一共 同載板之主要安裝面。晶片與共同載板上導電線路間之^ 接一般係藉由打線法（wire bonding)達成。然而該並排式 多晶片封裝體之缺點為封裝效率太低，因為該共同載板之 面積會隨著晶片數目的增加而增加。 因此半導體業界開發出一多晶片封裝體之設計（參照 圖1) ’其特徵在於提供一第一晶片110覆晶接合於一具有 一開口122之載板120上表面124，再將一第二晶片130容置 於載板1 2 0之開口 1 2 2中，並與上述之第一晶片丨丨〇覆晶接 合。一般而言’第一晶片11 〇與第二晶片1 3 〇可分別為記憶 晶片及邏輯晶片’如此可將弟一晶片與第二晶片130之 訊號於封裝體内先行整合後，再經由載板1 2 〇下表面1 2 6之
第5頁 1225693 鋒球1 2 8與外界電性連接。如此之封裝體設計不僅能減少封 裝體之厚度，t可提升晶片之運算及傳輸效能。然而，由 於第曰曰片11 〇與載板1 2 0間係以導電凸塊丨6 〇電性連接，而 載板120之熱膨脹係數（約為丨6 χ 1〇_6ppm/ 〇遠大於第一晶 Μ 1 1 Π ^ X ..」. 關 測 試 或 進 行 運 作 時 常 因 接 第 一 晶 片 1 1 〇與載板1 2 0 間 有 鑑 於 此 j 為 避 免 前 述 多 晶 片 封 裝 體 中 之 晶 片 效 能 ( ) [ 發 明 内 容 ] 有 鑑 於 上 述 課 題 5 本 發 裝 體 用 以 避 免 連 接 δ又 置 於 電 凸 塊 之 破 壞 0 緣 是 為 了 達 成 上 述 a 封 裝 體 ， 主 要 包 含 - 載 板 、 加 勁 元 件 與 複 數 個 導 電 凸 塊 塊 覆 晶 接 合 於 載 板 之 上 表 面 開 V 中 且 與 第 — 晶 片 覆 晶 加 勁 元 件 同 時黏 著 於 第 二 晶 於 加 勁 元 件 之 教 $ 膨 脹 係 數 係 之 間 ， 故 能 藉 由 加 勁 元 件 同 限 制 1 以 避 免 連 接 第 一 晶 片 綜 上 所 述 5 本 發 明 之 多 第一晶片 第一晶片 而第"^晶 合。同時 之背面及 於載板與 對載板與 載板之導 片封裝體 、一第 係藉複 片係容 ’利用 載板之 晶片之 第二晶 電凸塊 主要係 目的係提供一種多晶片封 上方之晶片與載板間之導 本發明係提供一種多晶片 一晶片、一 數個導電凸 置於載板之 一導熱膠將 下表面。由 熱膨脹係數 片之熱形變 之破壞。 利用設置於 1225693
㊁板：？面與第二晶片背面之加勁元彳，以提供對載板與 柘夕：带之熱形變限制之能力’以避免連接第-晶片與載 ^導電凸塊之破壞。$外’當第一晶片之厚度較 時’力σ勁元件可選擇其熱膨脹係數較接近載板熱 路：係數之材f。反之，當第一晶片之厚度較薄或尺寸較 二呀，加勁元件可選擇其熱膨脹係數較接近晶片熱膨脹係 数之材質。 (四）、【實施方式】 以下將參照相關圖式，說明依本發明較佳實施例之多籲 晶片封裝體。 圖2係顯示本發明第一較佳實施例之多晶片封裝體。本 發明之多晶片封裝體至少包含一第一晶片21〇、載板22〇、 一第二晶片230、一加勁元件240與複數個第一導電凸塊250 及第二導電凸塊2 6 0。其中，第一晶片2 1 〇係藉複數個第一 導電凸塊250覆晶接合於載板2 2 0之上表面224，而第二晶片 230係容置於載板220之開口222中，且藉由複數個第二導電 凸塊260與第一晶片210覆晶接合。同時，利用一導熱膠270 將加勁元件2 4 0同時黏著於第二晶片2 3 0之背面2 3 2及載板 _ 220之下表面226。再者，可於載板220之開口222中填充一 底膠280用以包覆複數個第一導電凸塊250及第二導電凸塊 260，如此可進一步避免連接載板220與第一晶片210間之第 一導電凸塊2 5 0，因載板220與第一晶片210之熱膨脹係數不， 匹配效應而破壞。此外，該載板22 0之下表面226可設置有
第7頁 1225693 五、發明說明（4) 複數個銲球2 2 8，用以與外界電性導通。 承上所述，當第一晶片210之厚度較大或其尺寸較大 時，加勁元件240可選擇其熱膨脹係數較接近載板220熱膨 脹係數之材質。反之，當第一晶片210之厚度較薄或尺寸較 小時，加勁元件240可選擇其熱膨脹係數較接近晶片熱膨脹 係數之材質。故加勁元件240之熱膨脹係數係介於晶片之熱 膨脹係數與載板2 2 0之熱膨脹係數之間。一般而言，晶片之 熱膨脹係數約4 X 1〇-6ppm/°c，而載板之熱膨脹係數約16 X l(T6ppm/°C。由於加勁元件24 0之熱膨脹係數係介於載板220 與晶片之熱膨脹係數之間，故能藉由加勁元件2 4 0同時對載籲 板220與第二晶片230之熱形變限制，以避免連接第一晶片 210與載板220之第一導電凸塊250之破壞。故加勁元件240 可為一虛晶片，或者該加勁元件2 4 0之材質可包含一銅金屬 或一紹金屬。 接著，請參考圖3，其係顯示本發明第二較佳實施例之 多晶片封裝體。與上述不同的是，可藉一黏著層（導熱膠） 2 72將一散熱片2 9 0設置於載板2 2 0上表面224，由於散熱片 2 9 0與載板2 2 0之熱膨脹係數不同，故可藉由散熱片2 9 0與載 板2 2 0間之熱形變限制，可避免連接第一晶片210與載板22 0鲁 之第一導電凸塊250之破壞。 承上所述，當第一晶片210之厚度較大或其尺寸較大 時’散熱片29 0可選擇其熱膨脹係數較接近載板2 2 0熱膨脹 · 係數之材質。反之，當第一晶片2 1 0之厚度較薄或尺寸較小· 時’散熱片2 9 0可選擇其熱膨脹係數較接近晶片熱膨脹係數
第8頁 1225693 五、發明說明（5) 之材質。故散熱片290之熱膨脹係數亦是介於晶片之熱膨脹 係數與載板220之熱膨脹係數之間。由於散熱片2gQ之熱膨 脹係數係亦是介於載板2 2 0與晶片之熱膨脹係數之間，故除 能藉由加勁元件240同時對載板22 0與第二晶片23 0之熱形變 限制外，更能藉由散熱片290與載板220相互間之熱形變限 制，以進一步避免連接第一晶片21〇與載板22〇之第一導電 凸塊250之破壞。故該散熱片29〇不僅可用以提升封裝體之 散熱效能外，更可用以辅助原有之加勁元件24〇，以加強加
勁兀件240之加勁效果。值得注意的是，該散熱片29〇可為 一環狀金屬（未顯示於圖中）環繞於第一晶片21 〇之週邊設 置，或為一條狀金屬設置於第一晶片之外圍（未顯示於圖 中）。其中，該散熱片290之材質可包含一銅金屬或一鋁金 屬。此外，該散熱片2 9 0亦可為一虛晶片。
另外，如圖4所述，散熱片290,之剖視圖亦可為一蓋 狀，，該散熱片29 0,係具有一晶片連接部291，及支撐部 292’ ，該晶片連接部291，係藉由黏著層（導熱膠）274與第一 晶片210相接合，而支撐部2 92,亦藉由黏著層（導熱膠j276 連接於載板220上，以將第一晶片210容置於蓋狀散埶片 2 9 0’中。當第一晶片210之厚度較大或其尺寸較大時散熱 2 2 9 0’可選擇其熱膨脹係數較接近載板22〇熱膨脹係數之材 貝反之’當第一晶片2 1 0之厚度較薄或尺寸較小時，散熱 片2 9 0’可選擇其熱膨脹係數較接近晶片熱膨脹係數之材 質。故散熱片2 9 0，之熱膨脹係數較佳的亦是介於晶片之熱 膨脹係數與載板2 2 0之熱膨脹係數之間。由於散熱片29〇/之
第9頁 1225693
熱膨脹係數亦疋介於載板22〇與晶片之熱膨脹係數之間，故 除能藉由加勁兀件240同時對載板22〇與第二晶片230之熱形 變限制外，更能藉由散熱片290,與載板22〇相互間之熱形變 限制，以進一步避免連接第一晶片21〇與載板220之第一導 電凸塊2 5 0之破壞。故該散熱片29 0,不僅可用以提升封裝體 之散熱效能外，更可用以辅助原有之加勁元件2 4 〇，以加強 加勁元件240之加勁效果。值得注意的是，該散熱片29〇之 材質可包含一銅金屬或一銘金屬。 於本實施例之詳細說明中所提出之具體的實施例僅為 了易於說明本發明之技術内容，而並非將本發明狹義地限 制於該實施例，因此，在不超出本發明之精神及以下申請 專利範圍之情況，可作種種變化實施。
1225693 圖式簡單說明 (五）、【圖式簡單說明】 圖1為一示意圖，顯示習知一種多晶片封裝體的剖面示 意圖。 圖2為一示意圖，顯示本發明第一較佳實施例之多晶片 封裝體之剖面示意圖。 圖3為一示意圖，顯示本發明第二較佳實施例之多晶片 封裝體之剖面示意圖。 圖4為一示意圖，顯示本發明第三較佳實施例之多晶片 封裝體之剖面示意圖。 元件符號說明 110 、 210 第 220 222 224 226 228 230 晶片 120 122 124 126 128 130 160 240 250 260 270 280 272 載板 開口 載板上表面 載板下表面 鲜球 第二晶片 導電凸塊 加勁元件 第一導電凸塊 第二導電凸塊 274、276 黏著層（導熱膠） 底膠
第11頁 1225693 圖式簡單說明 2 9 0 散熱片 290’ 散熱片 29Γ 晶片連接部 2 9 2’ 支撐部 1·11

Claims (1)

1225693 六、申請專利範圍 1. 一種多晶片封裝體，包含： 一載板，具有一上表面、一下表面及一開口； 一第一晶片’具有一第一主動表面及一第一背面，其中該 第一晶片係藉複數個第一導電凸塊與該載板之該上表面 覆晶接合，且該第一晶片係覆蓋該開口； 一第二晶片，具有一第二主動表面及一第二背面，其中該 第二晶片係藉複數個第二導電凸塊與該第一晶片之該第 一主動表面覆晶接合；以及
一加勁元件，係設置於第二晶片之背面及該載板之該下表 面。 2. 如申請專利範圍第1項所述之多晶片封裝體，其中該加勁 元件之熱膨脹係數係介於該晶片之熱膨脹係數與該載板之 熱膨脹係數之間。 3. 如申請專利範圍第2項所述之多晶片封裝體，其中該晶片 之熱膨脹係數為約4 X 1 0_6 p pm / °C。
4. 如申請專利範圍第2項所述之多晶片封裝體，其中該載板 之熱膨脹係數為約16 X 10_6ppm/ °C。 5.如申請專利範圍第1項所述之多晶片封裝體，更包含一黏 著層，該黏著層係設置於該加勁元件與該第二晶片之該背 面間。
第13頁 1225693 六、申請專利範圍 含 包 更 體 裝 封 片 晶 多 之 述 所 項 面 表 下 該 之 板 我 43— 該 與 件 元 勁 加 該 於 j置 第設 圍係 範層 利著 專黏 請該 申， 如層。 6著間 黏 7·如申請專利範圍第5項所述之多晶片封裝體，其中該黏著 層係為一導熱膠。 8·如申請專利範圍第1項所述之多晶片封裝體，其中該加勁 元件係為一虛晶片。 9.如申請專利範圍第1項所述之多晶片封裝體，其中該加勁 元件之材質係包含銅金屬。 1 0.如申請專利範圍第1項所述之多晶片封裝體，其中該加 勁元件之材質係包含鋁金屬。 11.如申請專利範圍第1項所述之多晶片封裝體，其中更包 含一底膠，該底膠係至少包覆該第一導電凸塊。 1 2.如申請專利範圍第1項所述之多晶片封裝體，其中更包 含一底膠，該底膠係至少包覆該第二導電凸塊。 1 3.如申請專利範圍第1項所述之多晶片封裝體，其中更包
1225693 六、申請專利範圍 含一散熱片設置於載板上。 1 4 ·如申請專利範圍第1 3項所述之多晶片封裝體，其中該散 熱片係為一環狀金屬，並環繞於第一晶片之週邊設置。 1 5 ·如申請專利範圍第1 3項所述之多晶片封裝體，其中該散 熱片係為一條狀金屬並設置於第一晶片之外圍。 1 6 ·如申請專利範圍第1 3項所述之多晶片封裝體，其中該散 熱片之材質係包含銅金屬。 1 7.如申請專利範圍第1 3項所述之多晶片封裝體，其中該散 熱片之材質係包含鋁金屬。 1 8.如申請專利範圍第1 3項所述之多晶片封裝體，其中該散 熱片係為一虛晶片。 1 9.如申請專利範圍第1 3項所述之多晶片封裝體，其中該散 熱片係具有一晶片連接部及一支撐部，該支撐部係與該載 板上表面相連接，且該晶片連接部係與該第一晶片相接 合。 2 0.如申請專利範圍第1 9項所述之多晶片封裝體，更包含一 黏著層，該黏著層係設置於該散熱片之該晶片連接部與該
第15頁 1225693 六、申請專利範圍 第一晶片之該背面間。 2 1 ·如申請專利範圍第1 9項所述之多晶片封裝體，吏包含一 黏著層，該黏著層係設置於該支撐部與該載板上表面間。
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