TWI223447B - Insulation structure of vertical trench transistor and its manufacturing method - Google Patents

Abstract

The present invention is related to a kind of trench type capacitor structure and the manufacturing process. In the invention, an isolation layer is formed on the top end of capacitor in a semiconductor substrate; and the isolation layer is composed of one silicon oxide layer, one nitriding layer and the other silicon oxide layer formed sequentially upward. Therefore, the covering layer in the insulation structure of the invented vertical trench type transistor can have sufficient thickness to sufficiently provide insulation effect without having the phenomenon of tilt or non-uniform thickness. In addition, the capacitor structure in the trench structure can be prevented from being contaminated in the following ion implantation or annealing procedure.

Description

1223447 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to an insulating structure and process of a vertical trench transistor, in particular, it forms a multilayer structure of isolation on the top of a capacitor of a DRAM memory cell. Layer to provide insulation or protection to the capacitor. [Prior technology] The memory cell (memory ce 1 1) of general dynamic random access memory (DRAM) is composed of a metal oxide semiconductor (M0S) transistor connected in series to a capacitor. (capacitor), where the capacitor is the main component of data storage. "At present, due to the increase in DRAM memory capacity requirements, the accompanying cascade standards must be smaller. Therefore, vertical trench transistors (11 A, Q structure) must be adopted. usually

In this type of transistor structure, a cover layer must be formed on top of the capacitor to provide insulation between the transistor and the capacitor. S [Contents of the Invention] "Technical Problems to be Solved" The covering layer in the conventional vertical trench transistor structure is a silicon oxide layer formed by an oxidation method, or a silicon oxide layer deposited by a high-density electrodeposition method. Made up of layers. However, the covering layer achieved by this type of technology often results in uneven thickness distribution on the periphery due to this method, or tends to have a thicker thickness on one side, which causes cracks or short circuits in too thin areas. The invention is based on the lack of an insulating structure and a manufacturing process of a conventional vertical trench transistor.

Page 4 of 1223447 V. Description of the invention (2) "Technical means to solve the problem" About the present invention is an insulating structure and manufacturing process of a vertical trench transistor, in order to actually solve one or even a few of the aforementioned related technologies Is missing. In order to achieve the above-mentioned object, the present invention provides an insulating structure and process of a vertical trench transistor, which is mainly formed by forming an isolation layer on the top of a capacitor in a semiconductor substrate, and the isolation layer is from bottom to top, Formation: a first oxide layer, which is a silicon oxide layer located on the bottom layer of the isolation layer and formed by low pressure chemical vapor deposition (LPCVD) or thermal oxidation; nitriding Layer, which is a silicon nitride layer formed on the first oxide layer by low-pressure chemical vapor deposition; and a second oxide layer, which is reacted by a rapid high temperature process (I n S i Tu Steam Generation, ISSG) A lower oxide layer formed on the nitrided layer, and an oxide layer formed on the lower oxide layer by high density plasma chemical vapor deposition (HDP-CVD) Made up of layers. "Effects on the prior art" Based on the aforementioned insulation structure and process of the vertical trench transistor of the present invention, it can achieve the following functions and effects: 1 · Process of manufacturing the insulation structure of the vertical trench transistor of the present invention In addition, its cover layer can reach a sufficient thickness without the phenomenon of tilt or uneven thickness 'so' can provide a sufficient insulation effect.

I22J447 V. Description of the invention (3) 2 · With the present invention, only + ^ ^ m ^ & 1 To avoid the occurrence of cracks or short-circuits at the periphery of the cover layer, the purpose and function of ^ ^ ^ are further improved by cooperating with the following diagrams-after the description, [Embodiment] A ^ ^ 1 according to the preferred embodiment of the present invention The illustration is explained in further detail. Fig. 1 (f) shows a preferred embodiment of the vertical trench transistor of the present invention. It is mainly a top layer of a capacitor (2) in a semiconductor substrate (1) forming an isolation layer. (3) Composition. The isolation layer (3) described above has a first oxide layer (31), a nitride layer (32), and a second oxide layer (33) from bottom to top, wherein the first oxide layer (31) is A silicon oxide layer formed by low pressure chemical vapor deposition (LPCVD) or thermal oxidation; the vaporized layer (32) is a silicon nitride layer formed by low pressure chemical vapor deposition (LpcVD), and the second oxide layer (3 3) is formed by one of the lower oxide layer (33a) formed by the rapid high temperature treatment reaction (Is SG) and one of the upper emulsified layer (33b) formed by the high-density plasma chemical vapor deposition (0?-(^ 0)). Referring to the first figure, a flow chart of a manufacturing method of a preferred embodiment of an insulating structure of a vertical trench transistor according to the present invention is shown, and its steps are explained in order as follows: Step 100 is the use of low-pressure chemical vapor deposition ( LPCVD) or thermal oxidation, on top of the deep trench capacitor (2) in a substrate (1), and along the deep trench (2))

Page 6 1223447 V. Description of the invention (4) A first oxide layer (3 1) with an appropriate thickness is formed on the inner side wall, as shown in the second (a) diagram > | > ° Step 2 0 0 uses low pressure chemistry Vapor deposition (LPCVD) forms a nitride layer (32) of an appropriate thickness on the inner surface of the first oxide layer (31) produced in the previous step, as shown in the second (b) diagram. Step 3 0 0 uses a rapid high temperature treatment reaction (ISSG) to form a lower oxide layer (33a) of an appropriate thickness on the inner surface of the nitrided layer (32) produced in the previous step, as shown in the second figure (c). . Step 40 0 uses high-density plasma chemical vapor deposition (HDP-CVD) to generate the inner surface of the lower oxide layer (33a) in one step to form an upper oxide layer (33b) with a sidewall thickness less than one of its bottom thickness. As shown in the second (d) figure. Step 5 0 uses a hydrofluoric acid solution (DHF or BHF) to etch the second oxide layer (33), the lower oxide layer (33a), and the upper oxide layer U3b) generated in the previous steps, respectively, until the nitride layer is exposed. (32), and then etch the exposed nitrided layer (32) on the sidewall with a hot phosphoric acid (H3p04) solution ^, until the exposed nitrided layer (32) is removed by 70 and reaches the first oxide layer ( 3 1), as shown in the second (e) figure. The combination of the concentration of the scale acid (H3po4) solution and the temperature described above makes the ratio of the etching rate of 51 t (S 1 N) to the rate of silicon dioxide (S i 02) about 70. Deep ^ V ?, 6 0 0 is etched using hydrofluoric acid solution (1) bite or bhf), until the first oxide layer (31) on it is completely engraved by the last name, and stops, as shown in the first and U diagrams display. a The drawing has two: the preferred embodiment of the present invention, which is not any modification or change of the present invention made by the enterprise, should still include

Page 7 1223447 V. Description of the invention (5) Within the scope of the present invention's intended protection. 1 ·· 1223447 Brief description of the drawings [Simplified description of the drawings] The drawings show specific embodiments of the constituent elements described in this specification, and explain the main purpose of the present invention to improve the understanding of the present invention. . The first figure is a schematic flow chart showing the manufacturing process of the insulating structure of the vertical trench transistor of the present invention. The second (a) to two (f) diagrams are schematic cross-sectional views showing one embodiment of the insulating structure of the vertical trench transistor of the present invention at each stage of the process.

[Description of element symbols] Substrate (1) Capacitor (2) Deep trench (2 1) Isolation layer (3) First oxide layer (3 1) Nitriding layer (3 2) Second oxide layer (33) Under oxide layer (33a )

Upper oxide layer (33b)

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Claims (1)

1223447 VI. Application patent scope 1. An insulating structure of a vertical trench transistor, which is mainly formed by forming an isolation layer on the top of a capacitor in a semiconductor substrate, and the isolation layer includes: a first oxide layer, which Is located at the bottom of the isolation layer; a nitride layer is a silicon nitride layer formed on the first oxide layer; a second oxide layer is a lower oxide layer formed on the nitride layer And an upper oxide layer formed on the lower oxide layer by high-density plasma chemical vapor deposition (HDP-CVD). 2. The insulating structure of the vertical trench transistor according to item 1 of the scope of patent application, wherein the thickness of the sidewall of the upper oxide layer is smaller than the thickness of the bottom thereof. 3. The insulating structure of the vertical trench transistor according to item 1 of the scope of the patent application, wherein the lower oxide layer and the upper oxide layer in the second oxide layer are both silicon dioxide (Si02). 4. The insulating structure of the vertical trench transistor according to item 1 of the patent application scope, wherein the first oxide layer is a silicon oxide layer formed by a low pressure chemical vapor deposition (LPCVD) or a thermal oxidation method. 5. The insulating structure of the vertical trench transistor according to item 1 of the patent application scope, wherein the nitrided layer is formed by low pressure chemical vapor deposition (LPC VD). 6. The insulating structure of the vertical trench transistor according to item 1 of the patent application scope, wherein the second oxide layer is formed by a rapid high temperature treatment reaction (I SSG). 7. A process for manufacturing an insulating structure of a vertical trench transistor, which mainly includes: (1) the use of low pressure chemical vapor deposition (LPCVD) or thermal oxidation on top of a deep trench capacitor in a substrate, and Form a proper thickness along the inner wall of the deep trench Page 10 1223447 6. The first oxide layer in the scope of patent application; (2) the low-pressure chemical vapor deposition is used to form a nitride layer with an appropriate thickness on the inner surface of the first oxide layer produced in the previous step; (3) Utilize fast high temperature processing reaction (I SSG) to form a lower oxide layer with appropriate thickness on the inner surface of the nitrided layer produced in the previous step; (4) Use high density plasma chemical vapor deposition (HDP-CVD) The previous step generates the inner surface of the lower oxide layer to form an upper oxide layer of an appropriate thickness; (5) Use a hydrofluoric acid solution (DHF or BHF) to etch the second oxide layer 'containing the lower oxide layer and the upper oxide layer generated in the previous step, and the nitride layer on the sidewall is exposed to the outside; (6) Use of hot phosphoric acid (H3P04) solution to etch the exposed nitride layer on the sidewall until the exposed nitride layer is completely removed and reaches the first oxide layer; (7) Continue the previous step to use a hydrofluoric acid solution (dhF or BHF) for etching Until the first oxide layer on the sidewall of the deep trench is completely etched and stopped. 8. The manufacturing process of the insulating structure of the vertical trench transistor according to item 7 of the patent application, wherein the thickness of the sidewall of the upper oxide layer is smaller than the thickness of the bottom thereof. 9 · The manufacturing process of the insulating structure of the vertical trench transistor according to item 7 of the scope of the patent application, where the concentration and temperature of the phosphoric acid (H3P04) solution used are superimposed. The ratio is such that the ratio of the etching rate of silicon nitride (S i N) to the etching rate of silicon dioxide (S i 0 2) is about 70. Page 11