CN112447497A - Oxide layer forming method, semiconductor device manufacturing method and semiconductor device - Google Patents
Oxide layer forming method, semiconductor device manufacturing method and semiconductor device Download PDFInfo
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Abstract
本申请涉及半导体技术领域，具体而言，涉及一种氧化层形成方法、半导体器件的制作方法及半导体器件。该氧化层形成方法可包括：提供半导体衬底；基于第一加热温度和第一压力对所述半导体衬底进行第一次热氧化处理，以在所述半导体衬底上形成第一子氧化层；基于第二加热温度和第二压力对所述半导体衬底进行第二次热氧化处理，以在所述第一子氧化层上形成第二子氧化层；其中，所述第二加热温度小于所述第一加热温度，所述第一压力小于或大于所述第二压力。该方案能够提高氧化层的质量和均匀性，以提高半导体器件的性能。
The present application relates to the field of semiconductor technology, and in particular, to a method for forming an oxide layer, a method for fabricating a semiconductor device, and a semiconductor device. The oxide layer forming method may include: providing a semiconductor substrate; subjecting the semiconductor substrate to a first thermal oxidation treatment based on a first heating temperature and a first pressure to form a first sub-oxide layer on the semiconductor substrate performing a second thermal oxidation process on the semiconductor substrate based on a second heating temperature and a second pressure to form a second sub-oxide layer on the first sub-oxide layer; wherein the second heating temperature is less than The first heating temperature and the first pressure are less than or greater than the second pressure. This solution can improve the quality and uniformity of the oxide layer to improve the performance of the semiconductor device.
Description
Technical Field
The application relates to the technical field of semiconductors, in particular to an oxide layer forming method, a semiconductor device manufacturing method and a semiconductor device.
Background
Recently, as the density of very large scale integrated circuits is increasing, the size of semiconductor devices such as DRAM (Dynamic Random Access Memory) will be smaller and smaller, and the thickness of the gate oxide layer is decreasing, and the requirement for the gate oxide layer is higher and higher in order to maintain the function of the semiconductor device, wherein the quality and uniformity of the gate oxide layer are the main factors affecting the performance of the semiconductor device.
It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present application and therefore may include information that does not constitute prior art known to a person of ordinary skill in the art.
Disclosure of Invention
The present application provides an oxide layer forming method, a semiconductor device manufacturing method, and a semiconductor device, which can improve the quality and uniformity of an oxide layer to improve the performance of the semiconductor device.
A first aspect of the present application provides an oxide layer forming method, including:
providing a semiconductor substrate;
performing first thermal oxidation treatment on the semiconductor substrate based on a first heating temperature and a first pressure to form a first sub-oxide layer on the semiconductor substrate;
performing second thermal oxidation treatment on the semiconductor substrate based on a second heating temperature and a second pressure to form a second sub-oxide layer on the first sub-oxide layer;
wherein the second heating temperature is less than the first heating temperature, and the first pressure is less than or greater than the second pressure.
In an exemplary embodiment of the present application, the first heating temperature is 950 ℃ to 1100 ℃; the second heating temperature is 800 ℃ to 950 ℃.
In an exemplary embodiment of the present application, one of the first pressure and the second pressure is 1Torr to 7Torr, and the other is 7Torr to 20 Torr.
In an exemplary embodiment of the present application, a thickness of the first sub-oxide layer is greater than a thickness of the second sub-oxide layer.
In an exemplary embodiment of the present application, a thickness of the first sub oxide layer accounts for 60% to 80% of a sum of thicknesses of the first sub oxide layer and the second sub oxide layer, and a thickness of the second sub oxide layer accounts for 20% to 40% of the sum of thicknesses of the first sub oxide layer and the second sub oxide layer.
In an exemplary embodiment of the present application, the first thermal oxidation treatment and the second thermal oxidation treatment include an in-situ steam oxidation process in which reaction gases include hydrogen and an oxygen-containing gas.
In an exemplary embodiment of the present application, the oxygen-containing gas includes oxygen, nitric oxide gas, or nitrous oxide gas.
In an exemplary embodiment of the present application, the concentration of hydrogen in the reaction gas is 1% to 33%.
A second aspect of the present application provides a method for manufacturing a semiconductor device, including:
providing a semiconductor substrate;
performing first thermal oxidation treatment on the semiconductor substrate based on a first heating temperature and a first pressure to form a first sub-oxide layer on the semiconductor substrate;
performing second thermal oxidation treatment on the semiconductor substrate based on a second heating temperature and a second pressure to form a second sub-oxide layer on the first sub-oxide layer;
forming a semiconductor element on the second sub-oxide layer;
wherein the second heating temperature is less than the first heating temperature, and the first pressure is less than or greater than the second pressure.
The third aspect of the present application provides a semiconductor device manufactured by the above manufacturing method of the semiconductor device.
The technical scheme provided by the application can achieve the following beneficial effects:
according to the oxide layer forming method, the semiconductor device manufacturing method and the semiconductor device, the oxide layer with high quality and high uniformity can be obtained through multiple thermal oxidation treatments under different conditions. Specifically, the first thermal oxidation treatment adopts high temperature to reduce interface trap charges and interface defect state density between the oxide layer and the semiconductor substrate, so that the reliability of the interface between the oxide layer and the semiconductor substrate can be improved, and the quality of the oxide layer is improved; the second thermal oxidation treatment adopts low temperature to reduce the reaction rate so as to prolong the growth time of the subsequent oxide layer, thereby being convenient to control the subsequent oxide layer to meet the requirement and ensuring the uniformity of the oxide layer; in addition, one of the first thermal oxidation treatment and the second thermal oxidation treatment has a higher pressure, and the other one has a lower pressure, so that the profiles of the first sub-oxide layer and the second sub-oxide layer are complementary, and the uniformity of the finally formed oxide layer can be further improved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and together with the description, serve to explain the principles of the application. It is obvious that the drawings in the following description are only some embodiments of the application, and that for a person skilled in the art, other drawings can be derived from them without inventive effort.
Fig. 1 is a flowchart illustrating a method for forming an oxide layer according to an embodiment of the present disclosure;
fig. 2 is a flow chart of a method for fabricating a semiconductor device according to an embodiment of the present application;
FIG. 3 is a schematic diagram after step S100 is completed;
FIG. 4 is a schematic view after step S102 is completed;
FIG. 5 is a schematic view after step S104 is completed;
fig. 6 is a schematic view after completion of step S2061;
fig. 7 is a schematic view after completion of step S2063;
fig. 8 is a schematic structural diagram of a gate oxide layer according to an embodiment of the present application;
FIG. 9 is a graphical representation of interface trapped charge and interface defect state density versus temperature.
Description of reference numerals:
in fig. 3to 8:
10. a semiconductor substrate; 11. a shallow trench isolation structure; 12. a groove; 13. a gate oxide layer; 13a, a first sub-oxide layer; 13b, a second sub-oxide layer; 14. a dielectric layer; 15. a gate layer; 16. and insulating the oxide layer.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus their detailed description will be omitted.
Although relative terms, such as "upper" and "lower," may be used in this specification to describe one element of an icon relative to another, these terms are used in this specification for convenience only, e.g., in accordance with the orientation of the examples described in the figures. It will be appreciated that if the device of the icon were turned upside down, the element described as "upper" would become the element "lower". When a structure is "on" another structure, it may mean that the structure is integrally formed with the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via another structure.
The terms "a," "an," "the," "said" are used to indicate the presence of one or more elements/components/etc.; the terms "comprising" and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. other than the listed elements/components/etc.; the terms "first" and "second", etc. are used merely as labels, and are not limiting on the number of their objects.
Most oxide layers (e.g., gate oxide layers) in semiconductor devices are usually formed by thermal oxidation, and thus, in order to improve the quality and uniformity of the oxide layers, the process conditions of the thermal oxidation, which mainly include pressure conditions and temperature conditions (i.e., temperature compensation values), can be changed, i.e., the quality and uniformity of the oxide layers can be improved by changing the pressure conditions or the temperature conditions. However, when the thickness of the oxide layer becomes thinner and thinner, it is difficult to improve the uniformity of the oxide layer only by adjusting the pressure; the uniformity of the oxide layer is controlled only by adjusting the temperature, which easily causes the difference between the temperature differences of the wafer surface to be too large, namely: the wafer is heated unevenly, so that the wafer is easy to warp, and even more, the interface of the oxide layer is easy to generate defects, thereby reducing the yield.
To solve the above problem, as shown in fig. 1, an embodiment of the present invention provides an oxide layer forming method, which includes:
step S100, providing a semiconductor substrate;
step S102, performing first thermal oxidation treatment on the semiconductor substrate based on a first heating temperature and a first pressure to form a first sub-oxide layer on the semiconductor substrate;
step S104, performing a second thermal oxidation treatment on the semiconductor substrate based on a second heating temperature and a second pressure to form a second sub-oxide layer on the first sub-oxide layer;
wherein the second heating temperature is lower than the first heating temperature, and the first pressure is lower than or greater than the second pressure.
In this embodiment, the oxide layer with high quality and high uniformity can be obtained by performing a plurality of thermal oxidation treatments under different conditions. In detail, the first thermal oxidation process using high temperature can reduce the interface trap charges (Qit) and the interface defect state density (Dit) between the oxide layer and the semiconductor substrate, as shown in fig. 9, thereby improving the reliability of the interface between the oxide layer and the semiconductor substrate and improving the quality of the oxide layer; the second thermal oxidation treatment adopts low temperature to reduce the reaction rate so as to prolong the growth time of the subsequent oxide layer, thereby being convenient to control the subsequent oxide layer to meet the requirement and ensuring the uniformity of the oxide layer; in addition, one of the first thermal oxidation treatment and the second thermal oxidation treatment has a higher pressure, and the other one has a lower pressure, so that the profiles of the first sub-oxide layer and the second sub-oxide layer are complementary, and the uniformity of the finally formed oxide layer can be further improved.
Note that in fig. 9, a solid line indicates Qit as a relation with temperature, and a broken line indicates Dit as a relation with temperature.
The oxide layer forming method described in the embodiments of the present application is explained in detail below with reference to the drawings.
In step S100, a semiconductor substrate is provided. As shown in fig. 3, the semiconductor substrate may include a semiconductor base 10 and a Shallow Trench Isolation (STI) structure formed on the semiconductor base 10, wherein an active region is formed on the semiconductor base 10 between the STI structures 11, the active region may be etched to form a groove 12, and an oxide layer may be formed in the groove 12.
Specifically, the step S100 may include a step S1001, a step S1002, a step S1003 and a step S1004. Wherein:
in step S1001, a semiconductor substrate 10 is provided. For example, the semiconductor substrate 10 may be a silicon substrate.
In step S1002, the semiconductor substrate 10 is etched to form a trench. For example, a CVD (Chemical Vapor Deposition) process may be used to deposit a silicon nitride layer on a silicon substrate, then pattern the silicon nitride layer to form a hard mask, and then etch the silicon substrate to form the trench.
In step S1003, an isolation material is filled into the trench to form the shallow trench isolation structure 11. For example, a CVD process may be used to fill the isolation material in the trench, and the isolation material filled in the trench may be an oxide, such as: silicon oxide for isolation from the silicon substrate; finally, carrying out Planarization treatment by a Chemical Mechanical Planarization (CMP) process, and removing the silicon nitride layer to form the semiconductor substrate with the shallow trench isolation structures, wherein the region between the shallow trench isolation structures in the semiconductor substrate is an active region.
In step S1004, a portion (this portion is an active region) of the semiconductor substrate 10 between the shallow trench isolation structures 11 is etched to form a groove 12, that is: and finishing the manufacture of the whole semiconductor substrate.
As shown in fig. 5, a first sub-oxide layer 13a and a second sub-oxide layer 13b may be formed at the groove 12. The structure of the semiconductor substrate is not limited to the above-described form, and may be adjusted according to actual circumstances.
For example, the oxide layer formed by the first sub-oxide layer 13a and the second sub-oxide layer 13b mentioned in the present embodiment may be a gate oxide layer 13, that is: the oxide layer formed on the semiconductor substrate may be a gate oxide layer 13, and the gate oxide layer 13 may be formed at the groove 12, for example, the gate oxide layer 13 may be a silicon oxide layer.
Based on the foregoing, the oxide layer forming method described in this embodiment may be a gate oxide layer 13 forming method.
In step S102, the semiconductor substrate is subjected to a first thermal oxidation process based on the first heating temperature and the first pressure to form a first sub-oxide layer 13a on the semiconductor substrate, as shown in fig. 4.
For example, the first heating temperature is in a high temperature stage, specifically, the high temperature stage may be 950 ℃ to 1100 ℃, such as: 950 ℃, 1000 ℃, 1050 ℃, 1100 ℃, etc., which can reduce defects between the first sub-oxide layer 13a and the semiconductor substrate, namely: when the first sub-oxide layer 13a is the first sub-gate oxide layer 13 and the semiconductor substrate includes a silicon substrate, the defects mentioned herein refer to defects such as Si dangling bonds, Si-H bonds, holes, and the like generated by insufficient reaction in the oxidation process, so that interface trap charges and interface defect state density between the first sub-oxide layer 13a and the semiconductor substrate can be reduced, the reliability at the interface between the oxide layer and the semiconductor substrate is improved, and the quality of the oxide layer is further improved.
Since the oxide layer subjected to the first thermal oxidation treatment has a high quality, when the first sub-oxide layer 13a is fabricated, the thicker first sub-oxide layer 13a can be fabricated, that is: the first sub-oxide layer 13a may account for more than half of the thickness of the entire oxide layer, that is, the thickness of the first sub-oxide layer 13a in the oxide layer manufactured in this embodiment may be greater than the thickness of the second sub-oxide layer 13b, as shown in fig. 5, for example, the first sub-oxide layer 13a may account for 60% -80% of the sum of the thicknesses of the first sub-oxide layer 13a and the second sub-oxide layer 13b (i.e., the target thickness of the entire oxide layer), and the second sub-oxide layer 13b may account for 20% -40% of the sum of the thicknesses of the first sub-oxide layer 13a and the second sub-oxide layer 13b (i.e., the target thickness of the entire oxide layer), so that on one hand, the quality of the entire oxide layer may be improved, thereby improving the yield of the product, on the other hand, the situation that the.
It should be understood that the thickness of the first sub-oxide layer 13a may be equal to the thickness of the second sub-oxide layer 13b, as the case may be.
The first pressure may be in a low pressure stage or a high pressure stage, and specifically, the low pressure stage may be 1Torr to 7Torr, such as: 1Torr, 3Torr, 5Torr, 7Torr, etc.; while the high pressure stage may be 7Torr to 20Torr, such as: 7Torr, 10Torr, 15Torr, 20Torr, etc. When the first pressure is in a low-pressure stage, a first sub-oxide layer 13a with a high profile at two ends and a low profile at the center can be formed; when the second pressure is in the high pressure stage, the first sub-oxide layer 13a with a profile of two ends being low and the center being high can be formed.
In step S104, the semiconductor substrate is subjected to a second thermal oxidation process based on the second heating temperature and the second pressure to form a second sub-oxide layer 13b on the first sub-oxide layer 13a, that is: the oxide layer is completed as shown in fig. 5.
For example, the second heating temperature is in a low temperature stage, specifically, the low temperature stage may be 800 ℃ to 950 ℃, such as: 800 ℃, 850 ℃, 900 ℃, 950 ℃ and the like, and the second sub-oxide layer 13b has a relatively thin thickness, so that the second thermal oxidation treatment can reduce the reaction rate through low temperature, thereby prolonging the growth time of the second sub-oxide layer 13b so as to control the second sub-oxide layer 13b to meet the requirements, and further ensuring the uniformity and quality of the whole oxide layer.
The second pressure can be in a low-pressure stage or a high-pressure stage, and particularly, in order to improve the uniformity of the whole oxide layer, when the first pressure is in the high-pressure stage, the second pressure is in the low-pressure stage; or when the first pressure is in a low pressure stage, the second pressure should be in a high pressure stage, that is, one of the first pressure and the second pressure is 1Torr to 7Torr, and the other is 7Torr to 20 Torr; this allows the first sub-oxide layer 13a to be formed to have a profile complementary to that of the second sub-oxide layer 13b, as shown in fig. 8, so that the uniformity of the finally formed oxide layer can be further improved.
Preferably, the first pressure is 1Torr to 7 Torr; the second pressure is 7Torr to 20Torr, that is, the profile of the first sub-oxide layer 13a formed by the first thermal oxidation treatment is high at both ends and low at the center; the second sub-oxide layer 13b formed by the second oxidation process has a profile with two lower ends and a higher center. Because the temperature of the first oxidation treatment is higher than that of the second oxidation treatment, in order to balance the reaction conditions of the two thermal oxidation treatments, the pressure of the first oxidation treatment is lower than that of the second oxidation treatment, so that the molding of the first sub-oxide layer 13a and the second sub-oxide layer 13b is conveniently controlled, and the quality and the uniformity of the whole oxide layer are improved.
It should be noted that, when the pressure value in the thermal oxidation process is 7Torr, the profile of the sub oxide layer (the first sub oxide layer 13a or the second sub oxide layer 13b) is greatly influenced by other factors (such as temperature), that is, when the pressure value in the thermal oxidation process is 7Torr, the profile of the formed sub oxide layer is not fixed, and the profile of the sub oxide layer may be high at both ends and low at the center, or low at both ends and high at the center, or may be relatively level at both ends and the center. Based on this, in order to facilitate control of the complementary profiles of the first sub oxide layer 13a and the second sub oxide layer 13b, in the present embodiment, the first pressure and the second pressure are preferably pressure values other than 7Torr at the first thermal oxidation treatment and the second thermal oxidation treatment, for example, when the first pressure is in the low pressure stage and the second pressure is in the high pressure stage, the first pressure is preferably a pressure value smaller than 7Torr at the low pressure stage, and the second pressure is preferably a pressure value higher than 7Torr at the high pressure stage.
The first thermal oxidation and the second thermal oxidation may include an in-situ steam oxidation (ISSG) process, in which the reaction gas may be a mixed gas, and the reaction gas may include hydrogen H2And an oxygen-containing gas, optionally, a concentration of hydrogen in the reaction gas of 1% to 33%, that is, a content of hydrogen in the reaction gas of 1% to 33% of the entire reaction gas, such as: 1%, 9%, 17%, 25%, 33%.
For example, the oxygen-containing gas may comprise oxygen O2Nitrogen monoxide gas NO or nitrogen monoxide gas N2O, i.e. the reaction gas in the in-situ steam oxidation process may be O2And H2May also be NO and H2Or a mixed gas of N2O and H2The mixed gas of (1). It should be understood that the oxygen-containing gas is not limited to O2、NO、N2O, and also other oxygen-containing gases.
As shown in fig. 2, an embodiment of the present application further provides a method for manufacturing a semiconductor device, which includes:
step S200, providing a semiconductor substrate;
step S202, performing first thermal oxidation treatment on the semiconductor substrate based on a first heating temperature and a first pressure to form a first sub-oxide layer on the semiconductor substrate;
step S204, performing a second thermal oxidation process on the semiconductor substrate based on the second heating temperature and the second pressure to form a second sub-oxide layer on the first sub-oxide layer, that is: completing the manufacture of the gate oxide layer;
step S206, forming a semiconductor element on the second sub-oxide layer;
wherein the second heating temperature is lower than the first heating temperature, and the first pressure is lower than or greater than the second pressure.
It should be noted that step S200, step S202, and step S204 in this embodiment are the same as step S100, step S102, and step S104 described in any of the foregoing embodiments, and are not repeated herein. The following mainly explains step S206 in the present embodiment in detail.
Specifically, the step S206 may include a step S2061, a step S2062 and a step S2063, wherein:
in step S2061, a dielectric layer 14 and a gate layer 15 are sequentially formed on the second sub-oxide layer 13b, as shown in fig. 6. For example, the dielectric layer 14 may be a silicon oxynitride layer for blocking the dopant in the gate layer 15 from diffusing into the oxide layer below the dielectric layer; the silicon oxynitride layer may be formed by Remote Plasma Nitridation (RPN), but is not limited thereto, and may be formed by other Nitridation processes. The gate layer 15 may be a polysilicon layer, which may be a doped polysilicon layer, the doping type of which is the same as the channel conductivity type of the semiconductor device, so as to enhance the conductivity of the polysilicon layer; the polysilicon layer may be formed by a CVD process, but is not limited thereto, and may be formed by other processes.
In step S2062, the gate oxide layer 13, the dielectric layer 14 and the gate electrode layer 15 are etched to make the sizes of the gate oxide layer, the dielectric layer 14 and the gate electrode layer 15 conform to the target size; it should be noted that, when the semiconductor substrate is formed with the grooves 12 at the positions between the STI structures and the oxide layer is formed at the positions of the grooves 12, a planarization process is also performed to make the STI structures level with the semiconductor substrate 10.
In step S2063, an insulating oxide layer 16 is formed on the side surfaces of the oxide layer, the dielectric layer 14 and the gate layer 15, that is: the process of manufacturing the semiconductor device is completed as shown in fig. 7.
Note that the method of manufacturing the semiconductor device is not limited to the above steps, and may include other steps, which are not described here.
The embodiment of the application also provides a semiconductor device which is manufactured by adopting the manufacturing method of the semiconductor device.
Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the invention following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the invention pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.
Claims (10)
1. A method for forming an oxide layer, comprising:
providing a semiconductor substrate;
performing first thermal oxidation treatment on the semiconductor substrate based on a first heating temperature and a first pressure to form a first sub-oxide layer on the semiconductor substrate;
performing second thermal oxidation treatment on the semiconductor substrate based on a second heating temperature and a second pressure to form a second sub-oxide layer on the first sub-oxide layer;
wherein the second heating temperature is less than the first heating temperature, and the first pressure is less than or greater than the second pressure.
2. The oxide layer forming method according to claim 1, wherein the first heating temperature is 950 ℃ to 1100 ℃; the second heating temperature is 800 ℃ to 950 ℃.
3. The method of claim 1, wherein one of the first pressure and the second pressure is 1Torr to 7Torr, and the other is 7Torr to 20 Torr.
4. The method according to claim 1, wherein a thickness of the first sub-oxide layer is greater than a thickness of the second sub-oxide layer.
5. The method according to claim 4, wherein a thickness of the first sub-oxide layer is 60 to 80% of a sum of thicknesses of the first and second sub-oxide layers, and a thickness of the second sub-oxide layer is 20to 40% of the sum of thicknesses of the first and second sub-oxide layers.
6. The method of claim 1, wherein the first thermal oxidation process and the second thermal oxidation process each comprise an in-situ steam oxidation process, and wherein the reactive gas comprises hydrogen and an oxygen-containing gas.
7. The oxide layer forming method according to claim 6, wherein the oxygen-containing gas includes oxygen gas, nitric oxide gas, or nitrous oxide gas.
8. The oxide layer forming method according to claim 6, wherein a concentration of hydrogen in the reaction gas is 1% to 33%.
9. A method for manufacturing a semiconductor device, comprising:
providing a semiconductor substrate;
performing first thermal oxidation treatment on the semiconductor substrate based on a first heating temperature and a first pressure to form a first sub-oxide layer on the semiconductor substrate;
performing second thermal oxidation treatment on the semiconductor substrate based on a second heating temperature and a second pressure to form a second sub-oxide layer on the first sub-oxide layer;
forming a semiconductor element on the second sub-oxide layer;
wherein the second heating temperature is less than the first heating temperature, and the first pressure is less than or greater than the second pressure.
10. A semiconductor device manufactured by the method for manufacturing a semiconductor device according to claim 9.
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Cited By (1)
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| CN117096012A (en) * | 2023-08-22 | 2023-11-21 | 中环领先半导体材料有限公司 | Oxide film, silicon wafer and preparation method thereof |
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Application publication date: 20210305 |