TWI222705B - Method and structure for a wafer level packaging - Google Patents

Abstract

A method and structure for a wafer level package is provided, which utilizes a plurality of spacer walls on a semiconductor wafer or a transparent substrate, which has the ability to decide the position of the sealant. As a result, the dimension of a device is decided by the position of the sealant and the spacer walls, therefore, shrinking the distance between the photosensitive zone and the sealant will enhance the gross dies after performing a die sawing process to the whole semiconductor wafer. In addition, the semiconductor process decides the height of the spacer walls so that the yield will be improved due to the fact that a uniformity of the gap, which is between the semiconductor wafer and the transparent substrate, and the width of sealant, will be controlled.

Description

1222705 V. Description of the invention (l) 1. [Technical field to which the invention belongs] The present invention relates to a wafer-level packaging method and structure, and more particularly to a method for forming a gap wall on a wafer or a light-transmissive substrate and Method and structure for wafer-level packaging of closed frame adhesive. 2. [Previous technology] In recent years, as the fabrication of microcircuits for wafers has developed toward a high degree of accumulation ', its wafer structure must also have processes such as high power, high density, thinness, and miniaturization. The wafer structure is to encapsulate the crystal grains with materials such as glue / ceramics after the wafer fabrication is completed, so as to protect the crystal grains from external moisture and mechanical damage. The main functions of the chip configuration are Power Distribution, Signal; Signal Distribution, Heat Dissipation, and Protection and Support. Because the development of integrated circuit manufacturing processes will affect the technology of integrated circuit packaging, today's electronic products require light, thin, short, and high integration, which will make the integrated circuit process miniaturization, resulting in an increase in the logic circuits included in the chip , And further increase the number of chip l / 0 (input / output) pins, and to meet these requirements, many different packaging methods have been generated, such as ball grid array (BGA), chip Chip Package (CSP), Multi Chip Mc Package (MCM package), FHp Chip

Package), Tape Carrier Package (TCP) and Wafer Level Package (WLP). V. Description of the invention (2) I No matter what kind of packaging method is used, A will separate the wafer into independent wafers and then ^ The packaging method of °° is a package if the packaging is a semiconductor if ίInstallation procedure. The wafer-level wafer is the packaging object, not the value. The wafer-level packaging is based on the entire package, so the packaging and testing are based on a single wafer as the die bonding and wire bonding process: slow = can be saved Filling, assembly, low labor costs and shortened manufacturing time. It is said that this can greatly reduce the number of steps, such as electric clocks, inspections, etc. Lacquer, fresh line, sealing, cutting, printing, and the first-A diagram to the first c diagram are schematic diagrams of traditional packaging technology. For example, the first one: Provide a semiconductor wafer 101 and a light-transmissive substrate 13. The + conductor wafer 101 includes a plurality of dies 103, and the plurality of dies 103 are utilized. A semiconductor process is performed to form a plurality of microcircuits on the die 103 (not shown in the figure). Then, as shown in FIG. 1B, each die 103 on the semiconductor wafer 101 is passed through A wafer dicing machine cuts | separates to obtain a plurality of independent dies. 〇03, and then uses the pick-and-place arm of a die attacher to place this independent dies on a semiconductor substrate. An epoxy (epoxy) (not shown) was used for adhesion. The semiconductor substrate 105 includes a border 107. The border 107 is obtained by using a special I-patterned stencil and semiconductor process technology. Since the die mount step uses a die bonding machine to separate each The grain i 〇3 is placed in half

Page 6 1222705 Description of the invention (3) On the conductive substrate 105, it is easy for the independent crystal grains to fall, resulting in the number of crystal grains (gr. ss die) decrease 'and therefore the yield will decrease. Then, a wirebond process is performed to transmit the circuit signal of each independent die 103 to the outside. This wiredon process includes wiring a gold wire 107 to this separate die 1 〇3 上. Next, as shown in FIG. 1C, after each independent die 103 is adhered and placed on the semiconductor substrate 105, a glue (M01d) process is performed and tied to the frame 107. A frame adhesive nl is coated on top and a light-transmissive substrate 113 is covered, so that the crystal grains 103 on the semiconductor substrate 105 are covered with a solid shell to prevent moisture from invading from the outside and can effectively bond the upper and lower surfaces. Two substrates. Another type of frame adhesive process is based on the process of thin film liquid crystal (TFT-LCD) display. 'Several gap squashes (Spacer bal Is) (not shown in the figure) are randomly mixed with frame adhesive 111 (3 ^ 1 &111;) Mixed, the purpose of the frame glue 111 is to make the upper and lower substrates in the liquid crystal panel adhere tightly and block the liquid crystal molecules in the panel from the outside. The gap squash ball mainly provides support for the upper and lower substrates. When the light-transmissive substrate Π 3 is covered and pressed, 'this gap squash will form a flat shape, and because the size and shape of this gap squash are different, it is easy to cause the width of the frame glue i [丨 to be difficult to control, and it cannot maintain the upper and lower sides. The proper gap (Gap) between the two substrates causes uneven electric field distribution, which in turn affects the grayscale performance of the liquid crystal. And because the frame adhesive 1 丨 1 is a polymer material, it is easy to chemically react with the liquid crystal, or it is easy to overflow into the sensor area including a wafer 103 when coating. in order to

Page 7 1222705 V. Description of the invention (4) Make the frame adhesive 1 1 1 and the display area have Zhao Shi n. · W θ $ the safe distance of the weight, that is, the size of the component (

Dimension) is not easy to shrink, and _ τ prevents the productivity from increasing. The number of dies that can be cut by the Japanese yen is also reduced, and the position and width of the plastic frame cannot be effectively and accurately controlled in the conventional packaging process or the thin-film LCD display process described above. Therefore, an improved packaging process is urgently needed to be provided. In order to overcome the problems faced by the conventional packaging process. [Inventive Content]

i A t ί 2 12: To provide a wafer-level packaging method and structure, ": using the t process to create a-Spacer Wall, • Fine closed frame glue can be placed on the gap wall 胄"Outside side 璧" and accurately control the position of the closed hinge glue and the distance between the fan frame glue and the display area to further control the size of the component, so that the number of crystal grains generated by the ^ circle is increased, thereby increasing productivity. Another purpose is to improve the yield by using a semiconductor process to produce a 1p stability by precisely controlling the bonding of the transparent substrates with the gap I_ circle and the gap between the transparent substrates. Wafer-level packaging method and structure, a gap wall (Spacer Wal 1), the height can effectively maintain the semiconductor crystal uniformity, and the width of the sealing frame is controlled by the gap between the wafer and the semiconductor wafer

1222705 V. Description of the invention (5) Another object of the present invention is to provide a wafer-level packaging method and structure, which uses a semiconductor process to generate a gap wall. Therefore, the semiconductor wafer and the light-transmissive substrate are implemented. After bonding, it can prevent the moisture from entering the display area from damaging the crystal grains, and can effectively discharge the heat generated inside to the outside.

Another object of the present invention is to provide a wafer-level packaging method and structure, which is based on a wafer-level packaging method. Cutting, therefore, can reduce the probability of die falling and dust (partic 1 e) falling on the die during the semiconductor manufacturing process, and improve its yield. According to the above-mentioned object, the present invention provides a wafer-level packaging method and structure. First, a semiconductor wafer and a light-transmissive substrate are provided, wherein the semiconductor wafer includes a plurality of dies and uses a semiconductor process. A plurality of microcircuits are formed on the plurality of grains. The semiconductor wafer system includes Shi Xi (Si) or other semiconductor materials, such as gallium arsenide (GaAs) 4 indium phosphide (I nP) ', and the plurality of crystal grains on the semiconductor wafer system includes a photosensitive element In addition, the light-transmissive substrate includes a glass or quartz with an optical clock film, such as an anti-refection (AR) layer, an indium tin oxide (ITO) conductive layer, and an anti-infrared ( IR cut) layer or a UV cut layer. Next, a dielectric layer, such as a silicon oxide layer, a nitride or a

Page 9 L 厶 厶 厶 丨 V. Description of the invention (6)), after that, a development process is performed on the dielectric layer to expose the eight-layer photoresist layer, and the photoresist layer is covered. The layer is etched, and then the photoresist layer is used to convert the photoresist layer into a plurality of L-paths including the dielectric layer. Finally, the photoresist layer is stripped to form the position and size of the gap wall. The wall structure is transparent On the optical substrate, the positions and geometrical shapes of the plurality of crystal grains refer to the size of the crystal grains on the semiconductor wafer, and their geometric shapes are slightly smaller. The size of the gap wall is slightly smaller than the two sides or surrounding The shape can be an arm around it, and its position can be L-shaped. > Forming—Rectangular or quadrangular shape, or iiii development process + 'is the use of the plural number on the semiconductor wafer = /, country pattern, and using an automatic frame glue machine to glue a closed frame: and Immediately adjacent to the outer or inner side walls of the plurality of gap walls: ί The closed frame rubber system may be selected from epoxy glue, ultraviolet j: two seals

Adhesive) glue or thermo-plastic glue. Then, the light-transmissive substrate is covered on a semiconductor wafer, and a plurality of dies on the semiconductor wafer are aligned with a plurality of gap walls on the light-transmittable substrate to complete the packaging process. The above-mentioned wafer-level packaging method and structure can also use a semiconductor wafer as a substrate, and form a structure of a gap wall and a closed frame adhesive on the semiconductor wafer. In addition, a gap wall structure can also be formed on a semiconductor wafer or a light-transmissive substrate, and a closed frame glue can be formed on a corresponding other semiconductor wafer or a light-transmissive substrate, and the same packaging as described above can be performed. program.

Page 10 1222705 V. Description of the invention (7) IV. [Embodiment] The following is a detailed description of the present invention. The description of the process and structure in the following description does not include the complete process of production. Existing techniques used in the present invention are only cited in detail here to help explain the present invention. The content of the present invention can be disclosed through the following description of the first preferred embodiment and its related diagrams (second A to second F). First, referring to the second diagram A, a semiconductor wafer 200 and a light-transmitting substrate 230 are provided. The semiconductor wafer 200 includes a semiconductor material, such as silicon (si), indium phosphide ( InP) or gallium arsenide (GaAs). Each semiconductor wafer 200 includes a plurality of die 001 (die) having a proper shape next to each other, such as a rectangle or a square. Each die 201 includes a light-sensitive element. For example, 'Complementary Oxide Metal Semiconductor Image Sensor (C μ 〇simage sensor), Liquid Crystal on Silicon (LCoS), Charge Coupled Device (CCD), etc., that is, each die 2 0 1 has a photosensitive area (not shown). In addition, a plurality of micro-circuits are included in the plurality of grains 2 01 (not shown in the figure), and moreover, each of the plurality of grains 2 1 includes one or two opposite sides. 201 A (Bonding Pads), such as an aluminum pad, is used as a semiconductor bonding pad to complete the packaging process and perform a cutting process to electrically connect with another substrate. The pad 2 is formed by chemical vapor deposition or physical vapor deposition. In addition, the light-transmissive substrate 20 includes an optical coating 2 0 3 A, such as a transparent indium tin oxide 1222705 with excellent conductive properties. V. Invention (8) (Indium Tin Oxide, ΙΤ0) layer or an anti-reflection layer 1, an anti-infrared (IR cut) layer, an anti-ultraviolet (UV cut) layer. Next, referring to FIG. 2B, first, a light-transmissive substrate 203, such as a quartz or a glass substrate, is provided. The light-transmissive substrate 20 3 includes an optical coating layer 203A, and then, the optical coating layer 20 is provided. A dielectric layer 205 is deposited on 3 A. The material of this dielectric layer 20 5 can be silicon oxide, silicon nitride, or a polymer film (such as polyimide). This dielectric layer 2 05 can be made of chemistry. It is formed by a vapor deposition method (Chemical Vapor Deposition, CVD). Next, as shown in FIG. 2C, a photoresist layer 207 is coated on the dielectric layer 205, and a gap wall structure 209 is obtained by using semiconductor processes such as exposure, development, and etching. The formation of the partition wall 209 is performed by the following steps: First, an exposure process is performed, and a photomask (not shown in the figure) with a specific pattern is transferred to the photoresist layer by pattern transfer. 〇7 on. Then, post-exposure bake is performed on the exposed photoresist layer 20 7 (post

Exposure Bake) procedure to reduce the standing wave phenomenon. Then, a developing process is performed to remove the exposed photoresist layer 207 to expose a part of the dielectric layer 205. After that, the unremoved photoresist layer 207 is used as a photomask, and the wet Etching or dry etching, for example, wet etching method of hydrofluoric acid aqueous solution (Hydr 〇f 1 u ric A cid) 'Plasma Etching or Reactive Ion Etch , RIE) dry etching method, remove the exposed dielectric layer 205 and the optical coating layer 203A below it, and finally, peel

Page 12122705 V. Description of the invention (9) After removing (stri ρ) the photoresist layer 2 0 7 which has not been removed, a gap wall structure 2 0 9 is formed on the light-transmitting substrate 2 0 3 'as described in the first ^ One D picture does not. This spacer step 009 includes a dielectric layer 205 and an optical coating layer 203A '. The height of the spacer wall 009 is determined by the material of the spacer wall 209. Generally speaking, the height is 〇 · 1 to tens of micrometers. Furthermore, the position, geometry, and size of the gap wall 209 can be determined according to the position, size, and geometry of the photosensitive area of the crystal grain 01. Furthermore, the position, geometry, and size of the gap wall 209 can also be based on the position of the crystal grains 001, the gap wall, or continuous. The gap walls on both sides of the above can be grown to maintain the gap wall. As mentioned, the support is transparent, regardless of size and geometry. In one embodiment of the present invention, the interval 209 has an arm-shaped geometry, or an arm-shaped gap arranged in an arm-shaped geometry with a number of independent or partially continuous unit structures. The wall 209 can refer to the opposite standing edge on the grain 201, and the size is slightly smaller than the length of the side of the grain. In another embodiment, the geometry of the wall 209 may be similar to the geometry of the grains on the semiconductor wafer or the photosensitive area of the grains, and the size is slightly smaller than the space around the grains for subsequent use. It should be noted that the position 4, geometry and size of the Π between the present invention is not limited to the above embodiment: the m semiconductor lithography step is made, which can be used as a balance and support a fixed distance between the first substrate 20 3 and the subsequent crystal grains. For example, the L-shape is out of the scope of the present invention. & Cool J ^ ^ An automatic frame glue machine (inner side wall or outer side of Auto 2 0 9 ', as shown in Figure ^ -E, using Sealant Machine), in the gap wall

1222705 Fifth, the invention description (ίο) = into a closed frame frWU closed frame adhesive 211 with a width less than 100 microns and a width less than 200 microns can be made of epoxy resin glue, ultraviolet glue or hot melt glue, etc. The material of the closed frame rubber 211 is selected ^ The material of the outer wall is fixed to the material of the adhesive gap wall 2G9 '. For example, when the wall 2 () 9 is-, the child, such as polyimide, can choose the curing speed. UV adhesive with fast thermal characteristics; and when the partition wall is thin, it can be used with any of the aforementioned frame adhesives. #Where the nitride is formed, the position of the wall 209 can be determined according to the size of each grain 20m or the photosensitive area on the grain, and the sealant 2m 1 is next to the ad join gap. The inner side wall or the outer side wall of the wall 2 0 9, so the position of the sealing frame 2 11 can be controlled, and the display area (photosensitive area) and the closing frame 2 of a grain 201 can be effectively shortened. Distance, and then increase the number of crystals obtained by a wafer to increase its production capacity. Next, a curing process is performed on the sealing frame adhesive 2 ′, such as an ultraviolet or thermal curing process [afterwards', using a grinding process to grind the sealing frame adhesive 2 11 on the light-transmissive substrate 203. Next, a semiconductor wafer 200 including a plurality of crystal grains 001 is covered on the light-transmissive substrate 230 and aligned with the plurality of gap walls 20 on the light-transmissive substrate 230. 9, so that each die 001 can be located in the structure of the gap wall 209, and then the semiconductor wafer 200 and the light-transmissive substrate 203 are bonded by the sealing frame adhesive 2 11 to Complete the wafer-level packaging process of the present invention. Since the present invention uses a semiconductor process to form the gap wall 20 9,

Page 14 1222705 V. Explanation of the invention (11) Therefore, its height and flatness can be accurately controlled. Therefore, when the semiconductor wafer and the light-transmitting substrate are bonded, the semiconductor wafer and the light-transmitting substrate can be controlled. The uniformity of the gap. Furthermore, since the sealant 2 1 1 does not support and balance the height (or distance) between the semiconductor wafer and the light-transmissive substrate, it also helps to precisely control the height and flatness. In addition, the present invention can further control the stability of its glue width and increase its yield, and because it does not require the traditional gap wall ball material to be mixed in this closed frame glue 2 11, it can reduce the process steps and prevent In the traditional packaging method, the frame adhesive overflows into the photosensitive area. Therefore, there is no need for a large safety distance between the frame adhesive and the photosensitive area, thereby increasing its productivity. After the wafer-level packaging of the present invention is completed, the gap wall 209 is used as a cutting line (Scribe Line) to perform a scribe process, such as laser cutting, wafer cutting (W afer S aw) and so on. When dicing is performed, the entire semiconductor wafer 2000 is diced to obtain a plurality of independent crystal grains 021. When one side of the plurality of grains 2 01 or the opposite sides include a plurality of welding pads 2 0 1 A, the cutting method for one side including the plurality of pads 2 0a The system uses a bevel cutting method so that the bonding pad 2A is exposed and serves as a contact point for electrical connection with the outside world. Since the present invention is to perform a dicing process after the semiconductor wafer 200 is packaged, the manufacturing time can be shortened, and the chip falling and dust (partic 1 e) due to chip dropping during the manufacturing process can be reduced. The probability of grains 001 can effectively improve the yield of the product.

1222705 V. Description of the invention (12) A semiconductor wafer 200 The second F diagram is a schematic diagram for explaining the situation of bonding with a light-transmissive substrate 2 0 3 in the second E diagram

The content of the present invention can be disclosed through the following description of the second preferred embodiment and its related diagrams (third A to third E). First, referring to FIG. 3A, a semiconductor wafer 300 and a light-transmissive substrate 300 are provided. The semiconductor wafer 300 includes a semiconductor material, such as silicon, indium phosphide, or gallium arsenide. Each semiconductor wafer 300 includes a plurality of dies 3 with appropriate shapes and close to each other, such as a rectangle or a square. Each of the plurality of dies 301 includes a light-sensitive element, for example, Complementary metal oxide semiconductor image sensors, silicon-based liquid crystals, charge-coupled devices, etc., that is, each die 301 has a photosensitive area (not shown). In addition, a plurality of microcircuits are fabricated on the plurality of grains 301 (not shown), and moreover, a plurality of grains are included on one side of each of the plurality of grains 30 or on opposite sides. The pad 301 A, such as a solder pad, is used as a solder joint for electrically connecting another substrate after the semiconductor wafer 300 completes the packaging process and performs a cutting process. This pad 301 A uses chemical gas. Formed by phase deposition or physical vapor deposition. In addition, the light-transmissive substrate 300 includes an optical coating 303A, such as a transparent Indium Tin Oxide (ITO) layer, an anti-reflection layer, and an infrared cut (IR cut) layer having excellent conductive properties. Or a UV-cut layer. . Next, referring to FIG. 3B, a dielectric layer 305 is deposited on the semiconductor wafer 300, where the semiconductor wafer 300 includes a plurality of grains 300i.

Page 12122705 The material of the dielectric layer 305 may be silicon oxide, silicon nitride or a quinqueline film (such as polyimide), and then the dielectric layer 305 is coated with 3 0 7. The dielectric layer 305 and the photoresist layer 307 can be formed by a wind product method. The pre-emulsion phase w deposits a photoresist layer 3 07 on the dielectric layer 3 05, and then, as shown in FIG. 3C, a semiconductor wall process such as exposure, development, and etching is used to obtain a wall structure 3 0 9 Each of the plurality of dies 3 on the semiconductor wafer 300 has two opposite sides of the surface. The formation of this gap wall 309 is performed by the following steps: First, a lithographic process is performed to transfer a pattern with a specific pattern to a light mask (not shown in the figure) by transferring the pattern to light. On the resist layer 307, the exposed photoresist layer 307 is then subjected to a post-exposure baking 9 procedure to reduce the occurrence of standing wave phenomena. Then, the exposed photoresist layer 3 07 is removed to expose a part of the dielectric layer 305, and then, the unremoved photoresist layer 3 07 is used as a photomask, and wet etching or dry etching is used. For example, the wet etching method of hydrofluoric acid solution (Hydrofluoric Ac id), dry etching method of plasma etching (Plasma Etching) or reactive ion etching (Reactive Ion Etch, RIE) will expose the dielectric layer. 305 Removed. Finally, the unremoved photoresist layer 3 0 7 is stripped to form a gap wall structure 3 0 9 each of the plurality of grains 3 0 1 on the semiconductor wafer 3 0 0 On the surface, for example, two opposite sides, the gap wall 3 0 9 includes a dielectric layer 3 0 5, and the height of the gap wall 3 9 9 is determined by the material of the gap wall 3 9 'Generally speaking' Its south degree is between 0.1 and several tens of micrometers (micrometer).

Page 17 1222705 V. Description of the invention (14) '' —Yet again 'The position, geometry and size of the gap wall 3 0 9 can be determined according to the position, size and geometry of the photosensitive area. Furthermore, the position, geometry, and size of the gap wall 309 can also be determined according to the position, size, and geometry of the crystal grains 301. In one embodiment of the present invention, the 'partition wall 3 0 9 has an arm-shaped geometry, or is arranged in an arm-shaped manner with a unit structure of ^ 1 standing or continuous or partially continuous. shape. The above-mentioned arm-shaped gap wall 3 0 9 can be opposite to the crystal grains 3 01 and the size of the rear side is slightly smaller than the length of the side of the crystal grains. In another embodiment, the geometry of the I5 two-walled wall ^ 0 9 may be similar to that of the crystal grains, and the size H is smaller than the perimeter of the crystal grains to reserve a certain distance for subsequent use. == The position and size of the gap wall 3 0 9 of the present invention are not limited to those described in the above examples, as long as it can be produced by using the semiconductor lithography step, it can be used as a balanced, f-supporting light-transmissive substrate 3 0 3 Those with a fixed distance from the subsequent crystal grains, such as l saint, etc., do not depart from the scope of the present invention. Then, as shown in the third figure, an automatic frame glue machine is used to form a seal with a width of less than ι 00 μ micron and a depth of less than 200 μm at the inner or outer side wall of the wall. Frame rubber 3 11, the quality of this closed frame rubber 3 丨} can be epoxy resin, UV glue or hot melt adhesive, etc., and the material of the closed frame rubber 311 selected is determined by the gap wall 3〇 9 material, for example, the door gap wall is known as 3 9 9 is a polymer film, such as polyimide, can be ^ q rV, chemical conversion speed and UV glue without heating characteristics, and when the gap wall returns 9 is oxidation Materials and nitride films, can be used with any of the foregoing materials

Page 18 1222705 V. Description of the invention (15) Frame rubber. Because the position of the gap wall 3 0 9 is determined according to the size of each grain 3 01, and the closed frame 31 31 is close to the inner or outer side wall of the gap wall 3 09, so the closed frame 31 The position can be controlled, and the distance between the photosensitive area containing a die 3 01 and the sealing frame 3 ′ can be effectively shortened, thereby increasing the number of die obtained from a wafer to increase its productivity. Next, the closed sealant 3 1 1 performs a curing process, for example, a UV light or thermal curing curing sequence “after” uses a grinding process to grind the closed sealant 3 11 on the semiconductor wafer 300, and then, A light-transmissive substrate 303 including an optical coating 3 303 A is covered on a semiconductor wafer 300, such as a glass or a quartz substrate, and aligned with a plurality of gap wall structures 309 on the semiconductor wafer 300 So that each die 301 can be located in the structure of the gap wall 309, and then the semiconductor wafer 300 and the light-transmissive substrate 303 are bonded by the sealant frame 311. . Since the present invention uses a semiconductor process to form the gap wall 309, the height and flatness of the gap wall 309 can be accurately controlled, and therefore the bonding of the semiconductor wafer and the light-transmissive substrate is also performed. At this time, the uniformity of the gap between the semiconductor wafer and the light-transmitting substrate can be controlled, and the stability of the glue width can be further controlled, thereby increasing the yield of its products. In addition, because it is not necessary to mix the traditional spacer squash material in the closed frame rubber 3, 11, the process steps can be reduced, and the traditional packaging method can prevent the frame rubber from overflowing into the photosensitive area. Therefore, the frame glue and the photosensitive area There is no need for a large safety distance, so its capacity can be increased.

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Page 19, 1222705 V. Description of the invention (16) ------- Then, after completing the wafer-level packaging process of the present invention, use the gap wall 30 9 as a cutting path to perform a cutting process, such as Laser cutting, wafer cutting, etc. When performing the dicing, the entire semiconductor wafer 30 () is diced to obtain a plurality of independent dies 3o. When one side of the plurality of dies 3o1 or the opposite sides include When a plurality of solder pads are used, the cutting method of one side including the plurality of solder pads 3 0 1 A is a bevel cutting method, so that the solder pad 301A is exposed as an electrical connection with the outside world. One touch point. Since the present invention is to complete the semiconductor wafer 300 package and then perform the dicing process, the manufacturing time can be shortened, and the drop of crystal grains and dust from falling on the crystal grains 3 during the process can be reduced. 〇1 probability, so can effectively improve the product yield. The second E diagram is used to assist in explaining the bonding situation of a semiconductor 300 and a light-transmissive substrate 303 in the third D diagram. 181 After the description of the above first and second preferred embodiments, it can be understood that there are other implementations of the present invention, such as gaps. The structures can be formed on a semiconductor wafer or a semiconductor wafer, respectively. On the light-transmitting substrate, the 2 sealant can also be coated on the corresponding other—a semiconductor wafer or a light-transmissive substrate, and then a dicing process is performed to obtain a separated independent chip. According to the above description of the preferred embodiments of the present invention, one of the advantages of the invention is the formation of a gap wall structure.

1222705 V. Description of the invention (π) The formation can precisely control the position of the sealing frame glue, and then control the size of the component '. Therefore, the number of crystal grains obtained after a wafer is cut can be increased. In addition, by precisely controlling the height of this gap wall, the uniformity of the gap between the semiconductor wafer and the light-transmittable substrate and the stability of the width of the sealant can be controlled. After the substrates are bonded, a dicing process is performed, so the productivity can be increased. The above description is only a preferred embodiment of the present invention, and is not intended to limit the patent application rights of the present invention. At the same time, the above description should be clarified and implemented by those who are familiar with the technical field t, so other equivalent changes or modifications made without departing from the spirit disclosed by the present invention should be included in the scope of patent application described below.

Page 21122705 Brief description of the drawings [Simplified illustration of the icons] Figures A to C are the schematic diagrams of the semiconductor structure corresponding to each step of the traditional packaging technology process; Figures A to F are based on A schematic diagram of a semiconductor structure junction surface corresponding to each step of a preferred embodiment of a wafer electrode packaging method of the present invention, wherein a spacer structure is formed on a light-transmissive substrate; and FIGS. 3A to 3E It is a schematic diagram of a semiconductor structure corresponding to each step of another preferred embodiment of a wafer electrode packaging method according to the present invention. The spacer structure is formed on a semiconductor wafer. Symbols of the main part

Page 22 1222705 Brief description of the drawings 203A Optical coating 205 Dielectric layer 207 Photoresist layer 209 Gap wall 212 Sealing frame 300 Semiconductor wafer 301 Die 301 A Pad 303 Light-transmissive substrate 30 5 Dielectric layer 307 Light Resistance layer 309 Clearance wall 311 Closure

Page 23

Claims (1)

1222705 VI. Scope of patent application 1 · A wafer-level package structure includes: a plurality of crystal grains are next to each other, each of the plurality of crystal grains has a photosensitive area; a plurality of gap wall structures are located on the plurality of crystal grains Each of the photosensitive regions is located between the plurality of gap wall structures; the plurality of closed frame adhesives are located on the plurality of crystal grains, and each of the plurality of closed frame adhesives is immediately adjacent (ad j 〇ini ng) On any side wall (si de wa 1 1) of each of the gap wall structure; and a light transmissive substrate is located on the plurality of gap wall structure. 2. The structure of the wafer-level package according to item 1 of the scope of application, wherein the material of the plurality of gap wall structures is a silicide. 3. The structure of the wafer-level package according to item 1 of Shen Zunwei, wherein the material of the plurality of gap wall structures is a silicon nitride. 4. The structure of the wafer-level package according to item 1 of the application scope, wherein the material of the plurality of gap wall structures is a polymer film. 5. The structure of the wafer-level package as described in item 4 of the application scope, wherein the above polymer film comprises a polyimide. 6 · The structure of the wafer-level package according to item 1 of the application scope, wherein the material of the light-transmittable substrate is glass. Page 24 1222705 6. Scope of patent application 7. The structure of the wafer-level package as described in item 1 of the scope of application, wherein the aforementioned closed frame adhesive material is an epoxy resin adhesive. 8. The structure of the wafer-level package according to item 1 of the scope of application, wherein the above-mentioned closed frame adhesive material is a UV-ray adhesive 9. The structure of the wafer-level package according to item 1 of the scope of application, wherein The closed frame adhesive material is a hot melt adhesive. 10. The structure of the wafer-level package according to item 1 of the application scope, wherein any one of the side walls is an inner side wall. 11. The structure of the wafer-level package according to item 1 of the application scope, wherein any one of the side walls is an outer side wall. 1 2. The structure of the wafer-level package according to item 1 of the application scope, wherein the plurality of gap wall structures described above include at least two unit structures. 1 3. The structure of the wafer-level package according to item 12 of the scope of application, wherein the plurality of gap wall structures further includes two opposite sides on the plurality of grains. 1 4. The structure of the wafer-level package as described in item 12 of the application scope, wherein the above Page 25 1222705 VI. The scope of the patent application The plurality of gap wall structures further includes two adjacent sides on the plurality of grains. 1 5. The structure of the wafer-level package according to item 1 of the scope of application, wherein the plurality of gap wall structures further include geometric shapes arranged in an arm shape by a plurality of independent unit structures. 1 6. The structure of the wafer-level package as described in item 1 of the application scope, wherein the plurality of gap wall structures further include a geometric shape arranged in the shape of an arm by a plurality of continuous unit structures. 1 7. A method for wafer-level packaging, comprising: providing a semiconductor wafer, wherein the semiconductor wafer includes a plurality of dies; depositing a dielectric layer on the semiconductor wafer, and covering the plurality of dies Grains, removing a portion of the dielectric layer to form a plurality of gap wall structures on each of the plurality of grain surfaces; forming a plurality of closed frame adhesives adjacent to any side wall of the plurality of gap wall structures; and A light-transmissive substrate is covered on the semiconductor wafer. 1 8. The method of wafer level packaging as described in item 17 of the scope of application, wherein any one of the plurality of dies mentioned above includes a photo-sensitive area. Page 26 1222705 VI. Scope of Patent Application 19. The method of wafer level packaging as described in scope 17 of application, wherein the step of removing the dielectric layer includes exposing a photosensitive area. 20. The method of wafer-level packaging as described in the scope of application 19, wherein the above-mentioned photosensitive area further includes being surrounded by any four of the plurality of gap wall structures. 2 1. The method of wafer level packaging as described in item 17 of the scope of application, wherein any one of the side walls is an inner side wall. 2 2. The method of wafer level packaging as described in item 17 of the scope of application, wherein any one of the side walls is an outer side wall. 2 3. The method of wafer-level packaging as described in item 17 of the scope of application, wherein the material of the light-transmittable substrate is quartz. 2 4. A method for wafer-level packaging, comprising: providing a semiconductor wafer and a light-transmissive substrate, wherein the semiconductor wafer includes a plurality of dies; and depositing a dielectric layer on the light-transmissive substrate Depositing a photoresist layer on the dielectric layer; removing part of the photoresist layer to expose part of the dielectric layer; removing part of the exposed dielectric layer, using the photoresist layer as a photomask, Page 27 1222705 6. Apply for a patent to form a plurality of gap wall structures on the light-transmissive substrate; form a plurality of closed frame adhesives immediately adjacent to any side wall of the plurality of gap wall structures; and cover the semiconductor A wafer is on the light-transmissive substrate. 2 5. The method of wafer level packaging as described in item 24 of the scope of application, wherein the step of removing a part of the exposed dielectric layer includes using the plurality of dies of the semiconductor wafer as a reference pattern. 26. The method of wafer level packaging as described in item 24 of the scope of application, wherein any one of the side walls is an inner side wall. 2 7. The method of wafer level packaging as described in item 24 of the scope of application, wherein any one of the side walls is an outer side wall. 28. The method of wafer level packaging according to item 24 of the scope of application, wherein any one of the plurality of dies mentioned above includes a photosensitive area. Page 28