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TW594964B - Multi-chip package - Google Patents

Multi-chip package Download PDF

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Publication number
TW594964B
TW594964B TW088114803A TW88114803A TW594964B TW 594964 B TW594964 B TW 594964B TW 088114803 A TW088114803 A TW 088114803A TW 88114803 A TW88114803 A TW 88114803A TW 594964 B TW594964 B TW 594964B
Authority
TW
Taiwan
Prior art keywords
chip
wafer
pads
patent application
scope
Prior art date
Application number
TW088114803A
Other languages
Chinese (zh)
Inventor
Hung-Min Liou
Original Assignee
United Microelectronics Corp
United Silicon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by United Microelectronics Corp, United Silicon Inc filed Critical United Microelectronics Corp
Priority to TW088114803A priority Critical patent/TW594964B/en
Application granted granted Critical
Publication of TW594964B publication Critical patent/TW594964B/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Semiconductor Memories (AREA)

Abstract

A multi-chip package changes the lead frame design to pack more than two chips in a single package. A chip carrier with area smaller than chip area can expose the pads when the chips are installed along the same direction. Hence no wire winding happens during wire bonding and without any process for chip. The package structure efficiency and chip density are raised to improve the device integrity under limit cost condition.

Description

594964 4966tw r.doc/〇〇6 A7 B7 五、發明說明（/‘） 本發明是有關於一種半導體的封裝結構，且特別是有 關於一種多晶片的封裝結構。 在半導體產業中，積體電路(Integrated Circuits, 1C)的 生產’主要分爲三個階段：矽晶片的製造、積體電路的製 作以及積體電路的封裝(Package)等。就積體電路的封裝而 言，此即是完成積體電路成品的最後步驟。封裝之目的在 於提供晶片（Die)與印刷電路板(Printed Circuit Board, PCB) 或其他適當元件之間電性連接的媒介及保護晶片。 在完成半導體製程後，晶片係由晶圓（Wafer)切割形 成。一般晶片上會具有焊墊（Bonding Pad)，其作用爲提供 晶片檢測之測試點，並作爲晶片與其他元件間連接之端 點。爲了連接晶片和其他元件，通常會使用導線（Wire)或 凸塊(Bump)作爲連接之媒介。 經濟部智慧財產局員工消費合作社印製 第1圖繪示習知一種晶片的封裝結構示意圖。晶片1〇〇 配置於一晶片座102上，晶片座102裝設於導線架1〇4的 中心。晶片100其中一面上有金屬製的焊墊1〇6，焊墊1〇6 的作用係用以作爲晶片100對外的接點，常以鋁做成。而 晶片100係以沒有焊墊的一面，利用晶片接合材料(adhesive) 固定在一起。在固定之後，再利用導線(wire)l〇8，將晶片 100上的各個焊墊一個一個的電性連接至與各個焊墊相對 應的接腳110。之後，再利用封裝材料(packaging matenal) 112 將晶片100、導線108、以及接腳110的部分位置封住，除 了可以固定各元件彼此之間的相對位置外，保護晶片及晶 片與導線連接的部分，並且隔絕外界對晶片操作的影響因 3 本紙張尺度適用中國國家標準（CNS)Al規格（210 X 297公楚) -- 594964 A7 B7 4966lvvr.doc/006 五、發明說明（厶） 素包括。接腳110由封裝材料112的側面伸出，並 向下彎折’連接到印刷電路板(printed circuit board，PBC)(未 繪示）。 然而’隨著晶片愈來愈高的積集度，業界對於封裝的 要求也日益局。傳統的封裝結構，內部僅有—^個晶片， 在今日高度情報化的社會，多媒體應用的市場不斷急速地 擴張，其兀件積極度與效能(performance)均受限於單一晶 片，而無法提升，造成成本價格無法降低。因此如何增加 積體電路的元件積極度與效能，進而降低成本已是刻不容 緩的課題。 因此，本發明提供一種多晶片的封裝結構，其結構包 括一第一晶片，包括一第一表面與一第二表面，第一表面 具有複數個第一銲墊；一第二晶片，包括一第三表面與一 第四表面，第三表面具有複數個第二銲墊；一導線架，包 括一晶片座與複數隻接腳，晶片座具有一第五表面與一第 六表面，第五表面貼附該第二表面，第六表面貼附第三表 面，且晶片座之第六表面暴露出第三表面上之銲墊，接腳 均具有一內腳部分與一外腳部分；複數條導線，分別對應 連接第一銲墊與第二銲墊至接腳的內腳部分；以及一封裝 材料，包覆第一晶片、第二晶片、與接腳的內腳部分。 本發明所提出的多晶片封裝結構，以現有的封裝技術 即可做到，極適合廠商的生產安排。 本發明改變對導線架的設計，使用面積較晶片爲小的 晶片座，如此不需對晶片本身作任何其他的處理，僅需使 4 本紙張尺度適用中國國家標準（CNS)Al規格（210 X 297公髮） --------------------訂·--------線 (請先閱讀背面之注音？事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 594964 4 9 6 61 \ν Γ. d 〇 c / 0 0 6 A7 B7 五、發明說明（3) 用同一規格的晶片，成本花費低。 本發明之多晶片封裝結構將兩片以上的晶片封裝在〜 起，當應用於動態隨機存取記億體時，可使其記億體的密 度倍增。同時不需對晶圓重新設計、製作，而可將二晶片 整合於一封裝中，縮短晶片間距離，使記憶體的效能提高。 而且由於不需重新設計、製作晶圓，因此本發明可快速的 切入市場。 藉由本發明所提出的多晶片封裝結構，可在增加有限 的成本中增強晶片的密度與效能，並進而增加元件的積極 度。 本發明亦可用於邏輯元件上，如此可將具有不同功能 的晶片封裝在一起，不僅增加其密度，而且增強其功能。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： 圖式之簡單說明： 第1圖繪示習知一種晶片的封裝結構示意圖；以及 第2圖繪示依照本發明〜較佳實施例之一種多晶片封 裝結構示意圖。 圖式之標記說明： 100、210、222 :晶片 102、202 :晶片座 104、200 :導線架 106、214、223 :焊墊 5 本紙張尺度適用中國國家標準(CNS)A4規格（210 X 297公 ---------訂---------線^^^_ (請先閱讀背面之注咅？事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 594964 4 9 6 61 w Γ. d 〇 c / 0 0 6594964 4966tw r.doc / 〇〇6 A7 B7 V. Description of the invention (/ ') The present invention relates to a semiconductor package structure, and more particularly to a multi-chip package structure. In the semiconductor industry, the production of integrated circuits (1C) is mainly divided into three stages: the manufacture of silicon wafers, the manufacture of integrated circuits, and the packaging of integrated circuits. As far as the packaging of integrated circuits is concerned, this is the final step to complete the finished integrated circuit. The purpose of packaging is to provide a medium for the electrical connection between the die and the printed circuit board (PCB) or other appropriate components and to protect the chip. After the semiconductor process is completed, the wafer is formed by wafer cutting. Generally, there will be a bonding pad on the wafer, which is used to provide test points for wafer inspection and as the end point of the connection between the wafer and other components. In order to connect the chip and other components, wires or bumps are usually used as the connection medium. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. Figure 1 shows a schematic diagram of a conventional package structure for a chip. The wafer 100 is arranged on a wafer holder 102, and the wafer holder 102 is installed in the center of the lead frame 104. One side of the wafer 100 has a metal pad 106. The function of the pad 10 is to serve as an external contact of the wafer 100, and is often made of aluminum. On the other hand, the wafer 100 is fixed on the side without pads by a wafer bonding material. After the fixing, the wires 108 are used to electrically connect each of the pads on the chip 100 to the pins 110 corresponding to the respective pads. After that, the packaging material (packaging matenal) 112 is used to seal the positions of the chip 100, the wires 108, and the pins 110. In addition to fixing the relative positions of the components to each other, the chip and the parts where the chips are connected to the wires are protected. , And isolate the outside world from the impact on the operation of the wafer because 3 paper sizes are applicable to the Chinese National Standard (CNS) Al specification (210 X 297 Gongchu)-594964 A7 B7 4966lvvr.doc / 006 5. Description of the invention (厶) Elements included. The pins 110 protrude from the side of the packaging material 112 and are bent downward 'to be connected to a printed circuit board (PBC) (not shown). However, as the chip becomes more and more highly integrated, the industry's requirements for packaging are becoming more and more severe. The traditional package structure has only ^ chips inside. In today's highly informative society, the market for multimedia applications continues to expand rapidly. Its enthusiasm and performance are limited to a single chip and cannot be improved. , Resulting in cost and price cannot be reduced. Therefore, how to increase the enthusiasm and efficiency of the integrated circuit components, and then reduce the cost is an urgent task. Therefore, the present invention provides a multi-chip packaging structure. The structure includes a first chip including a first surface and a second surface. The first surface has a plurality of first pads. A second chip includes a first chip. Three surfaces and a fourth surface, the third surface has a plurality of second pads; a lead frame includes a wafer holder and a plurality of pins, the wafer holder has a fifth surface and a sixth surface, and the fifth surface is attached Attach the second surface, the sixth surface is attached to the third surface, and the sixth surface of the wafer holder exposes the pads on the third surface, and the pins each have an inner leg portion and an outer leg portion; a plurality of wires, The first pad and the second pad are respectively connected to the inner leg portion of the pin; and a packaging material covers the first chip, the second wafer, and the inner leg portion of the pin. The multi-chip package structure proposed by the present invention can be achieved by the existing packaging technology, which is very suitable for the production arrangement of the manufacturer. The invention changes the design of the lead frame, and uses a wafer holder with a smaller area than the wafer, so that there is no need to do any other processing on the wafer itself, and only 4 paper sizes need to be adapted to the Chinese National Standard (CNS) Al specification (210 X 297 public hair) -------------------- Order · -------- line (Please read the phonetic on the back? Matters before filling out this page) Economy Printed by the Consumers' Cooperative of the Ministry of Intellectual Property Bureau 594964 4 9 6 61 \ ν Γ d oc / 0 0 6 A7 B7 V. Description of the invention (3) With the same specification chip, the cost is low. The multi-chip package structure of the present invention encapsulates more than two chips at a time. When applied to dynamic random access memory, the density of the memory can be doubled. At the same time, there is no need to redesign and fabricate the wafer. Instead, the two wafers can be integrated into a package, which shortens the distance between the wafers and improves the memory performance. Moreover, since the wafer does not need to be redesigned and fabricated, the present invention can be quickly cut into the market. With the multi-chip package structure proposed by the present invention, the density and efficiency of the chip can be enhanced while increasing the limited cost, and thus the enthusiasm of the component can be increased. The invention can also be applied to logic elements, so that chips with different functions can be packaged together, which not only increases their density, but also enhances their functions. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is described below in detail with the accompanying drawings as follows: Brief description of the drawings: FIG. 1 FIG. 2 is a schematic diagram showing a conventional packaging structure of a chip; and FIG. 2 is a schematic diagram showing a multi-chip packaging structure according to the present invention ~ a preferred embodiment. Description of drawing symbols: 100, 210, 222: Wafer 102, 202: Wafer holder 104, 200: Lead frame 106, 214, 223: Welding pad 5 This paper size applies to China National Standard (CNS) A4 (210 X 297) Public --------- Order --------- Line ^^^ _ (Please read the note on the back? Matters before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 594964 4 9 6 61 w Γ. D oc / 0 0 6

五、發明說明（¥ ) 經濟部智慧財產局員工消費合作社印製 108、220、225 ··導線 110、204 :接腳 112、230 :封裝材料 206、208 :平面 212 :第一晶片210之表面 216、226 :晶片座202的表面 218、228 :晶片接合材料 224 :第二晶片222之表面 232 :接腳204之內腳部分 234 ··接腳204之外腳部分 236 :印刷電路板 實施例 舊式的晶片封裝結構，其內部僅有一個晶片，其功能 將受到限制’爲了因應積極度的需求，本發明提出一種多 晶片的封裝結構，其藉由改變導線架的設計，採用比晶片 表面面積小的晶片座，將兩片以上的晶片封裝在一起，提 升其效能（performance)及密度。爲讓本發明之特徵和優點 能更淸楚，以下將以封裝兩個晶片爲例，對本發明的封裝 結構作詳細說明。 第2圖繪示依照本發明一較佳實施例之一種多晶片封 裝結構示意圖。 請參照第2圖，首先，提供一導線架200，作爲承載 器之用，其包括一晶片座202與接腳204。部分接腳204 向下折彎，形成一表面高度較低之第一平面206與一表面 6 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 1 ------------,λμ,--------訂---------線· 請先閱讀背面之注意事項再填寫本頁) 594964 A7 經濟部智慧財產局員工消費合作社印製 4 9 6 61 \ν Γ. d 〇 c / Ο Ο 6 __JB7 五、發明說明（<) 高度較高之第二平面208。將部分接腳204下凹可利於晶 片的打導線步驟，當然熟習該技術者應知此下凹結構並非 絕對必要。 第一晶片210之正面212具有金屬製的銲墊214，焊 墊214的作用係用以作爲第一晶片210對外的接點，典型 係以鋁做成。第一晶片210以具有焊墊214的一面212與 晶片座202的表面216黏合在一起。本發明改變對導線架 的設計’晶片座202之表面216的面積小於第一晶片210 之表面212的面積，因此，黏合後第一晶片210表面212 上的銲墊214將會暴露出來。其黏合例如是使用晶片接合 材料(adhesive)218固定在一起，典型係採用環氧樹脂（epoxy) 來黏合，亦可利用接合膠帶（adhesive tape)來固定。 在固定之後，利用導線(wire)220，將第一晶片210上 的各個焊墊214 —個一個的電性連接至與各個焊墊214相 對應並具有較低之第一平面206的接腳204上。 第二晶片222則以沒有焊墊223的一面224，與晶片 座202的另一表面226黏合在一起，其例如是使用晶片接 合材料228固定在一起，典型係採用環氧樹脂來黏合，或 利用接合膠帶來固定。第一晶片與第二晶片210、222可 以爲相同功能之晶片，比如DRAM晶片；亦可以爲不同的 晶片，比如記憶體晶片、邏輯元件晶片、快閃記憶體晶片 等。 同樣的，在固定之後，利用導線225，將第二晶片222 上的各個焊墊223 —個一個的電性連接至與各個焊墊223 7 ^ ? 旛 -------------- I------^---— — — — — — —----I--- (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A.〗規格（210 X 297公釐） 594964 A7 4966twr.doc/006 B7____ 五、發明說明（G ) 相對應且具有較低之第一平面206的接腳204上。 (請先閱讀背面之注意事項再填寫本頁) 將部分接腳204下凹除了可使第一晶片210打導線時 更容易連接，且使整個的晶片組能固定於封裝結構的中間 部分。 接著，利用封裝材料(packaging material)230，將第一 晶片210、第二晶片222、導線220、225、以及部分接腳204 封住，其中具有第一平面206的接腳204與部分具有第二 平面208的接腳204均被包覆住。如此，除了可以固定各 元件彼此之間的相對位置外，亦可以防止濕氣進入。被封 裝材料230包覆的部分內腳204即爲接腳204之內腳部分 232 ’而未被包覆的爲接腳204之外腳部分234。 接腳204之外腳部分234由封裝材料230的側面伸出， 並向下彎折’連接到印刷電路板（printed circuit board， PBC)236 上。 經濟部智慧財產局員工消費合作社印製 本發明之多晶片封裝結構係將兩片以上的晶片封裝在 一起，可在增加有限的成本中增強晶片的效能。以動態隨 機存取記憶體（dynamic random access memory，DRAM)爲 例’一顆64百萬位元的DRAM的價格約爲一顆128百萬 位元的DRAM的價格的三分之一，甚至不到三分之一。因 此’將兩顆64百萬位元的DRAM封裝在同一個封裝結構 中’則不但可以具有128百萬位元的DRAM的效能，且價 格增加極爲有限。 而且，本發明較佳實施例中將兩片晶片封裝在一起， 若應用於DRAM產品時，其記憶體的密度倍增，即64百 8 規格（210 x 297公釐） 本紙張尺度_中Θ IS家標準（CNS)A4 594964 A7 B7 49661 w Γ. doc/006 五、發明說明（7) 萬位元直接升級爲128百萬位元，如此不僅提升了元件的 積極度，而且可於不需對晶元重新設計、製作的情況下’ 使記憶體達到雙倍的效能。由於不需重新設計、製作晶元’ 因此本發明可快速的切入市場。同時由於縮短晶片間的距 離，可以提高訊號傳輸速率，提高元件效能。 本發明的晶片封裝結構也可應用於邏輯元件、快閃記 憶體或其他元件上’將具有不同功能的晶片封裝在一起’ 可增強其功能。 再者，由於本發明使用比晶片面積小的晶片座作爲承 載器，當第一晶片固定於晶片座上時’第一晶片可以以具 有銲墊之表面與晶片座之表面黏合，且將銲墊暴露出來， 如此，僅需將第一與第二晶片以相同的方向擺放，便不會 有連接用的導線纏繞在一起的情形發生’因此晶片上的銲 墊不需做鏡像重新排列（mirror re-distribution)，或者增加 interposer ， 亦即晶片本身不需作任何其他的處理，僅需使 用同一規格的晶片’成本花費低。 此外，本發明之多晶片封裝結構’以現有的封裝技術 即可做到，極適合廠商的生產安排。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明’任何熟習此技藝者’在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾’因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 9 表紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) -裝--------訂---------線秦 經濟部智慧財產局員工消費合作社印製V. Description of the invention (¥) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 108, 220, 225 · Leads 110, 204: Pins 112, 230: Packaging materials 206, 208: Plane 212: Surface of the first chip 210 216, 226: Surfaces 218, 228 of the wafer holder 202: Wafer bonding material 224: Surfaces of the second wafer 222 232: Inner pin portion 234 of the pin 204 ·· Outer pin portion 236 of the pin 204: Printed circuit board embodiment The old-style chip packaging structure has only one chip inside, and its function will be limited. In order to respond to the demand for enthusiasm, the present invention proposes a multi-chip packaging structure. By changing the design of the lead frame, the specific chip surface area is adopted. Small chip holder, which packs more than two chips together to improve its performance and density. In order to make the features and advantages of the present invention more comprehensible, the package structure of the present invention will be described in detail below by taking two packages as an example. FIG. 2 is a schematic diagram of a multi-chip packaging structure according to a preferred embodiment of the present invention. Please refer to FIG. 2. First, a lead frame 200 is provided as a carrier. The lead frame 200 includes a chip holder 202 and a pin 204. Part of the pins 204 are bent downward to form a first surface 206 and a surface 6 with a lower surface height. This paper size is in accordance with China National Standard (CNS) A4 (210 X 297 mm) 1 ------ ------, λμ, -------- Order --------- Line · Please read the notes on the back before filling out this page) 594964 A7 Employees ’Intellectual Property Bureau of the Ministry of Economic Affairs Consumption Cooperative printed 4 9 6 61 \ ν Γ. D oc / Ο Ο 6 __JB7 V. Description of the invention (<) The second plane 208 with a higher height. Recessing a portion of the pins 204 can be beneficial to the wire routing step of the wafer. Of course, those skilled in the art should know that this recessing structure is not absolutely necessary. The front surface 212 of the first wafer 210 has metal pads 214. The function of the pads 214 is to serve as the external contacts of the first wafer 210, and is typically made of aluminum. The first wafer 210 is adhered to the surface 216 of the wafer holder 202 with a side 212 having bonding pads 214. The present invention changes the design of the lead frame. The area of the surface 216 of the wafer holder 202 is smaller than the area of the surface 212 of the first wafer 210. Therefore, the bonding pads 214 on the surface 212 of the first wafer 210 will be exposed after bonding. The adhesion is, for example, fixed together using an adhesive 218, and typically epoxy resin is used for the adhesion, and it can also be fixed with an adhesive tape. After the fixing, each wire pad 214 on the first chip 210 is electrically connected to the pins 204 corresponding to the respective pads 214 and having a lower first plane 206 by using a wire 220. on. The second wafer 222 is bonded to the other surface 226 of the wafer holder 202 with one side 224 without the solder pad 223. For example, the second wafer 222 is fixed with a wafer bonding material 228, and is typically bonded with epoxy resin or by using Fix with adhesive tape. The first chip and the second chip 210 and 222 may be chips with the same function, such as a DRAM chip; they may also be different chips, such as a memory chip, a logic element chip, a flash memory chip, and the like. Similarly, after the fixing, each of the bonding pads 223 on the second chip 222 is electrically connected to each of the bonding pads 223 7 ^? 幡 ----------- --- I ------ ^ ---- — — — — — — — I --- (Please read the precautions on the back before filling out this page) This paper size applies to Chinese national standards ( CNS) A. Specification (210 X 297 mm) 594964 A7 4966twr.doc / 006 B7____ 5. Description of the invention (G) on the pin 204 corresponding to the lower first plane 206. (Please read the precautions on the back before filling in this page.) Removal of some of the pins 204 can make it easier to connect the first chip 210 when wiring, and the entire chipset can be fixed in the middle of the package structure. Then, using a packaging material 230, the first chip 210, the second chip 222, the wires 220, 225, and a portion of the pins 204 are sealed, wherein the pin 204 having the first plane 206 and a portion having the second pin 204 are sealed. The pins 204 of the plane 208 are all covered. In this way, in addition to fixing the relative positions of the components to each other, it is also possible to prevent moisture from entering. The part of the inner leg 204 covered by the encapsulating material 230 is the inner foot part 232 'of the pin 204, and the part not covered is the outer foot part 234 of the pin 204. The outer leg portion 234 of the pin 204 protrudes from the side of the packaging material 230 and is bent downward 'to be connected to a printed circuit board (PBC) 236. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs The multi-chip package structure of the present invention is to package two or more chips together, which can enhance the efficiency of the chip at a limited cost. Take dynamic random access memory (DRAM) as an example. 'The price of a 64 million bit DRAM is about one third of the price of a 128 million bit DRAM. To a third. Therefore, 'packaging two 64 megabit DRAMs in the same package structure' can not only have the performance of 128 megabit DRAMs, but the price increase is extremely limited. Moreover, in the preferred embodiment of the present invention, two chips are packaged together. When applied to DRAM products, the memory density is doubled, that is, 64-eight size (210 x 297 mm). Home Standard (CNS) A4 594964 A7 B7 49661 w Γ. Doc / 006 V. Description of the invention (7) The 10,000-bits are directly upgraded to 128 million-bits, which not only improves the enthusiasm of the components, but also eliminates the need for In the case of wafer redesign and production, the memory is doubled. Since there is no need to redesign and manufacture wafers', the present invention can be quickly cut into the market. At the same time, since the distance between the chips is shortened, the signal transmission rate can be increased and the component performance can be improved. The chip packaging structure of the present invention can also be applied to logic elements, flash memories, or other elements to 'package chips with different functions together' to enhance their functions. Furthermore, since the present invention uses a wafer holder having a smaller area than the wafer as a carrier, when the first wafer is fixed on the wafer holder, the first wafer may be bonded to the surface of the wafer holder with a surface having a pad, and the pad Exposed, so that only the first and second chips need to be placed in the same direction, there will be no situation where the connecting wires are entangled. Therefore, the solder pads on the chip do not need to be mirror-rearranged (mirror re-distribution), or increase the interposer, that is, the chip itself does not need to do any other processing, just use the same specifications of the chip 'cost is low. In addition, the multi-chip package structure of the present invention can be achieved with the existing packaging technology, which is very suitable for a manufacturer's production arrangement. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention to "any person skilled in the art" without departing from the spirit and scope of the present invention, and can make various modifications and retouches. The scope of protection of the invention shall be determined by the scope of the attached patent application. 9 The paper size of the table is applicable to China National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling this page) -Installation -------- Order ------ --- Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs

Claims (1)

594964 A8 496(m ’广 d(u'/〇〇6 1½ C8 DS 申請專利範圍 1· 一種多晶片的封裝結構，包括： 弟一晶片，包括一第一^表面 表面具有複數個第一銲墊； ~第二晶片，包括一第三表面與一第四表面，該第三 表面具有複數個第二銲墊； 一導線架，包括一晶片座與複數隻接腳，該晶片座具 有一第五表面與一第六表面，該第五表面貼附該第二表 面’該第六表面貼附該第三表面，且該晶片座之面積小於 該第二晶片，以暴露出該第三表面上之該些第二銲墊，該 些fe：腳均具有一內腳部分與一*外腳部分， 複數條導線，分別對應連接該些第一銲墊與該些第二 銲墊至該些接腳的內腳部分；以及 一封裝材料，包覆該第一晶片、該第二晶片、與該些 接腳的內腳部分。 2. 如申請專利範圍第1項所述之多晶片的封裝結構， 其中該第一晶片與該第二晶片相同。 經濟部智慧財產局員工消費合作社印製 一第二表面，該第一 (請先閱讀背面之注意事項再填寫本頁)594964 A8 496 (m '广 d (u' / 〇〇6 1½ C8 DS patent application scope 1. A multi-chip package structure, including: a first chip, including a first surface with a plurality of first pads on the surface ~ The second chip includes a third surface and a fourth surface, the third surface has a plurality of second pads; a lead frame includes a chip holder and a plurality of pins, and the chip holder has a fifth A surface and a sixth surface, the fifth surface is attached to the second surface, the sixth surface is attached to the third surface, and the area of the wafer holder is smaller than the second wafer to expose the third surface; The second pads, the fe: feet each have an inner foot portion and an * outer foot portion, and a plurality of wires are correspondingly connected to the first pads and the second pads to the pins, respectively. And a package material covering the first chip, the second chip, and the inner pin portions of the pins. 2. The multi-chip package structure described in item 1 of the scope of patent application, The first wafer is the same as the second wafer. Hui Property Office employees consumer cooperatives printed a second surface, the first (please read the note and then fill in the back of this page) 3. 如申請專利範圍第1項所述之多晶片的封裝結構， 其中該些接腳的內腳部分均經折彎使其尖端位於一第一平 面該第一平面接近第四表面，且該些導線係分別對應連接 該些第一銲墊與該些第二銲墊至該些接腳之內腳部分位於 該第一平面的尖端。 4. 如申請專利範圍第1項所述之多晶片的封裝結構， 其中該第一晶片與該第一晶片及該晶片座間更包括一晶片 接合材料層，用以固定該第一晶片與該第二晶片及該晶片 Μ氏適用中國國家標準（cns)A.丨规格（210x37公t) 594964 Λ8 1^8 4966l\v r.doc/006 ^ 1 Jo T、申請專利範圍 座。 5. 如申請專利範圍第4項所述之多晶片的封裝結構’ 其中該晶片接合材料層包括環氧樹脂。 6. 如申請專利範圍第1項所述之多晶片的封裝結構， 其中該第一晶片與該第二晶片及該晶片座間更包括一接合 膠帶，用以固定該第一晶片與該第二晶片及該晶片座。 7. 如申請專利範圍第1項所述之多晶片的封裝結構， 其中該些接腳之外腳部分用以連接至一印刷電路板上。 -----------裝--------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印¥ 本纸永4嗖適用屮闷阀家丨ΪΨ (CNS)Al規格（210x297公發）3. The multi-chip package structure described in item 1 of the scope of patent application, wherein the inner leg portions of the pins are bent so that their tips are located on a first plane, the first plane is close to the fourth surface, and the The wires are correspondingly connected to the first pads and the second pads to the inner leg portions of the pins at the tips of the first plane. 4. The multi-chip packaging structure described in item 1 of the scope of the patent application, wherein a wafer bonding material layer is further included between the first wafer and the first wafer and the wafer holder to fix the first wafer and the first wafer. The second chip and the M chip of this chip are applicable to the Chinese National Standard (cns) A. 丨 Specification (210x37mm t) 594964 Λ8 1 ^ 8 4966l \ v r.doc / 006 ^ 1 Jo T, the scope of patent application. 5. The multi-chip package structure described in item 4 of the scope of the patent application, wherein the layer of wafer bonding material includes epoxy resin. 6. The multi-chip packaging structure according to item 1 of the scope of the patent application, wherein a bonding tape is further included between the first chip, the second chip and the wafer holder to fix the first chip and the second chip. And the wafer holder. 7. The multi-chip package structure according to item 1 of the scope of the patent application, wherein the outer portions of the pins are used to connect to a printed circuit board. ----------- Installation -------- Order --------- line (Please read the precautions on the back before filling this page) Employees of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by Consumer Cooperatives ¥ This paper is always 4 嗖 Applicable to 屮 屮 Valve House 丨 ΪΨ (CNS) Al Specifications (210x297)
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