TW557637B - Data compression/decompression transmission circuit device having tri-state electrical characteristics - Google Patents

Abstract

The present invention is a data compression/decompression transmission circuit device having tri-state electrical characteristics, which compresses the two-bit data to be compressed into the data compression waveform having tri-state electrical characteristics through the hardware electrical characteristics, and provides a decompression method and circuit function of the data compression waveform having tri-state electrical characteristics. Its data compression method and circuit have the feature of low complexity, its execution speed increases due to the hardware electrical characteristics, so as to achieve the practical function of compression and decompression circuit.

Description

557637 V. Description of the invention (1) Technical field to which the invention belongs The present invention relates to a data compression / decompression transmission circuit device, and more particularly to a data compression / decompression transmission circuit device with three-state electrical characteristics. In the prior art, according to the general traditional data compression method, a complex calculation method sorted out after logical reasoning is used. The calculation method uses the characteristics of the data itself as the main parameter for statistics and arrangement. It does not use binary data 1 0 π 1π 1 1 and π Ο π 1 2 waveforms, as shown in the first figure, the electrical characteristics are the main parameters of compression and decompression. Therefore, the traditional data compression method must count and sort the characteristics of the data itself, and then process it through this calculation method. The functions of compression and decompression can be achieved, however, this is a rather complicated operation. The composition of the traditional compression and decompression circuit is to form its circuit according to the execution steps of the calculation method, or it can be directly executed on the platform of the computer environment by a computer program. However, the complexity of traditional data compression methods and circuit characteristics is high, and the cost and execution speed need to be improved by the relevant industry. SUMMARY OF THE INVENTION The main object of the present invention is to provide a data compression / decompression transmission circuit device with three-state electrical characteristics, and electrically convert the two-bit data to be compressed so that the section data is correspondingly compressed to the three-state electrical characteristics. Data compression waveform. A secondary object of the present invention is to provide a three-state electrical characteristic.

557637

V. Description of the invention (2)

The compression / decompression transmission circuit is set, and the compressed three-state electrical signal compression waveform is decompressed back to the second embodiment by electric inverse conversion. The second embodiment is shown in FIG. 7. The state-of-the-art electrical characteristics of the mine / decompression transmission circuit device generally includes a data compression transmission 1 0 0 face 50 and a data decompression transmission circuit 60 0. The system shown in the figure will Metadata 10, as shown in the first figure, is cut into a number of bit data sections 30 by a proportion of seven times, and as shown in the third picture, the bit, section 0, and section 3 0 Composed of the two bits of data, 102, 1, 1 "and all Hungarian 1 2 and other three bits' The segment 30 is the same before and after, the formula uses three bits as a cutting unit There is a data compression transmission circuit 50 'referring to the fifth and seventh figures, which has the function of compressing the bit data 10, which is received after the receiving system 1000 rotates to correspond to 7 data sectors 30. Using the electrical conversion method, the data of the segment data 30 is compressed into the output bit data segment 40, as shown in the fourth figure. The round-rotation, reduction transmission circuit 50 includes a compression logic device 51 and a three-state transmission path 52. The compression logic device 51 receives the bit data segment 30 from the round-in end of the data compression transmission circuit. The data control input terminal 521 of the three-state transmission buffer device 52 and the output of the input control device 51 are enabled, and the three-state transmission buffer device ^ is the output terminal of the data compression transmission circuit 50. The data solution Compression transmission circuit 60, as shown in FIGS. 6 and 7

D7637

The next ’is for checking the poor material into green yf and ^ Ojb Γ into binary data i. Κ 输 = reduced data 20 decompressed mirror circuits 62, 63 and a decomposed input stage 61, two currents ^ ^ ^ t ^ 5 Ο ^% Λ Λ 1〇 ^ 61 ^ ^ f ^ In the meantime, the current mirror circuits 641 and 641 of the current mirror circuits are connected to the input terminal 2 of the interpretation device 64 by Φ ▲ wheel :! With; = connect: receive the input end of the interpretation device 64, the output end of the circuit 60, and the output end connected to the data decompression transmission

Enter 彳 fr: one bit data 1 of Ϊ 资料 Ϊ is cut into each of the losers in the manner described above ΐ ϋ section 30, the input bit data section 3 〇 is sequentially input to The compression logic device 51, one of the compression logic device 51, data input 10 waveform input, adjusting the three-state transmission delay, a data control input terminal 5 2 1 and the enable control input terminal 2 # 'The output of the two-state transmission buffer device 5 2 is an output bit data section 40 which is a mark unit with the data compression waveform 20 of the three-state electrical characteristics adjusted. The input bit data section 3 0 in this embodiment is a two-bit data composed of a level "j" n, = level Π〇Π 12 and a level "丨" n: the compression logic device 5 1 Adjust the enabling control input 5 2 2 to be in a driving state. When the enabling control input 5 2 2 is in a driving state, the output of the tri-state transmission buffer device 52 changes linearly with its data control input 52. 'At this time, the compression logic device 51 outputs a data compression waveform 20 with three-state electrical characteristics composed of a negative half-cycle waveform 2 3 and a positive half-cycle waveform 2 1. As shown in the second figure, when zero The value 2 2 is generated when the compression

Page 8 557637 V. Description of the invention (4) 1st series ΐΓ 干 Ιϊί "control input 522 is in a cut-off state. At this time, the output terminal of ΐ j ϊ ί and the data control input terminal 521 become isolated complaints, and the material is compressed. The transmission circuit 50 can be three-state transmission. Ί 52 Set the data of the three-state electrical characteristics generated by the 52 hardware electrical characteristics. The value 22 of the voltage waveform 20 is 22, and the hardware electrical characteristic waveform of the zero value 22 is 1 = resistance. The state appears. In this way, the data compression transmission circuit 50 outputs the data compression waveform 20 of the data compression waveform 20 generated by the two-state transmission buffer device 52 hardware and the three-state electrical characteristics ^ 40 ° The above-mentioned input bit data section 30 uses three bits as a cutting unit to cut the two bit data. If the binary data representation is used to represent the amount of data change, eight data changes require three Single bit representation, please refer to the third figure. After the data compression transmission circuit 50, the sector data 30 is correspondingly compressed into the output bit data sector 4 by the electrical conversion method. As shown in the fourth figure, only two The data compression waveform 20 of the three-state electrical characteristics is a mark unit, and the clock cycle ^ is used to achieve the purpose of compressing one-third of the uncompressed data cycle. When it is to be decompressed into the two-bit data, the waveform is provided to provide When giving the system 1 0 0 'refer to the sixth and seventh figures, the input stage 6 1 receives the data compression waveform 2 0 of the three-state electrical characteristics through the input of the data decompression transmission circuit 60 0 as a mark The bit data section of the unit is 40. The input stage 61 is composed of transistors 612 and 614. The signal VI is connected to the gates of the transistors 612 and 6 1 4 to drive the transistors 6 1 2 and 6 1 4. Transistor 6 1 2 is connected between current mirror circuit 6 2 and an input node 6 1 6, while transistor 6 1 4 rhi mm Page 9 557637 V. Description of the invention (5) '' Connected to another current mirror circuit 6 3 and the input node 6 1 6. After the compressed bit data section 40 is input by the input node 6 1 6, please refer to ^ Four details of this data to decompress the transmission circuit 6 〇 The received bit data section 4 〇 is a combination of & _ negative half-period waveform 23 and a positive half-period waveform 21 Data compression waveform, the input stage 61 generates a pair of output control adjustment signals to the current mirror circuits 6 2 and 63 according to the received $ bits, and generates control adjustment signals to input the interpretation of the interpretation device 64 respectively. Terminal 64 丨 and 6 4 2 'Last' interpretation device 64 interprets to system 100 according to the level of the input control adjustment signal. The interpretation device 64, as shown in the sixth figure and the figure, includes a sum gate. Interpretation output L represents negative half-period waveform of negative potential 2 3. A mutually exclusive or gate interpretation output Z represents zero value of zero-potential waveform 2 2 signal and an inverse OR gate interpretation output Η represents positive half-period of positive potential Waveform 2 1. For example, when the negative half-period waveform 23 is input, a negative voltage turns on the transistor 6 1 connected to the input stage 61 and the current mirror circuit 62, and simultaneously turns on the input stage 61 and the current mirror circuit 6. 3 The connected transistor 6 1 4 is turned off, and the transistor is turned on or off to form a dual output control adjustment signal. At this time, the control adjustment signal is input to the current mirror circuit 6 2 through the transistors 6 1 2 and 6 1 4 respectively. 6 3, so that the current mirror circuits 6 2 and 6 3 respectively output a pair of high potential output voltage value adjustment signals to the input terminals 641 and 6 42 of the interpretation device 64. Since the input signals are all high potential, The output L of the gate is interpreted by the system 100, and then the system 100 executes the decompression program or adds an execution circuit decompression program to restore the two-bit data 10. The waveform is provided to the system 100. The above-mentioned input execution procedure of the positive half-cycle waveform 21 and the zero value 22

V. Explanation of the invention (6) The same is true. The positive half-period waveform 21 is the reverse of the positive / periodic waveform 21, and the zero value 22 is not solved by ϊΓΛ. The electrical output z table ~ the zero value 22 of the non-zero potential waveform. The times at which the gate is decompression # 60 are relative to the data decompression transmission circuit. So, the program of decompression and decompression is increased due to the low complexity of the characteristics of the hardware electrical circuit. &Quot; o'd and i have excellent compression characteristics, such as the traditional ν = but the N of the present invention, and the number of (high p and anti-state) "J 2-the pulse train can represent" 〇 · 丨 ~ ", The number of two sorrowful bursts: it can represent more than 1 large number and small ^ u nm shrinking / decompressing transmission circuit device has three states 气 ϊ ϊ ϊ ϊ ϊ The data is output by the system to At this end, the data of the hard characteristics of the input and compression / decompression transmission circuit device are compressed and decompressed, and the data is reduced and transmitted; the data of the software method is the fruit of the result. Multiplying compression effect transmission κ 2 The data compression / decompression of the three-state electrical characteristics of the present invention provides the three-state negative compression waveform for the two-bit 'electric delay characteristics to be compressed. 557637 5. Description of the invention (7) Electrical characteristics Data compression waveform decompression method and circuit function, data compression method and power The characteristics of low complexity and the execution speed are also enhanced by the hardware electrical characteristics to achieve the function of the compression and decompression circuit. 0 Page 12 557637 The diagram is a simple illustration to enable your reviewers to better understand the purpose and characteristics of the present invention. And functions, here is a preferred embodiment with the following drawings: The first diagram is a schematic diagram of the two-bit data waveform to be compressed in the embodiment of the present invention; the second diagram is the waveform of the three-state electrical characteristics of the present invention as a mark unit Schematic diagram; the third diagram is the waveform of the segment of the two-bit data in the first diagram; the fourth diagram is the waveform diagram of the compressed output bit data section of the present invention with the three-state electrical characteristics as the mark bit; the fifth diagram is this Schematic diagram of the data compression transmission circuit of the invention; Figure 6 is a schematic diagram of the data decompression transmission circuit of the invention; and Figure 7 is a data compression / decompression transmission circuit device with three-state electrical characteristics of the invention. ................. 10 Two-bit data level of 1 0 "Γ ......... 11 Two Bit data 1 0 level π 0 π ......... 12 Three-state electrical Compressed waveform ... 2 0 Waveform 2 0 Positive half-cycle waveform ......... 21 Waveform 2 0 Zero value ............... ......... 22 Negative half-period waveform of waveform 2 0 ... 23 Input bit data section ............... .... 30 Output bit data section ... 40

557637 Schematic description of data compression transmission circuit ... 50 compression logic device ... .... 51 Three-state transmission buffer device ... 52 Data control input terminal ... .... 521 enable control input ......... 522 data decompression transmission circuit ......... ... 60 Input stage ... 61 Transistor ... ............ 612 Transistor ............ ..... 614 Input Node .............. 616 Current Mirror Circuit .. ......... 62 Current Mirror Circuit ... ... 63 Interpreting device ......... 64 Inputs ... ............... 641 Input ... ...... 642 system ...................................... 100

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Claims (1)

557637 Repair core Mir. VI. Patent application scope 1. A data compression / decompression transmission circuit with three-state electrical characteristics, including: a data compression transmission circuit, which compresses one or two bits of data into one by the electrical characteristics of the hardware Data with three-state electrical characteristics; and a data decompression transmission circuit that uses the different potentials of the three-state electrical characteristics to decompress the data with three-state electrical characteristics. The circuit of item 1 of the profit range, wherein the data wave of the three-state electrical characteristics, the two digits, and the zero characteristic of the data as described in the data. 3. If the road device is completed, the two should be used to compress the data. 4 If the circuit is installed in one of the circuits, the special waveform is composed of a positive half-cycle waveform and a negative half-cycle waveform. The three states The data compression waveform of the electrical characteristics is generated by the hardware. It provides three different functions of data compression waveform characteristics. _ Please press the compression bit and the second one. Please input the three-state integer signal input by the package. The circuit of item 1, wherein the data compression transmission circuit is a compression logic device connected to a tri-state transmission buffer device and a group of logic devices receives the two-bit data to be compressed, and adjusts the data waveform output of the tri-state transmission buffer device, The reduction transmission circuit device uses the electrical characteristics of the hardware circuit, and the bit data becomes the data with the three-state electrical characteristics. The circuit of item 1 of the profit range, wherein the data is decompressed and transmitted including: stage, receiving the data with three-state electrical characteristics, generating a pair of control-regulated first current mirror circuits according to the potential of the data waveform of the electrical characteristics, and according to the Dual control adjustment signal generation Page 15 557637 6. The first signal in the patent application scope; a second current mirror circuit that generates a second signal based on the dual control adjustment signals; and an interpretation device that interprets the level of the first and second signals The data with the three-state electrical characteristics is compressed to become the binary data. 5. The circuit of item 4 in the scope of patent application, wherein the input stage is converted into the dual-control adjustment signal by different signal state changing characteristics of the compressed waveform based on the data of the three-state electrical characteristics. 6. The circuit of item 4 in the scope of patent application, wherein the input stage is formed by connecting two MOS transistors in series. 7. The circuit of claim 4 in which the interpretation device includes an AND gate, a mutually exclusive OR gate and an anti-OR gate connected to the first and second signals, respectively. Page 16