TW554509B - Multi-chip module - Google Patents

Abstract

A multi-chip module comprises an upper layer chip carried on a connection substrate, a lower layer chip carried on a base substrate, and an intermediate substrate clamped between the connection substrate and the base substrate, wherein the connection substrate is installed on the base substrate. The base substrate includes a first assembling pad, a second assembling pad located on the upper surface of the base substrate, and a third assembling pad located on the lower surface of the base substrate, wherein the third assembling pad is electrically connected to the first assembling pad and the second assembling pad. The lower layer semiconductor chip is electrically connected to the first assembling pad and shielded in a first molding compound. The connection substrate has a set of connection pads formed on its lower surface. The upper layer semiconductor chip is formed on the upper surface of the connection substrate and electrically connected to the connection pad on the lower surface of the connection substrate. A second molding compound encapsulates the upper layer chip. The intermediate substrate is provided to electrically connect the connection pads on the lower surface of the connection substrate to the second set of connection pads on the upper surface of the base substrate. The intermediate substrate has an opening for accommodating the lower layer chip. The minimum vertical distance between the connection substrate and the base substrate is larger than the maximum cross-section height of the first molding compound.

Description

554509 5. Description of the invention (1) [Field of the invention] The present invention relates to a multi-chip package structure (muni-chip: d; le, MCM) 'It is particularly related to-a stacked multi-chip package structure [prior art] A

As electronic products become thinner and thinner, the packaging structure used to protect and provide external circuit connections is also lighter, miniaturization and increased demand for high operating speeds. More and more attractive. The multi-chip package structure can be combined with ":: one or two or more chips (such as a processor (㈣⑶" memory and related logic unit (10 gic)) f

In the package structure, '纟 minimizes the speed limit of the system. In addition = reduce the length of the inter-chip Scher circuit and reduce the signal. The most common multi-chip package structure is a side-by-sid chip package structure, which installs two or more chips side by side on a single chip. Mounting surface. One of the chips and the conductive lines on the common substrate is achieved by wire bonding. However, the disadvantage of this side-by-side chip package structure is that the packaging efficiency is too low, because of the common board The area will increase with the increase in the number of wafers. Therefore, the semiconductor industry has developed a stacked wafer package structure 100, which generally includes two wafers 11 and 13 stacked on each other (as shown in the first figure). The wafer 110 is fixed on a substrate 15 with an adhesive layer 112. 554509 5. The surface of the invention (2). An adhesive layer 132 is provided between the wafers 110 and 130. The wafers 110 and 130 are respectively bonded with bonding wires. (Bond ng wi re) 11 4, 1 34 A plurality of wire-bonding pads 152 electrically connected to the upper surface of the substrate 150. A plurality of solder balls are provided on the lower surface of the substrate 150. Pads 1 5 4 which are electrically connected to A plurality of wire bonding pads on the upper surface of the substrate 150 are provided. Each of the solder ball pads 154 is provided with a solder ball 156 for electrically communicating with the outside world. The wafers 110 and 130 and the bonding wires 114 and 134 And a portion of the upper surface of the substrate 150 is covered with a colloidal 160. However, when the stacked wafer package structure 〇Q has the same stacked wafers, the upper wafer 13 will block the lower wafer 11 0. In addition, the length and height of the bonding wire 134 used to connect the upper wafer J 3 0 to the substrate 150 wire bonding pad 152 to the ground, plus' this will increase the difficulty of the wire bonding operation. For example, the more difficult The longer and higher path type of the wire is, the easier it is to break the wire during wire bonding, and the easier it is to cause wire sweep when encapsulating the gel. Furthermore, the more = the more: the more the path type Wires and stacked wafers require a high degree of dryness, which is sufficient to cover the wires and stacked wafers, thereby reducing packaging efficiency. In addition, several wafers are placed in a single package with additional The more rural the chip, the more likely it is ,,. These defects include "good bare crystals" 线. Because the wafer line is bonded to the substrate and asked: It is not easy to confirm whether the wafer is intact and free of defects. There is a 内 女 θ in the device structure. μ l Ge Guoxi's Japanese-Japanese film Feng Fu xe 虿 If one Japanese-Japanese film is defective, the entire Feng Meng is wrong, provoked, and judge

Abandon. Therefore, although the multi-chip package structure provides many:

〇-177.ptd Page 5 554509 V. Description of the invention (3) The yield is often greatly reduced due to the increase in the probability of defects. SUMMARY OF THE INVENTION Therefore, the main object of the present invention is to provide a multi-chip package structure with a low thickness, which can overcome or at least improve the problems of the foregoing prior art. According to the multi-chip package structure of the present invention, it mainly comprises an upper layer wafer carried on a connection substrate and a lower layer wafer carried on a recess of a base substrate, wherein the connection substrate is mounted on the upper surface of the base substrate. The base substrate includes a first group of pads located in the recess, a second group of pads located outside the recess on the upper surface of the base substrate, and a third group of pads located on the lower surface of the base substrate. It is electrically connected to the first group of pads and the first and second terminals. d is electrically connected to the first set of pads in the lower layer of the base substrate recess and is covered in a first sealant. The connection substrate is provided with a second set of connection pads on a lower surface thereof for electrical connection to the base substrate. The upper semiconductor wafer is a connection pad provided on the connection substrate and electrically connected to a lower surface of the connection substrate. A second body covering a is on the upper wafer of the connection substrate. Since the upper layer wafer and the lower layer wafer can be independently packaged and tested, the connection substrate is mounted on the upper surface of the base substrate, so the problem of "known good die" can be solved, and the number of chips can be reduced. The difficulty of the chip package structure test can greatly increase the yield of the multi-chip package structure of the present invention. In addition, it is worth noting that the connecting plate ^ is provided on the upper surface of the base substrate so that the distance between the connecting substrate and the recess is greater than the maximum cross-sectional height of the first sealant.

Page 6 POO-177.ptd 554509 V. Description of the invention (4) Multi-chip sealing structure with low profile. In order to make the above-mentioned and 1 features of the present invention obvious, the present invention is enumerated below in comparison with the following examples: special features: advantages can be more clearly explained in detail as follows. Through the yoke example, and in conjunction with the attached diagram, [Explanation of the Invention] Referring to the second figure, it reveals that according to the chip package structure 200, the main board J Λ is a multi-connection substrate 220 and a lower embodiment of the preferred embodiment. Acoustic crystal upper layer wafer 210 is carried on a contiguous 24nfl Xi Guangbugan Japanese film 23 is carried on a recess of a base substrate 240; inside: the base substrate 24 ° includes a first group of pads 242 provided on the recess ㈣ 4-position base substrate The recessed portion 246 on the surface is located on the lower surface of the bottom substrate.彳 Understand = Several conductive lines (not shown) are provided in the base substrate 24 to provide electricity between the second group of pads 246, the first group of pads 242, and the second group of pads 2 4 4 Sexual connection. The connection substrate 2 2 0 is provided with a set of connection pads 2 2 2 on the lower surface, and two sets of connection pads 224 on the upper surface. It can be understood that a plurality of conductive lines (not shown in the figure) are provided in the connection substrate to provide the electrical connection between the connection pads 22 and 24. The core iayer can be made of glass fiber reinforced BT (bismaleimide-triazine) resin, or FR-4 glass fiber reinforced epoxy resin (fibergiass reinformed epoxy resin). In addition, the substrate may be a ceramic substrate. First, the wafer 230 is set in a recess 240a of the base substrate 240 using a die attach mater, and then a bonding wire (such as a gold wire) is bonded to a wafer pad of the wafer 230 by a wire bonding machine and the first

P00-177.ptd Page 7 554509 V. Description of the invention (5) Group of pads 242. Then, the wafer 230 is sealed in a piece of colloid 232 by a conventional transfer molding method. It can be understood that the encapsulant 232 can also be formed by a top mass process (giOb-Trop prcess). 3 Then, the wafer 210 is affixed to the upper surface of the connection substrate 2 20, and then bonded to the wafer pad of the wafer 2 10 and the connection pad 2 2 4 with a fresh wire (for example, a gold wire). Finally, the wafer 21 is sealed in the sealing compound 2 12. It can be understood that the semiconductor wafer 210 or 230 can also be electrically connected to the conductive line on the substrate by other conventional techniques (such as flip-chip or tape-and-tape (TAB)).

Preferably, the upper-layer chip 210 and the lower-layer chip 230 can be individually packaged and tested, and then the connection substrate 22 is mounted on the upper surface of the base substrate 240. It is worth noting that the connecting substrate 22 is installed on the upper surface of the base substrate 240 so that the minimum vertical distance between the connecting substrate 22 and the recessed portion 24a is larger than the maximum cross-sectional height of the sealing body 232. As shown in the second figure, the connection pads 222 on the lower surface of the connection substrate 220 are electrically connected to the second group of connection pads 244 on the upper surface of the base substrate 240 through a plurality of solder balls 25 $. In contrast, referring to the third figure, it discloses a multi-chip package / molding 300 according to a third preferred embodiment of the present invention, which is characterized in that the connection pads 222 on the lower surface of the connection substrate 22 are formed by a plurality of pillars. The solder bumps 26 are electrically connected to the second set of pads 244 on the upper surface of the base substrate 240. This columnar solder bump 26 is preferably formed by wedge printing (s t en c i 1 p r i n t i n g). Refer to the fourth figure, which discloses a multi-chip package structure 400 according to a third preferred embodiment of the present invention, which is characterized in that the connection substrate 22o utilizes an anisotropic conductive layer adhesive film

554509 5. Description of the Invention (6) (ACF)) 270 is bonded to the upper surface of the base substrate 240. The connection pad 222 on the lower surface of the connection substrate 220 is provided with a plurality of metal bumps 272. The car bumper is preferably a stud bump formed by a conventional wire bonding technique. ). It can be understood that 'the plurality of metal bumps 272 may also be provided on the upper surface of the base substrate 240 as a second set of pads 2 4 4. The metal bump 2 72 is electrically connected to the corresponding second group of pads 2 4 4 by using an anisotropic conductive adhesive layer 2 70. It is known that the anisotropic adhesive suitable for forming the anisotropic conductive adhesive layer 270 is a Γζ-axis anisotropic adhesive, which is filled with low-concentration conductive particles 27〇a and is placed on the xy plane. They will not contact each other. Therefore, compressing the anisotropic conductive adhesive layer 2 70 in the z direction will cause the metal bump 272 to be electrically connected to the corresponding second set of pads 2 4 4 by 27 tons of conductive particles. Referring to the fifth figure, it is disclosed that a multi-chip package structure 500 according to a fourth preferred embodiment of the present invention is characterized in that the lower surface of the base substrate 241 further includes a recess 240b. The multi-chip package structure 500 further includes a semiconductor chip 280 disposed in the recessed portion 240b and electrically connected to a fourth group of pads 248 in the recessed portion 24Gb of the lower surface of the base substrate. It can be understood that; ^^ Several conductive lines (not shown in the figure) are cleverly used to fix the j r ° in the base substrate 241 to provide electricity between the fourth group of pads 248 and the third group of pads 246. Sexual connection. The half wafer 280 is coated in a colloid. Please refer to the sixth figure, which discloses a chip package structure 600 according to the present invention, which is characterized in that the right person is an example ^ ^ ^, 〇〇n The text is provided with an interposer substrate 290 sandwiched between the connection substrate 220 The minimum vertical distance between the base plate 241b and the base plate 241b M ^ & connecting soil plate 220 to take 『M 1 distance is greater than the maximum P00-177.ptd page 9 554509

With a large cross-section height, the interposer substrate 290 has an opening for receiving the semiconductor wafer 230. It can be understood that the interposer substrate 290 is provided with a set of interposer pads 292 on its upper surface, a set of interposer pads 294 under the | surface 'and a plurality of conductive lines (not shown in the figure). The board 290 is used to provide an electrical connection between the interposer pad 292 and the interposer pad 294. The connection substrate 220, the base substrate 241b, and the interposer substrate 29 are electrically connected by a plurality of solder balls 250. In addition, the electrical connection can also be provided by a columnar solder bump or an anisotropic conductive adhesive layer (AM). Please refer to the seventh figure, which discloses a multi-chip package structure 700 according to a sixth preferred embodiment of the present invention, which is characterized in that it includes an upper-layer wafer 21 borne on a recess 296a of a connection substrate 296 and a lower-layer wafer 23 borne on A recessed portion 240 a of a base substrate 240. The connection substrate 296 is provided with a set of connection pads 296b outside the recessed portion 296a on its lower surface, and a set of connection pads 296c inside the recessed portion 296a on its lower surface. It can be understood that a plurality of conductive lines (not shown) are provided in the connection substrate 296 to provide electrical connection between the connection pad 29 讣 and the connection pad 296c. It is worth noting that the connection 296 is installed on the upper surface of the base substrate 240 so that the minimum vertical distance between the concave portion 296a of the connecting substrate 296 and the concave portion 24a of the base substrate 240 is greater than the maximum of the sealing bodies 232 and 214. Section height. The multi-chip package structure according to the present invention can be mounted on a substrate, such as a printed circuit board, using solder balls. It can be understood that the first group of connectors 246 at the bottom of the package structure can also be printed with a solder paste before being mounted on the substrate. According to the multi-chip package structure of the present invention, since the upper chip and the lower chip

554509

Although the present invention has been formulated with the foregoing description, anyone skilled in this art will not: the hedge = $ is not intended to be used within a limited range. Various changes and modifications can be made without departing from the spirit of the invention and the chip packaging structure. Constructed with two layers ^. For example, the multi-chip multi-chip package structure according to the present invention can be used as the second preferred embodiment. However, according to the present invention, the scope of protection of the present invention should be regarded as a package structure with three or more layers. Prevail. Commanded as defined by the scope of the patent application

554509 Brief description of the diagrams [Illustration] Figure 1 · Brake view of a conventional stacked chip package structure; Preferred embodiment of a multi-chip package structure Figure 2: Sectional view according to the present invention; Figure 3: Based on A cross-sectional view of a multi-chip package according to a second comparative embodiment of the present invention; a multi-chip package structure of a preferred embodiment. FIG. 4... According to a third cross-sectional view of the present invention; FIG. 5: a fourth preferred embodiment according to the present invention. A cross-sectional view of a multi-chip package structure; FIG. 6 ··· A cross-sectional view of a multi-chip package structure according to a fifth preferred embodiment of the present invention; and πfu k Fig. 7: a sixth preferred embodiment of the present invention Sectional view of a multi-chip package. 、 W [Illustration of drawing number] 100 stacked wafer package structure 110 wafer 112 adhesive layer 114 bonding wire 130 wafer 132 adhesive layer 134 fresh line 150 substrate 152 wire bonding pad 154 solder ball pad 160 sealing compound 200 multi-chip package structure 210 chip 212 Colloid g

POO-177.ptd Page 12 554509 Brief description of the diagram 220 Connection substrate 222 Connection pad 224 Connection pad 230 Chip 232 Sealant 240 Base substrate 241 Base substrate 241b Base substrate 240a Recess 240b Recess 242 Pad 244 Pad 246 Pad 248 Pad 250 Solder ball 260 Columnar solder bump 270 Anisotropic conductive adhesive layer 270a Conductive particle 272 Metal bump 280 Semiconductor wafer 290 Intermediate substrate 292 Intermediate pad 294 Intermediate pad 296 Connection substrate 2 9 6a Recess 296b Connection pad 296c Connection pad 300 multi-chip package structure 400 multi-chip package structure 500 multi-chip package structure 600 multi-chip package structure 700 multi-chip package structure

Φ

POO-177.ptd Page 13

Claims (1)

554509 lS ^ 9〇l〇i597 Sixth, the scope of the application for the patent is to amend the columnar welding: the columnar solder bumps are connected to the base substrate in bulk, and the large blocks are formed by stencil printing. The substrate is a multi-chip package structure according to item 1 of the patent, which is the connection board. 、、 / 、 Square conductive adhesive layer (ACF) is electrically connected to the base Page 15