TW522471B - Method of correcting a mask layout - Google Patents

Abstract

A method of correcting a mask layout is provided. The mask layout includes a plurality of element patterns. An inspection program is executed to classify the element patterns of the mask layout into a plurality of element pattern types according to a pattern density of the element patterns. Following this, each of the element pattern types is corrected.

Description

522471 V. Description of the Invention (l) Field of the Invention The present invention provides a method for correcting a mask layout, especially a method for correcting a systematic error generated when a mask layout is subjected to pattern transfer. Background description In order to integrate circuits, foundry, a layout pattern of a photometer must be made first, and the pattern on the photomask passes through the photoresist on the semiconductor wafer, and the area on the sheet is not covered by the photoresist. To remove. Therefore, the image on the photomask is first transferred to the photoresist, and then to the process. It can be said that the pattern on the photomask is passed through the lithographic wafer in the semiconductor process. It has become a research integrated circuit for forming a designed integrated circuit. A semiconductor mask is formed on the photomask and developed by photolithography. After being transferred to a certain ratio, it is transferred to a semiconductor crystal by an etching process, such as silicon or silicon. Silicon oxide, etc., uses two processes: lithography and engraving on semiconductor wafers. So lithography and etching are two very important processes, so how to accurately transfer the lithography process to the semiconductor process is very important. As the lithography process is used to transfer the mask pattern 5, the light layer is running at a high angle, and the corners of the mask pattern with high density are very equal to = 1, overexpose, or Underexposure causes well battles due to over- + approach effects

522471 V. Description of the invention (2) (optical proximity effect), which further affects the quasi-pain of pattern transfer. Therefore, the current solution is to use computer aided design (CAD) to perform an optical proximity correction (OPC) on the mask pattern to eliminate the optical proximity effect. However, in addition to the optical proximity effect, the photomask pattern may still be used in the etching process, because the element patterns designed on the semiconductor wafer have different pattern densities, which causes a micro-loading effect. Affects the uniformity of etching. Please refer to FIG. 1. FIG. 1 is a schematic diagram of a conventional photomask layout. As shown in Figure 1, the reticle layout diagram includes a plurality of linear element patterns A, B, and C having the same line width ¥, which are respectively used to define a word line (word 1 ine) or a bit line ( bit 1 ine) and other conductive areas. The line space s between the two element patterns A is defined as a, the line space s between the two element patterns b is defined as b, and the line distance s between the two element patterns C is defined as c, and the line The distances a, b, and c are not equal. In other words, the element patterns A, B, and C on the reticle layout chart have unequal pattern densities. Please refer to FIG. 2. FIG. 2 is an after-etch-inspection critical dimension (ΑΕΙ CD) obtained when the pattern is transferred to a semiconductor wafer by an etching process according to the mask layout shown in FIG. 1. A schematic diagram of the relationship between the line width w 'and the line spacing s. Where the vertical axis table

Page 5 522471 V. Description of the invention (3)

The line width of each element pattern on the photomask layout diagram after being transferred to the semiconductor wafer. The horizontal axis represents the line spacing between the element patterns on the photomask layout diagram. The hollow circle is a linewidth measurement. The black solid line is a line width approximation curve (fi 11 i ng curve) made by using numerical methods and various line width measurements. As shown in Figure 2, the etched line width w 'of each element pattern on the mask layout may be affected by micro-load or other system error factors, resulting in uneven etching. For example, the line width of each element pattern may be etched. As the line pitch increases, it means that the lower the pattern density and the more isolated the linear pattern, the greater the post-etching line width that can be obtained than the denser line pattern: the post-line width. Because in the traditional IC design of the 0.18 micron process, the micro-load effect is not a major factor in considering the overall uniformity of the semiconductor wafer, the etching unevenness caused by the micro-load effect is often ignored. However, with the reduction in the size of semiconductor devices and the increase in the degree of accumulation, the requirements for the uniformity of devices have become increasingly strict. Assuming that the micro-load effect can cause a line width error of 10 nanometers (narometer, nm), the error rate has reached 6%, 8% for 0.15, 0.1 3, or even 0.1 micron processes. Even 10%. So how to improve the surface uniformity of semiconductor wafers to increase production

Product yield has become an important issue for processes below 0.1 5 microns. SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a method for correcting a layout of a photomask.

Page 6 522471 V. Explanation of the invention (4) The method 'to effectively avoid the pattern deviation caused by the micro-load effect' is to first provide the element diagrams and element patterns on the mask layout, including the plural diagrams, and then proceed with the case. After detecting the patterns between the component patterns in the preferred embodiment of the present invention, a detection program is performed, and each component pattern is divided into a plurality of types of component patterns according to the density of the mask layout image. . Because the present invention can be modified according to the element pattern on the layout of the photomask that causes the micro-load effect, it can be appropriately modified ... This can effectively modify the 4 degree of conductivity, especially can improve the MU U face sentence below 0.15 microns Detailed Description of Uniform Invention FIG. 3 is a flow chart of a method for modifying the reticle layout of the present invention to avoid the negative effects of the midwife. As shown in Figure 3b, the method of the present invention first proceeds to step 10, and provides a photomask to decorate a 4 mesh database. The gastric mask layout diagram contains a plurality of (linear) component patterns, which are used to define the conductive areas of different areas on the single-chip, such as the memory cell region and the logic circuit area (10 gic circuit region), such as word lines or bit lines, with different circuit design requirements, or used to define device patterns on multiple chips (mul ti_chip), and the database contains parameter data for each of the device patterns . 522471 V. Description of the invention (5) Since the micro-load effect is caused by the difference in pattern density between element patterns, the present invention then proceeds to step 20, provides a detection program, and calculates the pattern density of each element pattern. Classify, as shown in step 30, divide each element pattern into plural types of element patterns 32, 34, 36, 38, including the first type element pattern, the second type element pattern to the N-1 type element pattern, and the first N-type patterns and the like are also referred to as dense patterns, sub-dense patterns, semi-dense patterns, and isolated patterns, and the like. Subsequently, as shown in step 40, different types of component widths are compensated and corrected according to the classification results. For example, a first fixed value correction 42 is performed for the first type of element pattern 32, a second fixed value correction 4 for the second type of element pattern 34, and an Nth- 1 fixed value correction 46, and performing an N fixed value correction 4 8 on the Nth type element pattern definition 8. Finally, step 50 is performed to synthesize the correction values and output a mask layout diagram including the pattern of each correction element, thereby completing the mask pattern correction of the present invention. Please refer to Figure 4 for the revised mask layout. Figure 4 uses line-width component patterns A, B, and C shown in Figure 1 as examples to perform line-width correction, that is, for components with lower pattern densities, respectively. The patterns A and B are reduced in line width to different degrees to form element patterns A ′ and B ′, respectively. In addition, in other embodiments of the present invention, the line width correction may also be performed according to each element pattern.

Page 8 522471 V. Description of the invention (6) The pattern density determines whether to increase or decrease its line width.

As shown in Figures 5 and 6, after the micro-load correction of the element patterns A 'and B' of the present invention after pattern transfer, the obtained line width values after etching will fall within a reasonable line width range (such as 1 2 6 to 1 3 2 nanometers), and further reduce the difference between the line width after etching of the element pattern C (between 1 2 3 to 1 3 3 nanometers), and the present invention is micro-loaded. After the correction, the overall line width deviation value can be reduced to 5-6 nanometers, which is far lower than the traditional etching deviation value of up to 15 nanometers without micro-load correction, so it is compared with the traditional mask without micro-load correction. According to the layout diagram, the present invention can effectively improve the etching uniformity of a semiconductor wafer.

The feature of the present invention is mainly to classify each element pattern according to the pattern density of each element pattern on the photomask layout drawing, and then perform an isoline width correction for each element pattern in the same type of element pattern. The pattern density on which the present invention is based can be determined by the line spacing between two linear patterns. For example, the order of the pattern a, b, and c determines the order of the pattern density of the element patterns A, B, and C, and their corresponding Line width correction value. In addition, the pattern density can also be determined by any other method that can distinguish dense patterns or isolated patterns. For example, the line width w of a linear pattern is divided by the line spacing s between two adjacent linear patterns to obtain the two-element pattern A. The formula for calculating the pattern density d = w / a. In addition to dividing each element pattern according to the pattern density of each element pattern

Page 9 522471 V. Description of invention (7) In other embodiments of the present invention, the critical line width deviation data of each element pattern after pattern transfer (etching process) can also be directly used to perform the element pattern classification. That is to say, the present invention can also use the relationship diagram of line width and line pitch after etching to set a plurality of line pitch ranges, and at least classify each element pattern into a dense pattern, a semi-dense pattern, and an isolated pattern. Equivalent line width correction of each element pattern in the same category ° Compared with the conventional method of correcting the mask layout, the present invention performs a component pattern on the mask layout according to the pattern density that causes the micro-load effect. Classification, and appropriate correction of various element patterns, so can effectively improve the surface uniformity of semiconductor wafers, especially can improve the yield of products below 0.1 5 microns. The above description is only a preferred embodiment of the present invention \ Every equivalent change and modification made in accordance with the scope of the patent application for the present invention shall fall within the scope of the patent of the present invention.

522471 Simple illustration of the diagram Simple illustration of the diagram Fig. 2 is a schematic diagram showing the relationship between the line width and the line pitch after etching in one of the conventional photomask layout drawings. FIG. 3 is a flowchart of a method for modifying a photomask layout of the present invention. FIG. 4 is a schematic diagram of a photomask layout modified according to the method of the present invention.

Fig. 5 is a comparison diagram of the line width after etching with micro-load correction according to the present invention and the line width after etching without conventional micro-load correction. Fig. 6 is a comparison chart of the line width deviation value after the micro load correction of the present invention and the conventional line width deviation value without the micro load correction. Explanation of symbols in the diagram 10 ~ 50 Correction of mask layout steps A, B, O A ,, B, component pattern a, b ^ c Line pitch W Line width

Page 11

Claims (1)

522471 6. Scope of patent application 1. A method for modifying a mask layout, the mask layout includes a plurality of linear patterns, and the method includes the following steps: providing each of the linear patterns in a pattern Line width deviation data generated during the transfer process; a detection program is performed to classify each line pattern into at least a first type line pattern and a second type according to the line width deviation data of each line pattern A linear pattern; and performing a first fixed value correction on the first type of linear pattern and a second fixed value correction on the second type of linear: pattern respectively. 2. The method according to item 1 of the scope of patent application, wherein the linear pattern of the first type and the linear pattern of the second type have different pattern densities. 3. The method according to item 2 of the patent application range, wherein the pattern density is determined by the space between two adjacent linear patterns. 4. The method according to item 1 of the scope of patent application, wherein the line width deviation is caused by a systematic error (systematic e r r o r). 5. The method according to item 1 of the scope of patent application, wherein the line width deviation is caused by a micro- loading effect. 522471 6. Scope of patent application 6 · For the method of the first scope of patent application, the line width deviation is an after-etch-inspection critical dimension (ΑΕΙ CD) deviation value. 7. The method according to item 1 of the scope of patent application, wherein the first type of linear pattern is a dense or semi-dense pattern, and the second type of linear pattern is an isolated ( isolated) pattern. 8 · / The method according to item 1 of the scope of patent application, wherein the first type linear pattern f is an isolated pattern or a semi-isolated pattern, and the second type linear pattern is a dense pattern. And: the method of item 1 of the patent scope, wherein the first fixed value correction # 2 and the second fixed value correction include increasing the line width of each linear pattern or deleting the line width of the linear pattern. · The method used to apply for item 1 of Shen Qing's patent scope, in which each of the linear patterns is the meaning-conductive area. The system of Health 1 is the method of producing the first and the first error of a mask layout diagram during a pattern transfer process. The mask layout diagram includes a plurality of components ^ The method includes the following steps: λ — The detection program for the case's gatekeeper 'classifies each element pattern into a plurality of element patterns according to the pattern density of each element pattern N θ on the mask layout diagram; Page 13 522471 6. Scope of Patent Application and Correction for each type of component pattern. 1 2. The method according to item 11 of the scope of patent application, wherein each of the element patterns is a linear pattern. 1 3 · The method according to item 12 of the scope of patent application, wherein the correction of the pattern of each type of element includes increasing the line width of each linear pattern or deleting the line width of each linear pattern. 14. The method according to item 12 of the scope of patent application, wherein the pattern density is determined by the line spacing between two adjacent linear patterns. 15. The method according to item 14 of the scope of patent application, wherein each type of the element pattern includes at least a dense pattern, a semi-dense pattern, and an isolated pattern. 16. The method according to item 11 of the patent application scope, wherein the pattern density is determined by circuit design requirements. 1 7. The method according to item 16 of the scope of patent application, wherein each of these types of element patterns includes at least a memory cell region element pattern and a logic circuit region element pattern. 18. The method of item 11 in the scope of patent application, wherein Page 522 522471 Page 15