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TW483132B - Semiconductor package having lid member - Google Patents

Semiconductor package having lid member Download PDF

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Publication number
TW483132B
TW483132B TW090111431A TW90111431A TW483132B TW 483132 B TW483132 B TW 483132B TW 090111431 A TW090111431 A TW 090111431A TW 90111431 A TW90111431 A TW 90111431A TW 483132 B TW483132 B TW 483132B
Authority
TW
Taiwan
Prior art keywords
cover
substrate
semiconductor package
cover member
patent application
Prior art date
Application number
TW090111431A
Other languages
Chinese (zh)
Inventor
Jung-Shiun Lung
Yan-Juen Chen
Yun-Lung Tsai
Original Assignee
Siliconware Precision Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siliconware Precision Industries Co Ltd filed Critical Siliconware Precision Industries Co Ltd
Priority to TW090111431A priority Critical patent/TW483132B/en
Application granted granted Critical
Publication of TW483132B publication Critical patent/TW483132B/en

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

A semiconductor package having lid member is disclosed, which comprises a substrate for at least one chip pasted on the first surface thereof, and an electrical connection end is disposed on the second surface opposed to the first surface of the substrate for the chip to form electrical connection with the external device; an encapsulation to wrap the chip and part of the first surface of the substrate; a lid member to cover at least the first surface of the substrate, so that the second surface of the substrate exposes out of the lid member, and form at least a bump to touch the encapsulation and at least a venting hole on the lid member; and a thermal adhesive to glue the lid member to the first surface of the substrate. Since the disposition of the lid member bump touches the encapsulation, the relative height of the encapsulation to the lid member can be ensured to control the quality of the product thickness, and the required space by the thermal adhesive can be pre-reserved by controlling the height to prevent the flash of the thermal adhesive out of the lid member. At the same time, the venting hole formed in the lid member can vent the air between the thermal adhesive and the lid member in the process to prevent the flash at the instant when the air is compressed to eject the thermal adhesive, thus the production quality can be enhanced and the production operation can be improved.

Description

483132 經濟部智慧財產局員工消費合作社印製 1 A7 五、發明說明(1 / 【發明領域】: 本發明係有關一種具蓋件之半導體封裝件,尤指一 種作為多媒體卡(Multi-Media Card,MMC)之具蓋件之半 導體封裝件。 【背景技術說明】: 目前作為多媒體卡(MMC)之半導體封裝件,如美國 專利第6,040,622號案已揭示出一種如第4A圖所示之結 構。該種MMC半導體封裝件1,係包括於一基板之第 一表面100上黏設有至少一晶片u,並使該晶片u與該 基板10形成電性連接關係;且於該基板Μ之第二表面1 〇 1 上佈設有多數電性連結端12,以供該晶片u藉之與外界 裝置電性連接;又於該基板10上形成有一封裝膠體13用 以包覆住該晶片11及部份之該基板1〇之第一表面1〇〇而 與外界氣密隔離。該半導體封裝件1並具有一蓋件14, 其仰視圖及剖視圖係如第4B及4C圖所示。該蓋件μ形 成有一凹穴140用以覆蓋隹至少該基板1〇之第一表面 1〇〇,使該基板ίο之第二表面101外露出該蓋件14,並 以一熱融膠15黏接該蓋件14與該基板之第一表面 100 〇 然目刖生產之MMC半導體封裝件,於封膠模壓製程 (MoldmgProcess)中,如第4D圖所示,往往由於基板w 與封裝膠體13材質之不同,而導致因熱膨脹係數差異(CTE mis-match)使該基板1〇產生翹曲16 (Warpage)等現象,使 該基板10與蓋件14組裝後無法確實控制產品厚度,造成 16251 裝--------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 483132 A7 五、發明說明(2 , 檢測結果之不穩定性揾宾· v 1, 心/王杈阿,又該翹曲16使得該基板1〇與 該盖件14間之相對高j# 丁 ρ ^ 才门度不易控制,而無法有效控制熱融 膠1 5存在空間,故於製鋥中 表裎肀易形成該熱融膠15外溢之溢 膠17 (Flash)情形;再去,游一 殘留於該熱融膠15與該蓋件14 之間空氣無法排出造成空洞18(void),而於熱屋時易因 擠壓使得該线於瞬間喷出19而造成溢膠17。故該顧。 半導體封裝件易導致溢膠及產品厚度控制不易尊問題,不 但有損於產品之生產品f,亦造成現場作業之困擾。 【發明概述】: 本發明之目的即在提供一種具蓋件之半導體封裝 件,使得確保封裝膠體與蓋件之相對高I,以控制產品厚 度之品質要求,ϋ得藉由高度控制以㈣熱融膠厚度所需 之二間以防止熱融膠溢膠於蓋件外。同時,本發明之具 蓋件之半導體封裝件,得以讓殘存於熱融膠與蓋件間之空 氣於製程中順利排出,以防止因空氣被擠壓瞬間連帶熱融 膠噴出而造成溢膠。再者,本發明之具蓋件之半導體封裝 件,得以控制合理熱融膠用量,以符合基板與蓋件之接合 面積,使得以防止溢膠,並進一步確實控制封裝件組裝後 尺寸之精度,故得以提昇生產品質,並改善生產作業。 為達成上揭及其他目的,本發明之一種具蓋件之半 導體封裝件,係包括:一基板,其具有第一表面與第二表 面’於該第一表面上係佈設有多數之導電跡線,而於該第 二表面上形成有多數藉導電穿孔(C0nductive Vias)或連通 電路(Interconnecting Wires)與該等導電跡線電性連接之 16251 --------訂----- (請先閱讀背面之注意事項再填寫本頁) A7 B7 五、發明說明(3 ) 性連結端;至少一晶片,其係黏設至該基板之第一表面上; 多數銲線,用以電性連接該晶片與該等導電跡線;一封裝 膠體用以包覆該晶片、該等銲線、該等與該晶片電性連 (請先閱讀背面之注意事項再填寫本頁) 接之導電跡線及部份之該基板之第一表面;一蓋件,得以 ,脂化合物製成,係於其—表面上形成有-凹穴,用以覆 蓋住至少該基板之第一表面,使該基板之第二表面外露出 該蓋件,且於該凹穴形成有至少一凸起及至少一排氣孔, 其中該排氣孔係形成於該蓋件之凹穴之邊緣位置處;以及 熱融膠,得為環氧樹脂,係塗佈於該蓋件之凹穴内不影 響該凸起與該排氣孔分布之位置處,用以黏接該凹穴與該 基板之第一表面。 形成於該蓋件凹穴之Λ鈕在 、 八芝凸起係具有一高度小於該凹穴 之深度。同時,談凸起媒游士、 憨侍形成於該凹穴内對應該封裝膠體 佈局之位置處’並抵觸該封裝膠體與該凹穴内面相對之表 面;又該凸起得形成於該蓋件之凹穴内之中央位置處等非 _凹穴邊緣之位置處* 以下列舉實施例以推一 乂洋",田說明本發明,但本發 明並不受此等實施例所限帝】。 【圖式簡單說明】: 第1圖係本發明具苔杜* *、盆 蓋件之+導體封裝件之實施例之 剖視圖; 第2A圖係第1圖之笔姓483132 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 1 A7 V. Description of the Invention (1 / [Field of Invention]: The present invention relates to a semiconductor package with a cover, especially a multi-media card (Multi-Media Card, [MCC] semiconductor package with cover. [Background Description]: Currently, as a multimedia card (MMC) semiconductor package, such as US Patent No. 6,040,622 has revealed a structure as shown in Figure 4A. The A MMC semiconductor package 1 includes at least one wafer u adhered to a first surface 100 of a substrate, and the wafer u and the substrate 10 are electrically connected to each other; and on the second surface of the substrate M A plurality of electrical connection ends 12 are arranged on the 010 for the chip u to be electrically connected to an external device; and a packaging gel 13 is formed on the substrate 10 to cover the chip 11 and a part of the chip. The first surface 100 of the substrate 100 is air-tightly isolated from the outside. The semiconductor package 1 also has a cover 14 whose bottom view and cross-sectional view are shown in FIGS. 4B and 4C. The cover member μ is formed There is a cavity 140 The cover 14 is covered with at least the first surface 100 of the substrate 10, the cover 14 is exposed from the second surface 101 of the substrate, and the cover 14 and the first A MMC semiconductor package produced on a surface of 100 mm in the mold molding process (MoldmgProcess), as shown in Figure 4D, often due to the difference in the material of the substrate w and the packaging colloid 13 due to the difference in thermal expansion coefficient ( CTE mis-match) causes the substrate 10 to warp 16 (Warpage) and other phenomena, making the substrate 10 and the cover 14 unable to accurately control the thickness of the product after assembly, resulting in 16251 assembly ------ order- ------- line (please read the precautions on the back before filling this page) 483132 A7 V. Description of the invention (2, Instability of test results · Bin · v 1, Heart / Wang A, again The warpage 16 makes the relative height between the substrate 10 and the cover 14 difficult to control, and it is impossible to effectively control the space of the hot-melt adhesive 15. Therefore, it is easy to form the surface in the manufacturing process. The situation where the hot melt adhesive 15 overflows the flash glue 17 (Flash); then, go to the left to leave a space between the hot melt adhesive 15 and the cover 14 Can not be exhausted to cause voids 18 (void), and in hot houses, it is easy to squeeze out the line to spray out 19 in an instant and cause overflow glue 17. Therefore, it is necessary to consider. Semiconductor packages can easily cause overflow glue and product thickness control problems. It not only damages the product f, but also causes troubles in the field. [Summary of the Invention]: The purpose of the present invention is to provide a semiconductor package with a cover, so as to ensure the relative high I of the packaging colloid and the cover. In order to control the quality requirements of the thickness of the product, we have to control the thickness of the hot-melt glue by the height control to prevent the hot-melt glue from overflowing the cover. At the same time, the semiconductor package with the cover of the present invention allows the air remaining between the hot-melt adhesive and the cover to be smoothly discharged during the manufacturing process, so as to prevent overflow of the glue caused by the hot-melt adhesive being ejected immediately when the air is squeezed. Furthermore, the semiconductor package with a cover of the present invention can control a reasonable amount of hot-melt adhesive to conform to the joint area of the substrate and the cover, so as to prevent the overflow of the glue and further control the accuracy of the size of the package after assembly, Therefore, it is possible to improve production quality and improve production operations. In order to achieve the disclosure and other objectives, a semiconductor package with a cover according to the present invention includes a substrate having a first surface and a second surface. A plurality of conductive traces are arranged on the first surface. 16251 are formed on the second surface to electrically connect these conductive traces through conductive vias or interconnecting wires. -------- Order ----- (Please read the precautions on the back before filling this page) A7 B7 V. Description of the invention (3) Sexual connection end; at least one chip, which is glued to the first surface of the substrate; most bonding wires are used for electricity The chip is connected to the conductive traces; a sealing gel is used to cover the chip, the bonding wires, and these are electrically connected to the chip (please read the precautions on the back before filling this page). A trace and a part of the first surface of the substrate; a cover member made of a fat compound, a cavity formed on its surface to cover at least the first surface of the substrate so that the The cover is exposed on the second surface of the substrate, and is in the shape of the cavity. There are at least one protrusion and at least one exhaust hole, wherein the exhaust hole is formed at the edge position of the recess of the cover member; and the hot-melt adhesive is obtained as an epoxy resin and is coated on the cover member. Positions in the cavity that do not affect the distribution of the protrusions and the vent holes are used to bond the cavity and the first surface of the substrate. The Λ button formed in the recess of the cover member has a height smaller than that of the recess in the Bazhi protrusions. At the same time, talk about the raised media travellers and the servants formed in the cavity corresponding to the layout of the encapsulating colloid ', and abut the surface of the encapsulating colloid opposite to the inner surface of the cavity; and the protrusion must be formed on the cover. At the central position in the cavity, such as at the non-_cavity edge position * The following examples are given to push the ocean ", Tian explains the present invention, but the present invention is not limited by these embodiments.] [Brief description of the drawings]: Figure 1 is a sectional view of an embodiment of the present invention with mosquito *, basin cover + conductor package; Figure 2A is the surname of Figure 1

之盍件之仰視圖;第2B圖係第2A 圖沿2B-2B之剖面線圖.筮v q,第2C圖係本發明半導體 之另一蓋件之仰視圖,·第2D翩及妨 午 弟2D圖係第2C圖沿2D-2D之剖 16251 483132 五、發明說明(4 面線圖。 = &本發明實施例所制之熱《塗佈於 蓋件之凹八内之分布圖;以及 第4A圖係習知具蓋件之 4B圖係第4A圖之蓋 封襞件之剖視圖;第 沿—剖面線 基板翹曲及^加蓋過程之溢膠問題Μ知半導體封裝件之 ^元件符號說明】·· 1 半導體封裝件 10 100 第一表面 基板 11 晶片 101 第一表面 13 封裝膠體 12 電性連結 140 凹穴 14 蓋件 16 輕曲 15 熱融膠 18 空洞 17 溢膝 2 半導體封裝件 19 空氣噴出 20 基板 201 第二表面 200 第一表面 22 電性連結蠕 21 導電跡線 24 銲線 23 晶片 250 佈局 25 封裝膠體 26 蓋件 251 表面 2600 内面 260 凹穴 262 排氣孔 261 凸起 27 熱融膠 蠕 用⑽g家標準 210 X 297 訂 經 濟 部 智 慧 財 產 局 員 工 消 費 合 社 印 製 16251 483132 A7 "----—— —____ 五、發明說明(5 ) " " 【發明之詳細說明】: [實施例] (請先閱讀背面之注意事項再填寫本頁) 第1圖所示者為本發明具蓋件之半導體封裝件之實 施例之剖視圖。該實施例之具蓋件之半導體封袭件^包 括一基板20,其具有第一表面20〇,及與該第一表面^⑽ 相對之第二表面201,以習知方法如蝕刻等於該第一表面 2〇〇上形成有多數之導電跡線21,而於該第二表面2〇1上 形成有夕數藉導電牙孔或連通電路(未圓示)與該等導電跡 線電性連接之電性連結端22。由於該導電穿孔或連通 電路之設置為習知者,故在此不予圖示及贅述。該基板2〇 則得以習用之聚亞醯胺樹脂(P〇lyimide Resin)、聚丁二烯 (BT)樹脂' 環氧樹脂玻璃(FR4)或陶瓷(Ceramic)等材質製 成者均適用之。 經濟部智慧財產局員工消費合作社印製 於該基板20之第一表面200上之預設位置以黏接至 少一晶片2 3 (為減化起見’如圖所示者僅繪示一個),然該 晶片23之設置數量得視需要而予以變化之。該晶片23於 黏接至該基板20後’遂以多數如金線等之銲線24與該基 板20第一表面2 00上之該等導電跡線21形成電性連接關 係;該晶片23亦得以習知之覆晶(FHp chip)或TAB(Tape Automated Bonding)技術電性連接至該等導電跡線2i。由 於該等導電跡線21與該基板20之第二表面201上之該等 電性連結端22電性連通,故該晶片23得藉該等電性連結 端22與外界裝置電性連結。 該晶片2 3與該基板2 0完成電性連接後,遂使用一 16251 本紙張尺度過用⑴3國孓標準(CNS)A4規烙(:2]ϋ X 297公.¾ ) A7 經 濟 部 智 慧 財 產 局 員 工 消 費 合 社 印 製 五、發明說明(6 二物等之封裝樹脂形成—封裝膠體Μ該基板 23、”用二2〇0上’使該封裝膠嚨25得以包覆該晶片 電性連接該晶片23與該基板2。之銲線Μ、 2〇之第1 23電性連接之導電跡㈣及部份之該基板 表面200而與外界氣穷 a U t 巧丨乱也&離,亚有助於保護該 及與之電性連接邻八备私、翁> # 該封裝膠體25”ϊ 遭受其他製程之污染。 度及封裝樹脂之用量僅f U包覆住 該封裝㈣25過厚”致糊 體尽度之增加,進而影響封裝件之薄化程度。 弟2A圖係第1圖之蓋件 圖沿2B-W夕W 盍件之仰視圖,苐2B圖係第2A 2 B之剖面線圖;第2 c [§[在士政 一 # 弟0£1係本發明半導體封裝件 为一盍件之仰視圖;第2d圖係第闽、 面線圖。 0係第%圖沿2D_2D之剖 於封膠模壓完成後,如第丨圖所夕错, 乐丨口所不,遂於該基板20 之第一表面200上覆蓋一蓋件26, -^ ^ ^ , 卫M 一熱融膠27(如環 乳樹月曰等)黏接該蓋件26與該基板2g η匕儿人, 必盍件2 6得以樹 月曰化,物等製成,且於其一表面上形成有—凹m續 之空間係足以覆蓋住該封裝膠體25及至少該基 扳2〇之第一表面200,使得該基板2〇 雨山分# 弟一表面201外 路出該盖件26。又於該凹穴2 60形成有5 , 丨 、一凸起261 及至>、-排氣孔262。該凸起261係具有_高度小於該 穴⑽之深度,·同時,該凸起261得形成於該凹穴施 對應該封裝膠體25佈局250(如第2Α及)r ^ 嬰走 C圖所示)之位 並抵觸該封裝谬體25與該凹穴_内面26⑽相 卜來请尺度適用令國國家標準(CMSM4規洛(2!〇χ297公釐) (請先閱讀背面之注意事項再填寫本頁) « n n u nFigure 2B is a bottom view of Figure 2B, Figure 2A is a cross-sectional view along 2B-2B. 筮 vq, Figure 2C is a bottom view of another cover of the semiconductor of the present invention, 2D Pian and Wu Wudi The 2D diagram is the 2C diagram along the 2D-2D section. 16251 483132 V. Description of the invention (4 side-line diagram. = &Amp; Heat produced in the embodiment of the present invention "distribution map coated in the recess of the cover member; and Fig. 4A is a cross-sectional view of the conventional lid sealing member 4B in Fig. 4A; along the cross-section line of the substrate warping and the problem of overflowing during the capping process. ^ Component symbols of the semiconductor package Explanation】 ·· 1 semiconductor package 10 100 first surface substrate 11 wafer 101 first surface 13 encapsulant 12 electrical connection 140 cavity 14 cover member 16 light bend 15 hot melt adhesive 18 cavity 17 overflow knee 2 semiconductor package 19 Air spout 20 Substrate 201 Second surface 200 First surface 22 Electrically connected worm 21 Conductive trace 24 Welding wire 23 Wafer 250 Layout 25 Sealing gel 26 Cover 251 Surface 2600 Inner surface 260 Recess 262 Vent hole 261 Bump 27 Heat Glue Glue Standard 210 X 297 Printed by the Consumers ’Cooperative of the Ministry of Economic Affairs and Intellectual Property of the Ministry of Economic Affairs 16251 483132 A7 " -------- --____ V. Invention Description (5) " " [Detailed Description of Invention]: [Example] (Please read first Note on the back, please fill in this page again.) Figure 1 is a cross-sectional view of an embodiment of a semiconductor package with a cover according to the present invention. The semiconductor package with a cover in this embodiment ^ includes a substrate 20, which It has a first surface 200 and a second surface 201 opposite to the first surface ^. In a conventional method, such as etching, a plurality of conductive traces 21 are formed on the first surface 200. Electrical connection ends 22 electrically connected to these conductive traces through conductive tooth holes or connecting circuits (not shown) are formed on the two surfaces 201. Since the conductive perforations or connecting circuits are conventionally set, It will not be illustrated or described here. The substrate 20 can be used in polyimide resin (Polyimide Resin), polybutadiene (BT) resin 'epoxy glass (FR4) or ceramics. (Ceramic) and other materials are applicable. Ministry of Economic Affairs Intellectual Property The employee consumer cooperative prints at a predetermined position on the first surface 200 of the substrate 20 to adhere to at least one wafer 2 3 (for the sake of reduction, 'only one is shown in the figure), but the wafer 23 The number of settings can be changed as needed. After the wafer 23 is adhered to the substrate 20, a plurality of bonding wires 24, such as gold wires, are then used to form an electrical connection relationship with the conductive traces 21 on the first surface 200 of the substrate 20; the wafer 23 also The conventional FHp chip or TAB (Tape Automated Bonding) technology is electrically connected to the conductive traces 2i. Since the conductive traces 21 are in electrical communication with the electrical connection terminals 22 on the second surface 201 of the substrate 20, the chip 23 may be electrically connected to external devices through the electrical connection terminals 22. After the chip 23 is electrically connected to the substrate 20, a 16251 paper size was used (3 National Standard (CNS) A4 gauge (: 2) x X 297. ¾) A7 Intellectual Property of the Ministry of Economic Affairs Printed by the Bureau ’s Consumer Cooperatives. 5. Description of the invention (6. Encapsulation resin formation of two objects, etc.-encapsulation colloid M. The substrate 23, "encapsulate the encapsulation throat 25 with two 200" to electrically connect the chip electrically. The wafer 23 is electrically connected to the substrate M with the bonding wire M, the first 23 of 20, and a part of the substrate surface 200, which is far away from the outside air. Asia helps to protect this and its electrical connection. The packaging gel 25 ”ϊ is subject to contamination by other processes. The degree and the amount of packaging resin only cover the package ㈣25, which is too thick. "The increase of the extent of the paste will affect the thickness of the package. Figure 2A is the bottom view of the cover of Figure 1 along 2B-W Xi W, and Figure 2B is the 2A 2 B of Sectional line drawing; Section 2c [§ [在 士 政 一 # younger 0 £ 1 is a bottom view of the semiconductor package of the present invention; Figure 2d is the first 0, the top line chart. 0 is the first% chart along 2D_2D section after the sealing and molding is completed. As shown in Figure 丨, it ’s wrong. 26,-^ ^ ^, Wei M, a hot-melt adhesive 27 (such as ring milk tree moon, etc.) glued the cover member 26 and the substrate 2g η dagger, the required member 26 can be transformed into a tree moon, material And the like, and a recessed space formed on one surface is sufficient to cover the encapsulating gel 25 and at least the first surface 200 of the base plate 200, so that the substrate 2〇 雨 山 分 # 弟 一 表面201 is out of the cover member 26. In the cavity 2 60, 5, 丨, a protrusion 261 and to >,-exhaust hole 262 are formed. The protrusion 261 has a height smaller than the depth of the hole ⑽ At the same time, the protrusion 261 must be formed in the cavity to correspond to the layout 250 of the encapsulating gel 25 (as shown in Figure 2A and R ^), and to oppose the encapsulation body 25 and the cavity. _Inner face 26, please come to the standard to apply the national standard of the country (CMSM4 gauge (2! 〇χ297 mm) (Please read the precautions on the back before filling in this page) «nnun

I* n n I 華· -If u H · 16251 6 叫 3132 __B7 五、發明說明(7 y (如第1圖所示)。如[2A及2B圖所示,於該 第 Θ之中央位置處得形成有-個之該凸起261,·如 及2D圖所示,兩個或以上之該等凸起261得形 Ϊ 封裝谬體25佈局250之位置處亦或非靠近該凹 需緣之位置處、·該凸起261之設置位置及數量得視 =开Γ變化之,且該凸起261之形狀並不受如圖所示 之邊 限制。再者,該排氣孔262係形成於該凹穴260 然1::置處’且其數量如第2Α及2C圖所示者為4個, .......又置位置及數量得視需要而予以變化之。 此外’該形成於該蓋件26凹穴·之凸起261得抵 u于裝缪體25 ’破得確保該封裝膠冑25之表面⑸盥 該蓋件20凹穴260之内面2 ,、 炙円面26⑽之相對兩度,以控制半導 敍裝件產品厚度之品質要求’並得籍由高度控制以預留 =㈣厚度所需之空間,以防止該熱融膠27溢膠於 該盍件26外’而得確實控制封裝件組裝後尺寸之精度。 又’該形成於該凹穴26〇之排氣孔262,於黏接該蓋件% 與該基板2G之製程中,得以讓殘存於該熱融膠27與該蓋 件26間之空氣順利排出’以防止形成空洞,造成空氣被 擠壓瞬間連帶該熱融膠27喷出而造成溢膠。 —第3圖係顯示本發明實施例所使用之熱融膠塗佈於 蓋件之凹穴内之分布圖。如圖所示,用以黏接該蓋件% 凹穴260與該基板20之熱融膠27係依該基板2〇之外型 ㈣於該蓋件26之凹穴260内不影響該凸起261與該排 氣孔2刀布之位置處’再施以加壓加熱處理,以達黏接 不纸張尺度適用中gi-^準 (CNS)A4 ^烙(2】。χ 297公釐了 ..... » ·,··Μ, I „| __ 7 16251 483132 A7 B7I * nn I Hua · -If u H · 16251 6 is called 3132 __B7 V. Description of the invention (7 y (as shown in Figure 1). As shown in Figures 2A and 2B, it is obtained at the center of the Θ One protrusion 261 is formed. As shown in the 2D diagram, two or more of the protrusions 261 are shaped. The position of the package 250 on the layout 250 may or may not be close to the concave edge. The position and number of the protrusions 261 can be changed depending on the position and the number of the protrusions 261, and the shape of the protrusions 261 is not limited by the edges shown in the figure. Furthermore, the exhaust hole 262 is formed in the The dimples 260 are 1: 1: placed, and the number is 4, as shown in Figures 2A and 2C, and the positions and number can be changed as needed. In addition, 'the formation The protrusions 261 in the recesses 26 of the cover member 26 can be matched to the mounting body 25 'to ensure that the surface of the sealant 25 is covered with the inner surface 2 of the recesses 260 of the cover member 20, Relatively two degrees, to control the quality requirements of the thickness of the semi-conductor assembly product 'and obtain the space required by the height control to reserve = ㈣ thickness, to prevent the hot melt adhesive 27 from overflowing outside the 2626' And indeed Controls the accuracy of the size of the package after assembly. Also, the exhaust hole 262 formed in the cavity 26 is used to adhere the cover member and the substrate 2G, so that the remaining hot melt adhesive 27 and The air between the cover members 26 is exhausted smoothly to prevent the formation of voids, causing the air to be squeezed and the hot melt adhesive 27 to be sprayed out at the moment, causing the glue to overflow.-Figure 3 shows the hot melt adhesive used in the embodiment of the present invention Distribution diagram of coating in the recesses of the cover. As shown in the figure, the hot-melt adhesive 27 used to bond the cover to the recesses 260 and the substrate 20 is formed on the cover according to the shape of the substrate 20. The cavity 260 of the piece 26 does not affect the position of the protrusion 261 and the blade 2 of the vent hole, and then a pressure heating treatment is performed to achieve the adhesion. A4 ^ (2). Χ 297 mm ..... »,, · Μ, I„ | __ 7 16251 483132 A7 B7

五、發明說明(8 ) 該蓋件26與該基板20之目的,故符合該基板20鱼該蓋 =:接合:積所塗佈之該熱融膠”,使得控制該熱融 "口理用里,並得以防止該熱融膠27溢膠於該蓋件26 外’故得以提昇生產品質,並改善生產作業。 惟以上所述者,僅係用以說明本發明之具體實施例 而已,亚非用以限定本發明之可實施範圍,舉凡熟習該項 技藝者在未脫離本發明所指.示之精神與原理下所完成之/ 等效改變或修飾,仍應皆由後述之專利範圍所涵蓋。 ---—---—訂--------- (請先閱讀背面之注意事頊再填寫本 經濟部智慧財產局員工消費合作社印製 」97公.¾ ) 16251V. Description of the invention (8) The purpose of the cover member 26 and the substrate 20 is consistent with the cover of the substrate 20; the cover =: bonding: the hot melt adhesive applied by the product ", so that the hot melt is controlled " oral management In use, the hot melt adhesive 27 can be prevented from overflowing outside the cover member 26, so the production quality can be improved, and the production operation can be improved. However, the above is only used to explain the specific embodiments of the present invention. Asia and Africa are used to limit the implementable scope of the present invention. For those skilled in the art, equivalent changes or modifications made without departing from the spirit and principles indicated in the present invention should still be covered by the patent scope described below. Covered. ---------- Order --------- (Please read the notes on the back 顼 and then fill in the "Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs" 97 companies.) 16251

Claims (1)

483132 六、申請專利範園 1· -種具蓋件之半導體封裝件,係包括: 第-表面與苐二表面’於該第一表面上孫佈設有 多數之導電跡線,而於一 向於笱第一表面上形成有多數與該 等導電跡線電性連接之電性連結端;483132 VI. Application for patent Fan Yuan 1. A semiconductor package with a cover includes: a first surface and a second surface. On the first surface, a plurality of conductive traces are provided on the first surface, and The first surface is formed with a plurality of electrical connection terminals electrically connected to the conductive traces; 經 濟 部 智 慧 財 產 局 合 作 社 印 ,少一晶片,其係黏設至鱗基板之第一表面上; 輝、線帛以電性連接該晶片肖該等導電跡線 一封裝膠體,用以叫該晶片、該等銲線、該等與 該晶片電性連接之導電跡線及部份之該基板之第一表面 ^ 蓋件,係於其一表面上形成有一日穴,用以覆 蓋住至少該基板之第—表面,使該基板之第二表面外 露出該蓋件,且於該凹穴形成有至少一凸起及至少一 排氣孔;以及 一熱融膠’塗佈於該苔杜夕 至仰趴及盍仵之凹穴内不影響該凸起 與該排氣孔分布之位置處’用以黏接該凹犬與該基板 之第一表面。 2.如申明專利範圍第1項具蓋件之半導體封裝件,其中 該等導電跡線係蝕刻該基板之第一表面而形成者。 3·如申請專利範圍第1項具蓋件之半導體封裳件,其中 該等電性連結端係藉導電穿孔或連通電路與該等導^電 跡線電性連接。 4·如申請專利範圍第1項具蓋件之半導體封裝件,其中 該等銲線係為金線。 5·如申請專利範圍第1項具蓋件之半導體封震件,其中 該封裝膠體係以樹脂化合物形成者。Printed by the cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, one less chip, which is glued to the first surface of the scale substrate; the glow wire and the wire coil are electrically connected to the chip and the conductive traces. , The bonding wires, the conductive traces electrically connected to the chip, and a portion of the first surface of the substrate ^ a cover member is formed with a day hole on one surface to cover at least the substrate The first surface, the cover is exposed from the second surface of the substrate, and at least one protrusion and at least one exhaust hole are formed in the cavity; and a hot-melt adhesive is coated on the moss The positions on the backside and the bottom of the cavity that do not affect the distribution of the protrusions and the vent holes are used to adhere the concave dog and the first surface of the substrate. 2. A semiconductor package with a cover as described in claim 1, wherein the conductive traces are formed by etching the first surface of the substrate. 3. If the semiconductor package with the cover item No. 1 in the scope of the patent application is applied, the electrical connection ends are electrically connected with the conductive traces through conductive vias or communication circuits. 4. If the semiconductor package with a cover as described in item 1 of the patent application scope, these bonding wires are gold wires. 5. The semiconductor shock-absorbing member with a cover member as described in the first item of the patent application scope, wherein the encapsulant system is formed of a resin compound. 16251 9 經濟部智慧財產局員工消費合作社印製 483132 A8 ______ D8 一 __________ 六、申請專利範圍 6·如申請專利範圍第1項具蓋件之半導體封裝件,其中, 該蓋件係以樹脂化合物製成者。 〃 7·如申請專利範圍第〗項之具蓋件之半導體封裝件,其 中’該凸起之高度係小於該凹穴之深度。 8·如申請專利範圍第丨或7項具蓋件之半導體封裝件,其 中,該凸起係形成於該蓋件之凹穴内對應該封裝膠體佈 局之位置處,並抵觸該封裝膠體與該凹穴内面相對之表 面0 9·如申請專利範圍第丨或7項具蓋件之半導體封裝件,其 中,該凸起係形成於該蓋件之凹穴内之中央位置處。 10·如申請專利範圍第丨項具蓋件之半導體封裝件,其中, 該排氣孔係形成於該蓋件之凹穴之邊緣位置處。 11·如申請專利範圍第1項具蓋件之半導體封裝件,其中, 該熱融膠係為環氧樹脂。 12·—種用於半導體封裝件之蓋件,特徵在於其一表面土形成有 一凹穴,且於該凹穴形成有至少一凸起及至少一排氣孔。 13·如申請專利範圍第12項之蓋件,其中,該蓋件係以樹 脂化合物製成者。 14·如申請專利範圍第12項之蓋件,其中,該凸起之高度 係小於該凹穴之深度。 15.如申請專利範圍第12或14項之蓋件,其中,該凸起係 形成於該蓋件之凹穴内之非邊緣位置處。 16·如申請專利範圍第12項之蓋件,其中,該排氣孔係形 成於該蓋件之凹穴之邊緣位置處。 * ^ --------訂--------- (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 10 1625116251 9 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 483132 A8 ______ D8 I __________ VI. Patent Application Scope 6 · Semiconductor packages with lids such as the scope of patent applications, where the lids are made of resin compounds Made by. 〃 7. If the semiconductor package with a cover is in the scope of the patent application, the height of the protrusion is smaller than the depth of the cavity. 8. If the semiconductor package with a cover member No. 丨 or 7 in the scope of the application for a patent, the protrusion is formed in the cavity of the cover member at a position corresponding to the layout of the packaging colloid, and abuts the packaging colloid and the recess Opposite surface of the cavity surface 0 9 · Semiconductor package with a cover member as described in the scope of patent application No. 7 or 7, wherein the protrusion is formed at a central position in the cavity of the cover member. 10. The semiconductor package with a cover member according to item 丨 of the patent application scope, wherein the exhaust hole is formed at an edge position of a recess of the cover member. 11. The semiconductor package with a cover according to item 1 of the patent application scope, wherein the hot melt adhesive is epoxy resin. 12. A cover member for a semiconductor package, characterized in that a recess is formed on a surface soil, and at least one protrusion and at least one exhaust hole are formed in the recess. 13. The cover member according to item 12 of the patent application scope, wherein the cover member is made of a resin compound. 14. The cover according to item 12 of the patent application, wherein the height of the protrusion is smaller than the depth of the recess. 15. The cover according to claim 12 or 14, wherein the protrusion is formed at a non-edge position in the recess of the cover. 16. The cover member according to item 12 of the patent application scope, wherein the vent hole is formed at an edge position of a recess of the cover member. * ^ -------- Order --------- (Please read the notes on the back before filling in this page) This paper size applies to China National Standard (CNS) A4 (210 X 297) Centimeters) 10 16 251
TW090111431A 2001-05-14 2001-05-14 Semiconductor package having lid member TW483132B (en)

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