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TW475219B - Method to remove the re-depositions on a wafer - Google Patents

Method to remove the re-depositions on a wafer Download PDF

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Publication number
TW475219B
TW475219B TW089114946A TW89114946A TW475219B TW 475219 B TW475219 B TW 475219B TW 089114946 A TW089114946 A TW 089114946A TW 89114946 A TW89114946 A TW 89114946A TW 475219 B TW475219 B TW 475219B
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TW
Taiwan
Prior art keywords
protective layer
dielectric
wafer
redeposits
depositions
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Application number
TW089114946A
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Chinese (zh)
Inventor
Renate Dr Bergmann
Christine Dr Dehm
Barbara Hasler
Ulrich Scheler
Guenther Dr Schindler
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Infineon Technologies Ag
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Publication of TW475219B publication Critical patent/TW475219B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • H01L21/02071—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a delineation, e.g. RIE, of conductive layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Weting (AREA)
  • Cleaning Or Drying Semiconductors (AREA)

Abstract

This invention relates to a method to remove the re-depositions on a wafer as well as a wafer which is free from re-depositions. The removal of the re-depositions on the wafer is carried out after applying a protection-layer on the top-electrode and the boundary face of the top-electrode with the dielectrics, so that these regions are not damaged by the wet-chemical medium, by which the re-depositions can be effectively removed.

Description

! ▲ 2 5 7 經濟部智慧財產局員工消費合作社印制衣 A7 __B7 五、發明說明（丨） 本發明係關於晶圓上去除再沉積物所用之方法以及一種 不會發生再沉積之晶圓。 在以光罩和反應性氣體來對（鐵電質）記憶電容器之層進 行電漿化學式蝕刻時通常會形成再沉積現象。側壁聚合物 是由可蝕刻之各層，光阻以及蝕刻氣體所形成之各種成份 來表示。這些污染物可達到光罩之高度。若這些污染物留 在已蝕刻完成之結構上，則會出現以下各種問題： -記憶體介電質會由於擴散而受到污染， -在導電性再沉積物中會發生短路現象， -此元件之拓樸形狀會改變。 再沉積物（其在底部電極之電漿化學式蝕刻之後形成）是 以濕式化學方式去除。這是可行的，因爲載體，位障層和 底部電極所形成之層結構很穩定，使其可承受濕式化學淨 化步驟。 再沉積物（其在介電質之電漿蝕刻之後形成）之去除是以 濕式化學方式進行，即，藉由含氫氧基之脫模機（例如， EKC- 265® )，有機溶解介質（例如，NMP(N -甲基吡咯啶）及 /或各種酸（例如，HF，BHF，已緩衝之HF或Caro’sche 酸，112304及11202 )或顯像劑（例如，1120中5%之四甲基氨氫 氧化物）之作用而可被去除或可被還原，但此種處理方式是 不値得推薦的，因爲其會造成頂部電極及/或笔個晶圓構 造之脫落。 本發明之目的是提供一種方法以便去除這些再沉積物（ 本紙張尺度適用中國國家標準（CNS)A4規格（2]0 X 297公釐） ------------- 装-----^----訂---------線 (請先閱讀背面之注意事項再填寫本頁) 475219 90. 9. 2 7： 年月ώ V". _^五、發明說明（5 ) 特別是沉積於介電質層上者），其中不會損害晶圓上之層結構。 此外，本發明亦提供一種晶圓，其不會發生此種再沉積現象。 本發明之內容是一種方法，其用來去除晶圓上之再沉積物，其 包含以下各步驟： -製備一基板⑴，其上配置介電質⑶，介電質⑶上配置一種已結 構化之電極⑸； -施加一種保護層⑷於介電質⑶上及該已結構化之電極⑸上； -使用一已結構化之遮罩來對該保護層⑷及介電質⑶進行蝕刻， 此時再沈積物⑹可形成在晶圓上； -藉由濕式化學淨化步驟去除該再沈積物⑹，此時該保護層⑷覆 蓋且保護該介電質⑶之一部份及該已結構化之電極⑸。 本發明之其它內容是晶圓，其基本上不會發生再沉積現象。 “基本上不會”在這裡之意義是：在此種過程中再沉積物仍是 不可忍受的，當此製造過程中所有之操作步驟已最佳化地工作時 ，不會有再沉積物留在晶圓上。 在本方法之較佳形式中，該保護層由氮化矽所構成。較佳是 使用無氫之LPCVD -氮化物。但適當之方法是亦可使用其它氮化 物（例如，電漿氮化物），其是以95000來進行沉積。所施加之層 之厚度可改變，但此種厚度通常是在10和lOOnm之間，較佳是 在15和80nm之間，特別好之情況是在30和5 Onm之間。須測 定此種厚度，使頂部電極和此種至介電質之界面可最佳化地受到 保護，但此晶圓之總厚度和應力在具備此保護層之情況下不會受 到太大之影響。另一方面是此種層在去除這些再沉積物之後該保 護層亦被去除時應可輕易地又被去除。因此，通常是力求一種儘 可能薄之保護層。 475219 經濟部智慧財產局員工消費合作社印製 A7 B7 ___ 五、發明說明（3) 依據一種構成方式，在此種蝕刻（其會形成一些再沉積物 )之前施加此種保護層。在此種情況下此保護層亦一起被蝕 刻。 較佳是以EKC- 26 5或類似之脫模機來去除這些再沉積物 。此種處理時間可改變，但通常是小於一小時，特別是小 於30分鐘。溫度同樣可.改變，但其通常是小於80 °C且較 室溫爲高。 依據本方法之形式，在去除這些再沉積物之後使保護層 被氧化成矽氧化物層及/或被去除。電漿過程適合作爲去 除用，此處較佳是使用一種型式是Strata之等向性下游 (downs t ream)反應器，其是以一種氧-四氟甲烷-化學品 來操作。另一方式是可使用一種電漿蝕刻室，例如，使用 一種在95000主機（main frame)上之MxP金屬蝕刻室。電 漿蝕刻之條件例如可爲150mTor r(毫托），60 Gauss，3 50W ，45 sccrn四氟甲院-流，90 seem氧氣流；50ηπι氮化砂 之齡1刻時間大約是5 0 s e c (秒）。 依據本方法之另一種形式，在晶圓上留下該保護層，此 種保護層在稍後之製程中可用作電容器上方之氫位障。， 依據本方法之形成，此保護層是與介電質一起被蝕刻。 因此，首先以光來界定各結構。在此種共同之蝕刻中可使 用一種在95000主機上之MxP金屬蝕刻室。電漿蝕刻條件 例如可爲 lOmTorr，80 Gauss，750W，50sccra 氫化溴-流，50nm氮化物和180nra SBT之蝕刻時間大約是150秒。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ------------- ^-----ί----^---------^ . (請先閱讀背面之注意事項再填寫本頁) 475219 A7 B7 五、發明說明（斗） (請先閱讀背面之注意事項再填寫本頁) 依據本方法之其它形式，此保護層之蝕刻是與介電質之 蝕刻步驟相分開，使得在此二個蝕刻步驟之間可改變這些 氣體及/或其它電漿條件。 此種基板較佳是一種具有鐵電質記憶電容器之晶圓。所 含有之介電質較佳是SBT( SrBi2Ta 209 )，其可受到保護層所 保護而不會受到濕式化學淨化方法所損傷。若不使用SBT ，則亦可使用其它陶瓷氧化物，例如，BST[(Ba，Sr )Ti03] 或PZT[Zr，Ti ]03]，其類似於SBT且亦會受到濕式化學淨化 步驟所損傷，因此在本發明中其上須覆蓋一層保護層。 由於這些再沉積物來自陶瓷氧化物之乾蝕刻，其化學成 份類似於陶瓷氧化物。一種却除這些再沉積物所用之淨化 劑因此亦可侵蝕（或至少可損害）此陶瓷氧化物。 本發明之保護層因此亦可保護此介電質使上側不會受到 侵触^ 以下將依據圖式來詳述一種實施形式。圖式簡單說明如 下： 第1圖 在介電質層蝕刻之後以及光罩被灰化之後此晶 圓之橫切面。 經濟部智慧財產局員工消費合作社印製 第2圖 在蝕刻之前施加一種保護層於晶圓後，此晶圓 之橫切面。 第3圖 在濕式化學淨化以及保護層去除之後此晶圓之 橫切面。 第1圖顯示一種晶圓構造之橫切面。可辨認的是載體1( 本紙張尺度適用中國國家標準（CNS)A4規格（2】0 X 297公釐） 475219 A7 B7! ▲ 2 5 7 Printed clothing by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 __B7 V. Description of the Invention (丨) The present invention relates to a method for removing redeposits from a wafer and a wafer that does not undergo redepositing. Re-deposition usually occurs when plasma-etching a layer of a (ferroelectric) memory capacitor with a photomask and a reactive gas. The side wall polymer is represented by various components formed by etchable layers, photoresist, and etching gas. These contaminants can reach the height of the reticle. If these contaminants remain on the etched structure, the following various problems will occur:-Memory dielectrics will be contaminated due to diffusion,-Short circuits will occur in conductive redeposition,- The topology will change. The redeposition, which is formed after the plasma chemical etching of the bottom electrode, is removed by wet chemistry. This is possible because the layer structure formed by the carrier, the barrier layer and the bottom electrode is stable enough to withstand the wet chemical purification step. Removal of the redeposition (which is formed after the plasma etching of the dielectric) is performed wet-chemically, that is, by a hydroxyl-containing mold release machine (eg, EKC-265®), an organic solvent (Eg, NMP (N-methylpyrrolidine) and / or various acids (eg, HF, BHF, buffered HF or Caro'sche acids, 112304 and 11202) or imaging agents (eg, 5% of 1120 Tetramethylammonium hydroxide) can be removed or reduced, but this treatment is not recommended because it will cause the top electrode and / or pen wafer structure to fall off. The purpose is to provide a method to remove these redeposits (this paper size applies the Chinese National Standard (CNS) A4 specification (2) 0 X 297 mm) ------------- equipment- --- ^ ---- Order --------- line (please read the notes on the back before filling in this page) 475219 90. 9. 2 7: year and month free V ". _ ^ Description of the invention (5) Especially those deposited on the dielectric layer), which will not damage the layer structure on the wafer. In addition, the present invention also provides a wafer, which does not undergo such redeposition. The content of the present invention is a method for removing redeposits on a wafer, which includes the following steps:-preparing a substrate ⑴, on which a dielectric CU is disposed, and a dielectric CU is disposed on the Structured electrode ⑸;-applying a protective layer ⑷ on the dielectric 及 and the structured electrode ；;-using a structured mask to etch the protective layer ⑷ and the dielectric ⑶ At this time, the re-deposit ⑹ can be formed on the wafer;-the re-deposit ⑹ is removed by a wet chemical purification step, and at this time, the protective layer ⑷ covers and protects a part of the dielectric ⑶ and Structured electrode ⑸. The other content of the present invention is a wafer, which basically does not undergo redeposition. The meaning of "substantially not" is that redeposition is still intolerable in this process. When all the operating steps in this manufacturing process have been optimized, no redeposition will remain on the wafer. In a preferred form of the method, the protective layer is composed of silicon nitride. It is best to use hydrogen-free LPCVD-nitrides, but appropriate The method is also possible to use other nitrides (for example, plasma nitride), which is deposited at 95000. The thickness of the applied layer can vary, but this thickness is usually between 10 and 100 nm, preferably Between 15 and 80nm, particularly good is between 30 and 5 Onm. This thickness must be measured so that the top electrode and the interface to the dielectric can be optimally protected, but this wafer The total thickness and stress will not be greatly affected if this protective layer is provided. On the other hand, such a layer should be easily and again removed when the protective layer is removed after removing these redepositions. Therefore, it is usually sought for a protective layer that is as thin as possible. 475219 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 ___ V. Description of the invention (3) According to a composition method, such a protective layer is applied before such etching (which will form some redeposition). In this case, the protective layer is also etched together. It is preferred to remove these redeposits with an EKC-265 or similar demolding machine. This processing time can vary, but is usually less than one hour, and especially less than 30 minutes. The temperature can also be changed, but it is usually less than 80 ° C and higher than room temperature. According to the form of the method, the protective layer is oxidized to a silicon oxide layer and / or removed after removing these redepositions. The plasma process is suitable for removal. Here, it is preferred to use a downs t ream reactor of the type Strata, which is operated with an oxygen-tetrafluoromethane-chemical. Another way is to use a plasma etching chamber, for example, a MxP metal etching chamber on a 95000 main frame. Plasma etching conditions can be, for example, 150mTor r (millitorr), 60 Gauss, 3 50W, 45 sccrn teflon-flow, 90 seem oxygen flow; the age of 50nπ nitrided sand is about 50 sec. second). According to another form of the method, the protective layer is left on the wafer, and this protective layer can be used as a hydrogen barrier above the capacitor in a later process. According to the method, the protective layer is etched together with the dielectric. Therefore, the structures are first defined by light. In this common etch, a MxP metal etch chamber on a 95000 host can be used. Plasma etching conditions can be, for example, 10mTorr, 80 Gauss, 750W, 50sccra bromine-flow, 50nm nitride and 180nra SBT. The etching time is about 150 seconds. This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) ------------- ^ ----- ί ---- ^ ------ --- ^. (Please read the notes on the back before filling this page) 475219 A7 B7 V. Description of the invention (bucket) (Please read the notes on the back before filling this page) According to other forms of this method, this protection The layer is etched separately from the dielectric etch step so that these gases and / or other plasma conditions can be changed between these two etch steps. Such a substrate is preferably a wafer having a ferroelectric memory capacitor. The dielectric contained therein is preferably SBT (SrBi2Ta 209), which can be protected by a protective layer without being damaged by a wet chemical purification method. If SBT is not used, other ceramic oxides can also be used, such as BST [(Ba, Sr) Ti03] or PZT [Zr, Ti] 03], which is similar to SBT and is also damaged by the wet chemical purification step Therefore, a protective layer must be covered thereon in the present invention. Since these re-deposits come from dry etching of ceramic oxides, their chemical composition is similar to that of ceramic oxides. A scavenger used in addition to these redepositions can therefore attack (or at least damage) the ceramic oxide. Therefore, the protective layer of the present invention can also protect the dielectric material from being invaded by the upper side. An implementation form will be described in detail below with reference to the drawings. The diagram is briefly explained as follows: Figure 1 A cross-section of the crystal circle after the dielectric layer is etched and the photomask is ashed. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Figure 2 A cross-section of the wafer after a protective layer is applied to the wafer before etching. Figure 3 Cross-section of the wafer after wet chemical purification and protective layer removal. Figure 1 shows a cross section of a wafer structure. Identifiable is the carrier 1 (this paper size applies to China National Standard (CNS) A4 specifications (2) 0 X 297 mm) 475219 A7 B7

經濟部智慧財產局員工消費合作社印製 五、發明說明（s ) 例如，氧化矽），其上施加一種已結構化之底部電極2 (例 如，1 00 - 200ηπι之鉑）。已結構化之介電質層3 (例如， 513丁，5“丨21^2〇9)連接至底部電極2，在介電質層3上可辨 認此頂電極5(例如，10(N 200nra之鉑），其是以一種磨成小 平面用且因此而自我淨化之過程而被結構化。利用箭頭7 來指出此種介於頂部電極和介電質層之間的界面，此界面 受到濕式化學淨化方法所保護。在介電質3之邊緣上可辨 認此種再沉積物6，其會干擾此晶圓之拓樸形狀且應被去 除，但這樣在不具有保護層時會造成脫落現象。 第2圖所示是和第1圖相同之晶圓橫切面。在蝕刻之前 施加一種保護層4。對此保護層和介電質進行蝕刻且將該 光罩去除。如圖所示，此保護層4(例如，一種30 - 50nra之 氮化矽層）覆蓋該頂部電極及覆蓋頂部電極和介電質之間 的界面。第2圖所示之晶圓所處之狀態是：其在此介電質 之蝕刻中去除不期望之再沉積物時未受損害地經歷一種濕 式化學淨化步驟。此種濕式化學淨化步驟例如包含一種以 EKC - 26 5，NMP (N -甲基吡咯啶）及/或氫氟酸來進行之處理 〇 第3圖是藉由淨化步驟去除此再沉積物6之後的晶圓。 濕式淨化步驟例如是以EKC - 2 6 5在6 5 °C時進行1 5分鐘。然 後同樣去除此保護層4。所剩下的是一種具有蕞佳化拓撲 圖形且無污染之晶圓，其可被擴散成各種不同之層。 元件符號對照表 本紙張尺度適用中國國家標準（CNS)A4規輅（2〗0 X 297公f ) -----------------r---訂---------， (請先閱讀背面之注意事項再填寫本頁} 475219 A7 B7 五、發明說明（（） 1 載體 2 底部電極 3 介電質層 4 保護層 5 頂部電極 6 -再沉積物 (請先閱讀背面之注意事項再填寫本頁) -K-----^----訂---------線 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the Invention (s) For example, silicon oxide, on which a structured bottom electrode 2 (for example, 100-200ηπ platinum) is applied. A structured dielectric layer 3 (for example, 513 d, 5 "丨 21 ^ 209) is connected to the bottom electrode 2, and the top electrode 5 (for example, 10 (N 200nra Platinum), which is structured by a process of grinding into a facet and thus self-purifying. Use arrow 7 to indicate the interface between the top electrode and the dielectric layer, which is subject to wet Protected by a chemical cleaning method. The redeposition 6 can be identified on the edge of the dielectric 3, which will interfere with the topography of the wafer and should be removed, but this will cause it to fall off without a protective layer Fig. 2 shows the same cross section of the wafer as in Fig. 1. A protective layer 4 is applied before etching. This protective layer and dielectric are etched and the photomask is removed. As shown in the figure, This protective layer 4 (for example, a silicon nitride layer of 30-50nra) covers the top electrode and covers the interface between the top electrode and the dielectric. The wafer shown in Fig. 2 is in a state of: This dielectric etch undergoes a wet process without damage when undesired redeposition is removed The chemical purification step. Such a wet chemical purification step includes, for example, a treatment with EKC-26 5, NMP (N -methylpyrrolidine) and / or hydrofluoric acid. Figure 3 removes this by a purification step. Wafer after redeposition 6. The wet cleaning step is performed with EKC-2 6 5 at 65 ° C for 15 minutes. Then the protective layer 4 is also removed. What is left is a kind with optimizing Topological graphics and non-polluting wafers, which can be diffused into various layers. Component symbol comparison table The paper size applies the Chinese National Standard (CNS) A4 regulations (2) 0 X 297 male f) ----- ------------ r --- Order ---------, (Please read the notes on the back before filling out this page} 475219 A7 B7 V. Description of the invention (() 1 Carrier 2 Bottom electrode 3 Dielectric layer 4 Protective layer 5 Top electrode 6-Redeposition (please read the precautions on the back before filling this page) -K ----- ^ ---- Order --- ------ Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, this paper is sized for the Chinese National Standard (CNS) A4 (210 X 297 mm)

Claims (1)

475219 、申請專利範圍 第891 14946號「去除晶圓上再沉積物之方法」專利案 (9^^92¾ 修正) 六申請專利範圍 1. 一種去除晶圓上再沉積物之方法，其特徵爲： -製備一基板⑴，其上配置介電質⑶，介電質⑶上配置一 種e結構化之電極⑸； -施加一種保護層⑷於介電質⑶上及該已結構化之電極 ⑸上； -使用一已結構化之遮罩來對該保護層⑷及介電質⑶進 行蝕刻，此時再沈積物⑹可形成在晶圓上； -藉由濕式化學淨化步驟去除該再沈積物⑹，此時該保護 層⑷覆蓋且保護該介電質⑶之一部份及該已結構化之 電極⑸。 2. 如申請專利範圍第1項之方法，其中這些待去除之再沉積 物來自陶瓷氧化物介電質之乾燥鈾刻過程。 3. 如申請專利範圍第1或第2項之方法，其中此保護層包含 氮化矽。 4. 如申請專利範圍第3項之方法，其中施加厚度1〇至1 〇〇nm 之保護層。 / 5. 如申請專利範圍第1項之方法，其中在介電質被蝕刻之前 施加該保護層且此保護層然後與介電質一起被蝕刻。 6. 如申請專利範圍第1或第5項之方法，其中此保護層在去 除這些再沉積物之後被去除。 7. 如申請專利範圍第1或桌5項之方法，其中此保護層在去 除這些再沉積物之後仍保留著。475219, patent application scope No. 891 14946 "method for removing redeposits on wafers" (9 ^^ 92¾ amendment) Six patent applications 1. A method for removing redeposits on wafers, characterized by: -Preparing a substrate ⑴, on which a dielectric ⑶ is arranged, and an e-structured electrode ⑸ is arranged on the dielectric ⑶;-applying a protective layer ⑷ on the dielectric 及 and the structured electrode ⑸; -Use a structured mask to etch the protective layer ⑷ and the dielectric ⑶, at which time redeposits ⑹ can be formed on the wafer;-remove the redeposits by a wet chemical purification step ⑹ At this time, the protective layer ⑷ covers and protects a part of the dielectric ⑶ and the structured electrode ⑸. 2. The method according to item 1 of the scope of patent application, wherein the re-deposits to be removed come from the drying uranium etching process of the ceramic oxide dielectric. 3. The method of claim 1 or 2, wherein the protective layer includes silicon nitride. 4. The method as claimed in item 3 of the patent application, wherein a protective layer having a thickness of 10 to 100 nm is applied. / 5. The method of claim 1, wherein the protective layer is applied before the dielectric is etched and the protective layer is then etched together with the dielectric. 6. The method of claim 1 or 5, wherein the protective layer is removed after removing these redeposits. 7. The method of claim 1 or table 5 in which the protective layer is retained after removing these redeposits.
TW089114946A 1999-07-27 2000-10-24 Method to remove the re-depositions on a wafer TW475219B (en)

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