TW466597B - Method to form the high resistive resistor of mixed-signal IC by laser annealing - Google Patents

Abstract

The present invention relates to a method to form the high resistive resistor of mixed-signal IC, which comprises providing a semiconductor structure, depositing a first polysilicon layer on the semiconductor structure, and implanting ions into the first polysilicon layer; next growing a first thin insulation layer on the first polysilicon layer by laser annealing; then transferring the pattern of a resistor on the first polysilicon layer and the first thin insulation layer, forming a resistor after etching, wherein first thin insulation layer can prevent the dopant from diffusing outward, so that the formed resistor has a high resistance.

Description

46 659 7 V. Description of the invention (1) ---- 5 -1 Field of invention: The present invention relates to a method for forming a resistor in a mixed-signal integrated circuit, in particular to forming a resistor with high resistance. The device can reduce the power consumption of the device when it is in standby. 5-2 Background of the Invention ·· Applied to Asymmetric Digital Subscriber Line

Subscriber Line (ADSL) mixed-signal integrated circuits on broadband services need high-resistance electrical resistors to reduce power consumption when the device is in standby. Generally speaking, if the resistor needs to have high resistance electrical properties, the dopant dose of the implanted resistor must be reduced in the manufacturing process. However, 'the low dose and depth of dopant is not easy to control in the semiconductor process.' Pushing mass is easily affected by the process and causes phenomena such as outward diffusion and excessively deep implant depth ', thereby reducing the electrical quality of the resistor. Therefore, the dopant is controlled. Qualitative dose and depth are very important for high resistance resistors. The general method for making a resistor in a mixed-signal integrated circuit is shown in Figure A. 'First, a substrate 101, a p-well 102, an N-well 103, an isolation element 110, and a sacrificial oxide layer 111 are provided. . A first polycrystalline silicon layer 120 is deposited on the sacrificial oxide layer 111, and then doped iso is implanted into the first polycrystalline silicon layer 120 by blanket implantation. First here

4 6 659 7 _ V. Description of the invention (2) The crystalline silicon layer 120 is used as the bottom electrode of the resistor and capacitor, and the dose of dopant 180 depends on the characteristics of the resistor. Β- The mask 1330, which has been pattern-transferred, covers the position of the resistor used to make the resistor in the first polycrystalline silicon layer 120 as the implantation mask of dopant 181, as shown in the first figure B. Generally speaking, the additive properties of dopant 180 and dopant 181 are used to achieve the required characteristics of the capacitor. Secondly, after the mask 130 is removed in a conventional manner, the entire wafer is placed in a hot furnace for tempering. Next, the pattern of the resistor and the capacitor is transferred to the first polycrystalline silicon layer 120 ′ and the first polycrystalline silicon layer 120 is etched to form a resistor 140 and a lower plate of the capacitor. 141 as shown in the first figure C. In the following, a transistor and a capacitor are completed on this substrate 101. Since the formation steps are known to those skilled in the art, they are not described in detail here. The method forms a transistor and a capacitor. The capacitor includes at least a lower electrode plate 141 and an upper electrode plate 142, and the gate electrodes 143 and the upper electrode plates 142 of the transistors are each composed of a second polycrystalline silicon layer. However, the conventional method described above, when used in the manufacture of high-resistance resistors, has many disadvantages. The main disadvantage is the high resistance electrical control

Page 5 4 6 659 7 V. Description of the Invention (3) Both the steps of ion implantation and tempering in the traditional method will cause unstable electrical resistance ^ At the stage of ion implantation, the depth of the dopant may be too deep However, the tempering stage may cause the dopants to diffuse outward, which in turn will cause difficult control of high resistance electrical properties. 5-3 Purpose and Summary of the Invention: In view of the above-mentioned backgrounds of the invention, many shortcomings of traditional high-resistance resistor manufacturing, the present invention provides a method for forming a resistor in a mixed signal integrated circuit. In this method, laser tempering is used instead of general furnace tempering, which has better energy and reaction time control. Another object of the present invention is to provide a method for forming a resistor with high electrical resistance in a mixed signal integrated circuit. In this method, a step of laser tempering can be used to simultaneously obtain a high-resistance electrical resistor and a capacitor with a low voltage coefficient. It is still another object of the present invention to provide a method for forming a resistor and a capacitor with high electrical resistance in a mixed signal integrated circuit. In this method, the dielectric layer formed by the laser tempering step is thin, so it can be easily removed without reducing the capacitance of the capacitor. According to the above-mentioned purpose, in the present invention, a forming mixture is disclosed

46 659 7 V. Description of the invention (4) Method of resistors and capacitors in a signal integrated circuit, this method provides a semiconductor structure 'first deposited on the semiconductor structure-a first polycrystalline silicon layer, and Ions are implanted in the silicon layer. Next, a magic material layer such as silicon nitride and silicon oxide layer is grown on the first polycrystalline silicon layer by laser tempering. The thickness of the silicide layer can be obtained by laser energy and operation time. control. Subsequently, pattern transfer is performed on the first polycrystalline silicon layer, and the pattern of the electrode plate under a resistor and a capacitor is transferred to the first polycrystalline silicon layer. Thereafter, a dielectric layer is formed on the electrode plate below the capacitor, and a second polycrystalline silicon layer is deposited on the semiconductor structure and the dielectric layer. On the other hand, pattern transfer is performed on the second polycrystalline silicon layer, and the pattern of the upper electrode plate of one of the capacitors is transferred to the second polycrystalline silicon layer. The upper electrode plate is located directly above the lower electrode plate, and is finally completed. Structure of a Capacitor and a Resistor "5 ~ 4 Invention Detailed Description: The semiconductor design of the present invention can be widely used in many semiconductor designs' and can be made with many different semiconductor materials. When the present invention is implemented in a preferred way When explaining the method of the present invention by examples, those who are familiar with this field should recognize that many steps can be changed, and materials and impurities can be replaced. These general replacements undoubtedly do not depart from the spirit and scope of the present invention. Furthermore, the present invention is easy to use in the overall complementary metal-oxide semiconductor, and it can also be used on the insulating layer with silicon soin (silon insulat).

Page 7 46659 7 V. Description of the invention (5) Due to this, when the invention is described in conjunction with a complementary metal-oxide semiconductor, it is recognized that the invention can be applied to a wide range of designs. Secondly, “The present invention is described in detail with a schematic diagram below, and when this embodiment is described in detail.” The cross-sectional view showing the semiconductor structure is partially enlarged in the semiconductor manufacturing process at a general scale for the convenience of explanation. In actual production, it should include three-dimensional space dimensions of two degrees in length and width. In the method of the present invention, a method of exposing a resistor in a high-resistance semiconductor implanted with a silicon via a thunder-polycrystalline structure is disclosed. Deposit a first son. Next, the pattern of the F electrode plate is performed on the first polymer layer such as nitrided energy and silicon layer to form a dielectric layer and two polycrystalline silicon layers on the first plate. On the other hand, on one of the transfer capacitors, the upper plate is a bit including the above gate on the lower pole. The silicon and oxygen are transferred over time and the polycrystalline silicon is provided on the half surface by a mixed method of the polar plate and the polar plate. The crystal layer is formed on the crystal layer, and the silicon layer is formed on the crystal layer, which is well transferred. The conductor structure is directly above the second polycrystalline gate. After the signal semiconductor is combined with the first control resistor, it is patterned on the dielectric layer and the final integrated circuit structure. First, a method of long thickness may be used in a polycrystalline silicon layer. A first polycrystalline layer is deposited on the electrode layer under the capacitor of the first and first capacitors, and the second polycrystalline layer is patterned into a tempered material layer. Then, in a preferred embodiment, referring to the second A diagram,

466597 V. Description of the invention (6) Body substrate 1, a P well 2 ', an N well 3, an isolation element 10, and a sacrificial oxide layer 1 a first polycrystalline silicon layer 2 0 deposited on the sacrificial oxide layer 11 1 Then, a dopant (not shown) is implanted into the first polycrystalline silicon layer 20 by blanket ion implantation. Secondly, a mask 30 that has been pattern transferred covers the position of the resistor in the first polycrystalline silicon layer 20 to be used as an implantation mask of the substrate 81. Here, the first polycrystalline silicon layer 20 is used as a lower electrode (bolitoin electrode) of a resistor and a capacitor. On the other hand, the dose of a blanket implant dopant depends on the characteristics of the resistor, and The blanket type implant dopant and dopant 81 are added to achieve the required characteristics of the capacitor. The second step is the focus of the present invention. As shown in Figure 2B, The method removes the mask 30 ', and then the laser furnace (excijner laser) is used instead of the heating furnace' to temper the wafer. Compared with hot furnace tempering, the energy and operating time of laser tempering can be well controlled, and the tempering step is performed in an environment full of nitrogen, laughing gas, nitric oxide, oxygen and ozone. In the laser tempering step, a silicide layer is formed on the surface of the first polycrystalline silicon layer 20. The silicide layer may be silicon nitride or silicon halide. It must be explained that the thickness of the silicide layer 51 can be accurately controlled by adjusting the laser energy and operation time. Furthermore, the step of transferring the pattern of the resistor and the capacitor to the first polycrystalline silicon layer 20 ′ and etching the first polycrystalline silicon layer 20 ′ forms a resistor 40 and a lower plate 42 of a capacitor as in the first step. Figure C

Page 9 46 659 7 V. Description of the invention (7). Finally, a dielectric layer (not shown) is first formed on the substrate 1, the lower electrode plate 42 and the resistor 40. The dielectric layer may be a high temperature oxide (temperatureΤΟ), oxide-nitrogen Oxide-nitride-oxide (ONO) or interpoly oxide (IPO). In addition, the temperature for forming the dielectric layer is preferably not more than 900 ° C, so as to reduce the influence of heat treatment (therma 1 eye 1 i ng) on the semiconductor material, and the thickness of the dielectric layer is between 200 to 5 0 0 Angstroms. The role of this dielectric layer is to reduce the encroachment of capacitors and resistors due to oxidation. Next, in addition to the dielectric layer on the capacitor, the remaining dielectric layers will be removed, and then a second layer is deposited. The polycrystalline silicon layer is formed on the substrate, and the upper electrode plate 43 and the interrogation electrode 44 of the capacitor are formed by the subsequent pattern transfer and etching steps. Then, a transistor is completed by an appropriate known method. In the invention, forming a thin layer of silicon nitride or silicon oxide on the surface of the first polycrystalline silicon layer by means of laser tempering can not only prevent the dopants from diffusing outwards, but also will not have an impact on the capacitance of the capacitor. The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the patent application of the present invention; any other equivalent changes or modifications made without departing from the spirit disclosed by the present invention shall be included in the following Within the scope of patent application.

466597 Schematic illustration of the first diagram A to the first D circle A conventional diagram for making a resistor in a mixed-signal integrated circuit using a conventional process. Figures 2A to 2]) are schematic diagrams of resistors in a mixed-signal integrated circuit according to the present invention. The main part of the symbol '· 1 substrate 2 P well' 3 N well 10 Isolating element 11 Sacrificial oxide layer 2 0 First polycrystalline layer 30 Mask 40 Resistor 42 Lower plate 43 Upper plate 44 Gate 81 Dopant 82 Gas 101 Substrate 102 P well 103 N well 1 10 Isolation element

46 659 7 Brief description of the diagram 111 Sacrificial oxide layer 120 First polycrystalline silicon layer 130 Mask 140 Resistor 141 Lower plate 142 Upper plate 14 3 Gate 180 Dopant 1 8 1 Dopant

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Claims (1)

4 6 659 7_ 6. Scope of Patent Application 1. A method for forming a resistor in an integrated circuit, the method at least comprises: providing a semiconductor structure; depositing a first polycrystalline silicon layer on the semiconductor structure; Implanting an ion in a polycrystalline silicon layer; growing a first insulating thin layer by laser tempering on the first polycrystalline silicon layer; performing pattern transfer on the first polycrystalline silicon layer, Transferring a pattern of a resistor onto the first polycrystalline silicon layer and the first insulating thin layer; and etching the first polycrystalline silicon layer and the first insulating thin layer to form the resistor. 2. The method according to item 1 of the scope of patent application, wherein the above-mentioned semiconductor structure includes at least: a first well having a first conductivity and a second well having a second conductivity, the first well and the A second well is located in a substrate; an isolation element is located on the substrate and interposed between the first well and the second well; and a second insulating layer is located on the surface of the substrate and the insulation element . 3. The method according to item 2 of the patent application, wherein the above-mentioned first conductivity is opposite to the second conductivity. 4. The method of claim 1, wherein the above-mentioned ion implantation step includes at least: implanting the ions in a blanket manner in the first polycrystalline silicon layer; Page 13 466597_ VI. Application scope Patent transfers a first implant mask on the first polycrystalline silicon layer, the first implant mask transfers a pattern defining the resistor; in the first Locally implanting the ions in the polycrystalline silicon layer according to the definition of the first implantation mask; and removing the first implantation mask. 5. The method according to item 1 of the patent application scope, wherein the first insulating thin layer is selected from one of the group consisting of silicon nitride and silicon oxide. 6. The method according to item 1 of the scope of patent application, wherein the above-mentioned laser tempering method is performed in a gas-filled environment, and the gas is selected from the group consisting of nitrogen, nitric oxide, laughing gas, oxygen, and ozone. One of the ethnic groups. 7. A method of forming a high-resistance resistor in a mixed-signal integrated circuit, the method at least comprising: providing a semiconductor structure; depositing a first polycrystalline silicon layer on the semiconductor structure; on the first polycrystalline silicon An ion is implanted in a blanket manner in the evening layer; a first implantation mask is transferred on the first polycrystalline silicon layer, and the first implantation mask is transferred on a pattern defining a resistor ; Implanting the ions locally in the first polycrystalline silicon layer according to the definition of the first implantation mask; removing the first implantation mask; and laser-tempered the first polycrystalline silicon layer Method to grow a first must Page 14 4 6 659 7 VI. Patent application margin thin layer > Perform pattern transfer on the first polycrystalline silicon layer to transfer the pattern of the resistor to the first polycrystalline silicon layer and the first insulating layer The first polycrystalline silicon layer and the first insulating thin layer are engraved on the thin layer and ik to form the resistor. 8. The method according to item 7 of the patent application > wherein the above-mentioned semiconductor structure includes at least: A conductive first well and a second conductive well. The first well and the second well are located in a substrate. An isolation element is located on the substrate and interposed between the first well. And the second well: and a second insulating layer is located on the surface of the substrate and the isolating element a 9. As the method of the scope of patent application No. 8 wherein the above-mentioned first conductivity and the second conductivity in contrast. 10. The method according to item 7 of the scope of patent application, wherein the above-mentioned first insulating thin layer is selected from the group consisting of silicon nitride and silicon oxide. The method of laser fire is performed in a gas-filled environment. The gas is selected from the group consisting of nitrogen \ nitrogen oxide, laughing gas, oxygen and ozone. Page 15 4 δ 659 7_ VI. Application scope 1 2. —A method for forming a resistor and a capacitor in a mixed signal integrated circuit, the method at least includes: providing a semiconductor structure; depositing a first on the semiconductor structure A polycrystalline silicon layer; implanting an ion in the first polycrystalline silicon layer; growing a first insulating thin layer by laser tempering on the first polycrystalline silicon layer; A pattern transfer is performed on the polycrystalline silicon layer, and the pattern of a lower electrode plate of a resistor and a capacitor is transferred to the first polycrystalline silicon layer and the first insulating thin layer; formed on the electrode plate below the capacitor A dielectric layer; depositing a second polycrystalline silicon layer on the semiconductor structure and the dielectric layer; and performing pattern transfer on the second polycrystalline silicon layer to transfer the pattern of an upper plate of the capacitor To the second polycrystalline stone layer, the upper electrode plate is located approximately directly above the lower electrode plate. 1 3. The method according to item 12 of the scope of patent application, wherein the above-mentioned semiconductor structure includes at least: a first well with a first conductivity and a second well with a second conductivity, the first And the second well is located in a substrate; _ an isolation element is located on the substrate and is between the first ridge and the second ridge; and a second insulation layer is located on the substrate and the isolation element On the surface. Page 1S 4 6 659 7 VI. The description of the patent application scope of the large-capacity device is the above-mentioned method. The item 3 of the positive encirclement of the item side 3, the Li Yuan special departure, please apply for this D Λ: 'bit 4 1 about the conductance of the first paragraph of the law in the above item 3-I ο Li Dian's special guide please two-φ-the first as it should. With 5 11 into the description of the plant's separation 2 of the law of the second round of the first offense: please include -5- as small as • step 6 1 step The first, the cover, the cover should be inserted into the planting one; The blanket transfer device of a pattern of the square pattern is blocked to cover the layers in the picture. Move the first cover, the cover, the cover, the cover, and the child, rf 0, and "11, the addition and the cover, β— θ, the fixed cover, cover the cover, and the first cover = o, according to the middle layer silicon crystal-cover cover, cover 1 No. The first one is described in the above-mentioned group of "Chengfa Group" 2 1 Oxygen and siege Fanfan " Qi Zhuan You please choose freely Bai Ti • Layer 7 1 Thin fire gas nitrogen return from i Lei to. The self-selection of the Qi family in the body group should be completed, and the group of law practitioners should enter the odorous environment of oxygen and the 2 1 Qi Qi surrounding body, Fan Qi Qi full of laughter, please Nitrogen application is based on the method of the oxygen method of 8 · ^^, the layer selection of the dielectric, and its legal method 2-I Page 17 4 6 659 7_ VI. Scope of patent application Since it is one of the groups consisting of high temperature oxide layer, oxide-nitride-oxide and internal polycrystalline oxide. 20. The method according to item 12 of the scope of patent application, wherein the step of forming a dielectric layer includes at least: depositing the dielectric layer on the semiconductor structure, the resistor, and the capacitor; on the dielectric layer The pattern transfers a second mask, which covers the lower electrode plate; and etched on the dielectric layer to remove the dielectric layer on the semiconductor structure and the resistor. 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