A7 B7 .437050 52 87iwr.doc/〇〇6 五、發明說明（/ ) 本發明是有關於一種靜電放電（Electrical Static Discharge ;以下簡稱ESD)保護電路，且特別是有關於一種 積體電路之ESD保護電路佈局（layout)，係於金氧半場效電 晶體（MOSFET)上呈釘耙交錯狀佈局之源極與汲極上設一 方框狀之高濃度接地區外，並於該源極上分別設有高濃度 P+與N+交錯之基底接地區，同時於此P+與N+交界之基底 接地區上設有邊緣接觸點，大幅降低基底電阻至趨近於 零，以達到快速ESD開啓及提昇ESD保護效能。 在積體電路(1C)例如動態隨機存取記憶體(DRAM)、靜 態隨機存取記憶體（SRAM)的製造過程中或是晶片完成 後，靜電放電事件常是導致積體電路損壞的主要原因。例 如在地毯上行走的人體，於相對濕度(RH)較高的情況下可 檢測出約帶有幾百至幾千伏的靜態電壓，而於相對濕度較 低的情況下則可檢測出約帶有一萬伏以上的靜態電壓。當 這些帶電體接觸到晶片時，將會向晶片放電，結果有可能 造成晶片失效。於是，爲了避免靜電放電損傷晶片，各種 防制靜電放電的方法便因應而生。最常見的習知作法是利 用硬體防制靜電放電，也就是在內部電路(Internal Circuit) 與每一焊墊（Pad)間，均設計一晶片嵌入式（〇n_chip)的靜電 放電保護電路以保護其內部電路。 再者’由於閘極氧化層之形成厚度會隨著製程積集度 增加而縮小’使得閘極氧化層的崩潰電壓將逐步逼近源極/ 汲極接面崩潰電壓’甚或更低，此時原來的ESD保護電路 設g十效能將大打折扣。此外，內部電路多半依循最小設計 3 本紙張尺度適用t國國家標準（CNS)A4規格（210 X 297公釐） (請先閲讀背面之注意事項再填寫本頁) H ϋ n n I 1 n n 線· 經濟部智慧財產局員工消費合作社印製 437U 5 0 52«7t\v Γ doc/006 A7 B7 經濟部智慧財產局員工消費合作社印f 五、發明說明（之） 準則（Minimum Design Rules)設計，且未適當地設計（例如接 觸窗到擴散區的邊緣以及接觸窗到閘極邊緣均需要足夠的 空間）以抵抗巨大的靜電放電暫態電流(Transient CiUTeni)， 致使在高積集度的情況下，晶片極容易受到靜電放電的損 害。所以，靜電放電的問題已成爲深次微米積體霓路故障 的原因之一’故如何有效提昇靜電放電保護電路的效能乃 爲目前業界所亟盼的。 請參照第1A圖與第1B圖’.第1A圖繪示的是習知一 種ESD保護電路的俯視圖，以及第1B圖繪示的是第ία圖 之ESD保護電路的剖面圖，其主要係由MOSFET構成。 如第1A圖與第1B圖所示’其主要係在一 p型基底90 適當位置分設有一 N+共用源極92，此共用源極92左右位 置分別對稱設有N+汲極91，且共用源極92與兩側之汲極 91上方均設有接觸點910與920，以連接至接地電壓VSS 之端點及供輸入訊號之輸入端點Ι/P。而相鄰接觸區910與 920間形成有二氧化矽閘氧化層80，在二氧化矽閘氧化層 80內介於每一共用源極92接觸區920與兩側接觸區910間 分設有一複晶矽閘極81，以便使對應於每一共用源極92 兩側分別形成兩組之MOSFET防靜電保護電路。 再者，又如第1A圖之佈局俯視圖及第1B圖之兩側所 示，更設有一方框狀之高濃度接地區70(用以供基底卯接 地之用）。而以上述保護電路之等效電路可如第1B圖下半 部分所示，其每組保護電路在基底90內分別形成有一基底 電阻（R-sub)，各基底電阻(R-sub)與位於周邊之高濃度接地 (請先閱讀背面之注意事項再填寫本頁) 訂----- f 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 437〇 5 0 52 87twf. doc/O Οά Α7 Β7 五、發明說明（3 ) 區70將形成串接關係’惟因此愈靠近中央處之保護電路， 其相對於接地區70之阻抗將愈高。因此，當靜電由汲極接 觸區910進入時’所有的汲極電位都相同，因爲接近高濃 度接地區70的基底電阻最小’所以流過基底電流就比較 大，換言之，流過此處的汲極電流最大。因此愈靠近中央 處之保護電路，其所通過的靜電流愈小，當保護電路的組 數很多時，位於中央位置之保護電路將形同無效，此一現 象勢必將影響並降低保護電路之防靜電效果。 請參照第2A圖與第2B圖，第2A圖繪示的是習知另 —種ESD保護電路的俯視圖，以及第2B圖繪示的是第2A 圖之ESD保護電路的剖面圖，其已揭露於中華民國專利公 告編號第344Π7號一文中。 如第2A圖與第2B圖所示’主要係在一 p型基底1〇 上分設有一 N+共用源極20與N+汲極30。此共用源極20 與N+汲極30之相對關係亦呈釘耙交錯狀，又其外圍更設 有一呈方框狀之高濃度基底接地區40,用以供p型基底10 接地之用。 呈釘耙狀之共用源極20各臂分別位於P型基底之適 當處，又亦呈釘耙狀之汲極30各臂則分別交錯位於共用源 極20左右位置，此共用源極20與兩側之汲極30上方均設 有接觸點21與31，以連接至接地電壓VSS之端點及供輸 入訊號之輸入端點Ι/P。而相鄰接觸區21與31間形成有二 氧化矽閘氧化層50，在二氧化矽閘氧化層50內介於每一 共用源極20接觸區21與兩側接觸區31間分設有一複晶矽 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) τ<— — 1ί 丨訂---------. 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 437〇50 52ίΐ7ΐ\ν i'.d〇c/0f)6 A7 ____B7 五、發明說明（¥) 鬧極51 ’以便使對應於每—共用源極2〇兩側分別形成兩 組MOSFET防靜電保護電路。 必須注意的是’在第2A圖與第2B圖中，其共用源極 20之各臂較寬，而於各臂中央處分別植入有一高濃度p+ 之基底接地區41。以上述保護電路之結構，其形成之等效 電路如第2B圖所示，由於每—共用源極川上分別植入有 高濃度P+接地區41，因此以每—共用源極2〇爲中心構成 的兩組保護電路，其相對於高濃度之接地區41在基底1〇 內所形成之基底電阻(R-sub)均屬相同，亦即每一組保護電 路之基底電阻(R-sub)均應一致，故其具備有相同的導通能 力。因此，當輸入端點（Ι/P)出現靜電，且由各接觸區31進 入時，其上各組由MOSFET構成之保護電路將同時導通， 藉此消弭靜電作用，以達到ESD保護作用。 然而’依照此習知ESD保護電路之結構，如第2A圖 之佈局結構’由於在共用源極20之各臂中央處分別植入一 高濃度P+之基底接地區41 ’使得共用源極20之各臂面積 較汲極30爲寬。但眾所皆知，ESD保護能力主要係與汲極 面積有關，亦即約99%造成的ESD損害，大多與汲極面積 及其閘氧化層邊緣有關，反而與源極面積較不相關，因此 較小的汲極面積，或其面積小於源極面積時，將造成較低 的ESD保護效能。 有鑒於此，本發明提出一種積體電路之靜電放電保護 電路，包括共用源極位於基底上，且共用源極上方設有數 個第一接觸點，以連接至接地電壓。汲極位於基底上，汲 (請先閱讀背面之注意事項再填寫本頁) 广v------!訂·^--------線· 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 x 297公釐） 437U 5 0 52S71W l.doc/006 A7 B7 五、發明說明（jT ) 極與共用源極係呈釘fE父錯狀，且汲極上方設有數個第二 接觸點’以連接至輸入端點。呈方框狀之高濃度基底接地 區設置於共用源極與汲極之外圍，用以供基底接地之用。 値得注意的是，汲極之各臂面積比共用源極之各臂面積還 要寬，且於共用源極之各臂中分別植入有高濃度以與N+ 交錯之基底接地區，使設於共用源極上之各第一接觸點分 別位於此高濃度P+與N+交錯之基底接地區的各交界處 上。 本發明提出之積體電路之靜電放電保護電路，係於共 用源極上分別植入高濃度P+與N+交錯之基底接地區，並 於此P+與N+交界之基底接地區上設有邊緣接觸點，使得 PN接面間之基底電阻値趨近於零，達到快速ESD開啓及增 加閉鎖的功能。再者，由於高濃度基底接地區延伸至共用 源極，故可快速導通保護電路’並輕易地將超額靜電引導 至基底上，有效防止後端之內部電路的閘極氧化層遭受到 破壞，以達到更佳的ESD保護作用。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉較佳實施例，並配合所附圖式，作詳細 說明如下： 圖式之簡單說明： 第1A圖繪示的是習知一種ESD保護電路的俯視圖； 第1B圖繪示的是第1A圖之ESD保護電路的剖面圖； 第2A圖繪示的是習知另一種ESD保護電路的俯視 圖； . /}ν Γ bN .), -----I J------- I I-----旬 ----1 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS>A4規格（210 x 297公釐） 經濟部智慧財產局員工消費合作社印製 437U 5 Ο 5 2 Κ 7 1 w Γ, tl ο c/O Ο 6 Α7 _Β7_五、發明說明（6) 第2Β圖繪示的是第2Α圖之ESD保護電路的剖面圖； 以及 第3圖繪示的是依照本發明一較佳實施例的一種ESD 保護電路的俯視圖。 圖式之標號說明： _ 10、90、100 :基底 20、 92、120 :共用源極 21、 31、m、131、910、920 :接觸點 30、91、Π0 :汲極 40、41、70 ' 140、141 :高濃度接地區 50、 80、150 :閘氧化層 51、 81、151 :複晶矽閘極 實施例 請參照第3圖，其繪示的是依照本發明一較佳實施例 的一種ESD保護電路的俯視圖。 如第3圖所示，主要係在一 P型基底100上分設有一 N+共用源極120與N+汲極130。此共用源極120與N+汲極 130之相對關係呈釘耙交錯狀，又其外圍更設有一呈方框 狀之高濃度基底接地區140，用以供P型基底100接地之 用。 呈釘耙狀之共用源極120各臂分別位於P型基底之適 當處，又亦呈釘耙狀之汲極130各臂則分別交錯位於共用 源極120左右位置，此共用源極120與兩側之汲極130上 方均設有數個接觸點121與131，用以分別連接至接地電壓 (請先閱讀背面之注意事項再填寫本頁) ο ----訂----- 線_ 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ! ^37u 5 Ο >2i47lw r.doc/006 A7 - ___B7______ 五、發明說明（^ ) vss之端點及供輸入訊號之輸入端點I/P，其中接觸點ι21 與131之構成形狀例如爲圓形。而相鄰接觸區121與ιΜ 間形成有閘氧化層150,在聞氧化層150內介於每一共用源 極U0接觸區121與兩側接觸區131間分設有一複晶矽閘 極15L·以便使對應於每一共用源極丨20兩側分別形成兩組 MOSFET防靜電保護電路。 在本實施例中，必須注意的是，共用源極120之各臂 面積較窄，而汲極130之各臂面積較寬。並且，於共用源 極120之各臂中分別植入有高濃度P+與N+交錯之基底接 地區Ml。較特別的是，設於共用源極120上之各接觸點 121，其配置位置分別剛好位於此高濃度P+與N+交錯之基 底接地區141的交界處上，換言之，以形狀爲圓形之接觸 點121爲例，其直徑剛好位於P+與N+交界之基底接地區 141上，亦即本發明所配置之接觸點121，係爲業界所稱之 爲邊界接觸（buttmg contact)的接觸點設計。由於接觸點121 係爲邊界接觸點的設計，故在其PN接面間之基底電阻値 將趨近於零，因此具有快速ESD開啓及增加閉鎖（iatch-up) 的功能。再者，由於做爲ESD保護環之高濃度基底接地區 140延伸至共用源極120，當輸入端點(Ι/P)出現靜電，且由 各接觸區131進入時，其上各組由M0SFET構成之保護電 路將會同時被快速導通，可更輕易地將超額靜電引導至基 底100上，有效防止後端之內部電路的閘極氧化層遭受到 破壞，以達到更佳的ESD保護作用。 綜上所述，本發明具有以下的優點： 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) ----訂---------線- 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 4370 5 Ο >2N7lw r.doc/0 0 6 A7 _B7 五、發明說明（g ) (1) 於共用源極上分別植入高濃度P+與N+交錯之基 底接地區，並於此P+與N+交界之基底接地區上設有邊緣 接觸點，使得PN接面間之基底電阻値趨近於零，達到快 速ESD開啓及增加閉鎖的功能。 (2) 由於高濃度基底接地區延伸至共用源極，故可快 速導通保護電路，並輕易地將超額靜電引導至基底上，有 效防止後端之內部電路的閘極氧化層遭受到破壞，以達到 更佳的ESD保護作用。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍內，當可作各種之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者爲準。 (請先閱讀背面之注意事項再填寫本頁)A7 B7 .437050 52 87iwr.doc / 〇〇6 V. Description of the invention (/) The present invention relates to an electrostatic discharge (ESD) protection circuit, and in particular, to ESD of an integrated circuit The layout of the protection circuit is connected to the source and drain of the metal-oxide-semiconductor half-field-effect transistor (MOSFET) in a staggered layout outside the box, and a high-concentration connection area is provided on the source. Concentrated P + and N + interlaced substrate contact areas. At the same time, edge contact points are provided on the substrate contact area at the junction of P + and N +, which greatly reduces the substrate resistance to near zero to achieve fast ESD turn-on and improve ESD protection performance. During the manufacture of integrated circuits (1C) such as dynamic random access memory (DRAM), static random access memory (SRAM), or after the chip is completed, electrostatic discharge events are often the main cause of damage to integrated circuits . For example, a human walking on a carpet can detect a static voltage of about several hundred to several thousand volts when the relative humidity (RH) is high, and can detect an approximate band when the relative humidity is low. There is a static voltage of more than 10,000 volts. When these charged bodies come into contact with the wafer, they will discharge to the wafer, which may cause the wafer to fail. Therefore, in order to avoid electrostatic discharge from damaging the wafer, various methods for preventing electrostatic discharge have been developed. The most common practice is to use hardware to prevent electrostatic discharge. That is, a chip-embedded (On_chip) electrostatic discharge protection circuit is designed between the Internal Circuit and each pad. Protect its internal circuits. Furthermore, 'Because the thickness of the gate oxide layer will decrease as the process accumulation increases', the breakdown voltage of the gate oxide layer will gradually approach the source / drain junction breakdown voltage' or even lower. The performance of the ESD protection circuit will be greatly reduced. In addition, the internal circuit mostly follows the minimum design. 3 This paper size is applicable to the national standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling this page) H ϋ nn I 1 nn cable · Printed by the Consumer Property Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 437U 5 0 52 «7t \ v Γ doc / 006 A7 B7 Printed by the Employee Cooperative Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs f V. Designed by (Minimum Design Rules) and Not properly designed (for example, sufficient space is required from the edge of the contact window to the diffusion region and the edge of the contact window to the gate) to resist the huge electrostatic discharge transient current (Transient CiUTeni), so that in the case of high accumulation, Wafers are extremely susceptible to damage from electrostatic discharge. Therefore, the problem of electrostatic discharge has become one of the reasons for the failure of deep submicron integrated circuits. Therefore, how to effectively improve the performance of the electrostatic discharge protection circuit is currently urgently expected by the industry. Please refer to FIGS. 1A and 1B ′. FIG. 1A shows a top view of a conventional ESD protection circuit, and FIG. 1B shows a cross-sectional view of the ESD protection circuit of FIG. MOSFET structure. As shown in FIG. 1A and FIG. 1B, it is mainly based on a p-type substrate 90 provided with an N + common source 92 at appropriate positions, and the common source 92 is provided with N + drains 91 symmetrically at left and right positions, and the common source Above the electrode 92 and the drain electrode 91 on both sides, contact points 910 and 920 are provided to connect to the terminal of the ground voltage VSS and the input terminal I / P for inputting signals. A silicon dioxide gate oxide layer 80 is formed between adjacent contact regions 910 and 920. Within the silicon dioxide gate oxide layer 80, a plurality of contacts are formed between each common source 92 contact region 920 and the contact regions 910 on both sides. The silicon gate 81 is formed so that two groups of MOSFET anti-static protection circuits are formed on both sides corresponding to each common source 92. Furthermore, as shown in the top view of the layout of FIG. 1A and the two sides of FIG. 1B, a box-shaped high-concentration ground connection area 70 (for basement ground connection) is further provided. The equivalent circuit of the above protection circuit can be shown in the lower half of FIG. 1B. Each set of protection circuits has a substrate resistance (R-sub) formed in the substrate 90, and each substrate resistance (R-sub) and High-concentration grounding in the surroundings (please read the precautions on the back before filling this page) Order ----- f This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) 437〇5 0 52 87twf doc / O Οά Α7 Β7 V. Description of the invention (3) The area 70 will form a series connection. However, the closer it is to the central protection circuit, the higher its impedance relative to the area 70 will be. Therefore, when static electricity enters from the drain contact region 910, 'all the drain potentials are the same, because the substrate resistance near the high-concentration junction region 70 is the smallest', so the current flowing through the substrate is relatively large, in other words, the drain flowing through here Maximum pole current. Therefore, the closer the central protection circuit is, the smaller the static current it passes. When the number of protection circuits is large, the protection circuit located at the center will be invalid. This phenomenon will definitely affect and reduce the protection of the protection circuit. Static effect. Please refer to FIG. 2A and FIG. 2B. FIG. 2A shows a top view of another conventional ESD protection circuit, and FIG. 2B shows a cross-sectional view of the ESD protection circuit of FIG. 2A, which has been disclosed. In the article of the Republic of China Patent Publication No. 344Π7. As shown in FIG. 2A and FIG. 2B, ′ is mainly provided with an N + common source 20 and an N + drain 30 on a p-type substrate 10. The relative relationship between the common source electrode 20 and the N + drain electrode 30 is also staggered, and the periphery is further provided with a box-shaped high-concentration substrate connection area 40 for grounding the p-type substrate 10. The arms of the rake-shaped common source 20 are located at appropriate positions of the P-type substrate, and the arms of the rake-shaped drain 30 are staggered at the left and right positions of the common source 20, respectively. Above the drain electrode 30, contact points 21 and 31 are provided to connect to the terminal of the ground voltage VSS and the input terminal I / P for input signals. A silicon dioxide oxide layer 50 is formed between the adjacent contact regions 21 and 31, and a plurality of silicon dioxide oxide layers 50 are interposed between the contact region 21 of each common source 20 and the contact regions 31 on both sides in the silicon dioxide oxide layer 50. Crystal silicon paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling this page) τ < — — 1ί Order --------- Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs printed 437〇50 52ίΐ7ΐ \ ν i'.d〇c / 0f) 6 A7 ____B7 V. Description of Invention (¥) 闹 极 51 ' In order to make two sets of MOSFET anti-static protection circuits corresponding to each side of each common source electrode 20. It must be noted that, in Figs. 2A and 2B, the arms of the common source 20 are wider, and a base contact region 41 of high concentration p + is implanted at the center of each arm. With the structure of the protection circuit described above, the equivalent circuit formed is as shown in FIG. 2B. Since a high-concentration P + contact region 41 is implanted on each of the common source channels, it is constituted with each common source 20 as the center. The two groups of protection circuits have the same substrate resistance (R-sub) formed in the substrate 10 with respect to the high-concentration junction area 41, that is, the substrate resistance (R-sub) of each group of protection circuits is the same. Should be the same, so they have the same continuity. Therefore, when static electricity occurs at the input terminal (I / P) and is entered by each contact area 31, the protection circuits composed of MOSFETs on it will be turned on at the same time, thereby eliminating the static electricity effect to achieve the ESD protection effect. However, according to this conventional ESD protection circuit structure, as shown in the layout structure of FIG. 2A, since a high-concentration P + substrate connection region 41 is implanted at the center of each arm of the common source 20, the common source 20 The area of each arm is wider than the drain electrode 30. However, as everyone knows, the ESD protection capability is mainly related to the drain area, that is, about 99% of the ESD damage caused is mostly related to the drain area and the edge of the gate oxide layer, but it is less related to the source area. A smaller drain area or an area smaller than the source area will result in lower ESD protection performance. In view of this, the present invention provides an integrated circuit electrostatic discharge protection circuit including a common source on a substrate, and a plurality of first contact points above the common source for connection to a ground voltage. The drain electrode is located on the substrate. (Please read the precautions on the back before filling in this page.) Guang v ------! Order · ^ -------- Line · This paper size applies to Chinese national standards ( CNS) A4 specification (21 × x 297 mm) 437U 5 0 52S71W l.doc / 006 A7 B7 V. Description of the invention (jT) The pole and the common source are nailed to the fE father, and there are several above the drain A second contact point 'to connect to the input endpoint. The box-shaped high-concentration substrate grounding region is provided on the periphery of the common source and drain electrodes for grounding the substrate. It should be noted that the area of each arm of the drain is wider than the area of each arm of the common source, and a high concentration is implanted in each arm of the common source so as to intersect with the substrate of N +. Each first contact point on the common source electrode is located at each junction of the high-concentration P + and N + interlaced base area. The electrostatic discharge protection circuit of the integrated circuit provided by the present invention is that a high-concentration P + and N + interlaced substrate junction area is implanted on a common source, and edge contact points are provided on the substrate junction area at the boundary between P + and N +. This makes the substrate resistance 値 between the PN junctions close to zero, achieving fast ESD opening and increasing blocking functions. In addition, since the high-concentration substrate contact area extends to the common source, the protection circuit can be quickly turned on and the excess static electricity can be easily guided to the substrate, effectively preventing the gate oxide layer of the internal circuit at the back end from being damaged. Achieve better ESD protection. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, the following describes the preferred embodiments in detail with the accompanying drawings as follows: Brief description of the drawings: FIG. 1A Shows a top view of a known ESD protection circuit; Figure 1B shows a cross-sectional view of the ESD protection circuit of Figure 1A; Figure 2A shows a top view of another known ESD protection circuit;. /} ν Γ bN.), ----- I J ------- I I ----- Xuan ---- 1 (Please read the notes on the back before filling this page) Intellectual Property of the Ministry of Economic Affairs The paper size printed by the Bureau ’s Consumer Cooperatives applies the Chinese national standard (CNS > A4 size (210 x 297 mm). Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economy, printed 437U 5 Ο 5 2 Κ 7 1 w Γ, tl ο c / O Ο 6 Α7 _Β7_ V. Description of the invention (6) Figure 2B shows a cross-sectional view of the ESD protection circuit of Figure 2A; and Figure 3 shows an ESD according to a preferred embodiment of the present invention Top view of the protection circuit. Symbols of the drawings: _ 10, 90, 100: base 20, 92, 120: common source 21, 31, m, 131 910, 920: Contact points 30, 91, Π0: Drain electrodes 40, 41, 70 '140, 141: High-concentration contact areas 50, 80, 150: Gate oxide 51, 81, 151: Example of a polycrystalline silicon gate Please refer to FIG. 3, which shows a top view of an ESD protection circuit according to a preferred embodiment of the present invention. As shown in FIG. 3, an N + common source is mainly provided on a P-type substrate 100. 120 and N + drain 130. The relative relationship between this shared source 120 and N + drain 130 is staggered, and the periphery is further provided with a box-shaped high-concentration substrate connection area 140 for the P-type substrate 100 For grounding, the arms of the rake-shaped common source 120 are located at appropriate positions of the P-type base, and the arms of the rake-shaped drain 130 are staggered at the left and right positions of the common source 120, respectively. This common source 120 There are several contact points 121 and 131 above the drain electrode 130 on both sides, which are respectively connected to the ground voltage (please read the precautions on the back before filling this page) ο ---- order ----- line _ This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)! ^ 37u 5 Ο > 2i47lw r.doc / 006 A7-___B7______ V. Description of the invention (^) The end point of the vss and the input end point I / P for the input signal, wherein the shape of the contact points ι21 and 131 is, for example, circular, and between the adjacent contact areas 121 and ιΜ A gate oxide layer 150 is formed, and a polycrystalline silicon gate 15L is provided between the common source U0 contact area 121 and the contact areas 131 on both sides in the oxidized oxide layer 150 so as to correspond to each common source. Two groups of MOSFET anti-static protection circuits are formed on both sides of 丨 20. In this embodiment, it must be noted that the area of each arm of the common source 120 is narrow, and the area of each arm of the drain 130 is wide. Further, high-concentration P + and N + interdigitated base contact regions M1 are implanted in the arms of the common source 120, respectively. More specifically, the contact points 121 provided on the common source electrode 120 are located at the junctions of the high-concentration P + and N + interlaced substrate junction areas 141, in other words, the contacts having a circular shape The point 121 is taken as an example, and its diameter is just on the base contact area 141 at the boundary of P + and N +, that is, the contact point 121 configured in the present invention is a contact point design called a buttmg contact in the industry. Since the contact point 121 is designed as a boundary contact point, the substrate resistance 値 between its PN junctions will approach zero, so it has the functions of fast ESD opening and increasing latch-up. In addition, since the high-concentration substrate connection area 140 serving as the ESD protection ring extends to the common source 120, when static electricity appears at the input terminal (I / P) and enters from each contact area 131, the upper groups are composed of MOSFETs. The formed protection circuit will be turned on at the same time, which can more easily guide the excess static electricity to the substrate 100, effectively preventing the gate oxide layer of the internal circuit at the back end from being damaged, so as to achieve better ESD protection. To sum up, the present invention has the following advantages: The paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling this page) ---- Order- -------- Line-Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 4370 5 Ο > 2N7lw r.doc / 0 0 6 A7 _B7 V. Description of the invention ( g) (1) High-concentration P + and N + staggered substrate junction areas are implanted on the common source, and edge contact points are provided on the substrate junction area at the boundary of P + and N +, so that the substrate resistance between the PN junctions is 値Approaching zero, achieving fast ESD opening and increasing blocking functions. (2) Because the high-concentration substrate contact area extends to the common source, the protection circuit can be quickly turned on and the excess static electricity can be easily guided to the substrate, effectively preventing the gate oxide layer of the internal circuit at the back end from being damaged, Achieve better ESD protection. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be determined by the scope of the attached patent application. (Please read the notes on the back before filling this page)
一&,’ I ^1 ^1 ^1 ] n n 1« 1 1 1 1 ^1 ^1 — ^1 ^1 ^1 ^1 ^1 ^1 ^1 ^1 ^1 ^1 .^1 ^1 ^1 ^1 ^1 ^1 ^1 .^1 I 本紙張尺度適用中國國家標準（CNS>A4規格（210 X 297公釐）一 &, 'I ^ 1 ^ 1 ^ 1] nn 1 «1 1 1 1 ^ 1 ^ 1 — ^ 1 ^ 1 ^ 1 ^ 1 ^ 1 ^ 1 ^ 1 ^ 1 ^ 1 ^ 1. ^ 1 ^ 1 ^ 1 ^ 1 ^ 1 ^ 1 ^ 1. ^ 1 I This paper size applies to the Chinese national standard (CNS > A4 size (210 X 297 mm)