TWI633729B - High-voltage esd protection circuit and a low-voltage-bulk-trigger esd current discharging circuit thereof - Google Patents

Abstract

The invention relates to a high-voltage electrostatic protection circuit and a low-voltage base-triggered electrostatic current discharge circuit. The low-voltage base-triggered electrostatic current discharge circuit is formed by serially connecting a plurality of low-voltage substrate isolation type transistors, and the total breakdown voltage can be Suitable for high-voltage system power supply; the base of each low-voltage substrate isolation type transistor is connected with a switching circuit of the high-voltage electrostatic protection circuit, and is not connected with a substrate to improve trigger efficiency; and the low-voltage substrate isolation type transistor The gate of the gate is kept at a distance from the sidewall of the gate insulating layer of the gate to improve the electrostatic discharge tolerance; when the static electricity occurs, the switch circuit triggers the isolation of the low-voltage substrate isolation transistor to smoothly eliminate the electrostatic current.

Description

High-voltage electrostatic protection circuit and low-voltage base trigger electrostatic current discharge circuit

The invention relates to a high voltage electrostatic protection circuit, in particular to a high voltage electrostatic protection circuit with a low voltage base triggering electrostatic current discharge circuit.

In an integrated circuit using a high-voltage voltage source, a high-voltage electrostatic protection circuit is generally designed at the output and the input end of the integrated circuit to prevent static electricity from being transmitted through the output and discharged to the inside of the integrated circuit, thereby causing circuit damage.

Please refer to FIG. 7 , which is a common high-voltage electrostatic protection circuit including an electrostatic detecting circuit 50 and a high-voltage gate-triggered transistor 60 , and the gate-triggered transistor 60 and the static detecting circuit 50 . Parallel, and connected between the high and low voltage terminals HV_VCC and HV_VSS of the high voltage source; when the static electricity occurs, the static detecting circuit 50 first detects and triggers the gate triggering transistor 60 through the gate G Turning on, the electrostatic current is removed through the turned-on gate trigger type transistor 60. However, the high-voltage gate-triggered transistor 60 itself is a high-voltage MOS device, so the trigger voltage is high, and it is difficult to protect the internal high-voltage circuit components, and the internal resistance is high, so that the static current is eliminated after being turned on. And it is necessary to further improve it.

In view of the shortcomings of the high voltage electrostatic protection circuit used in the foregoing integrated circuit, the main object of the present invention is to provide a high voltage electrostatic protection circuit and a low voltage base triggered electrostatic current discharge circuit.

The main technical means used to achieve the above purpose is to make the high-voltage electrostatic protection circuit include: an electrostatic detection circuit; a low-voltage base-triggered electrostatic current discharge circuit, which is connected in parallel with the electrostatic detection circuit, and is isolated by a plurality of low-voltage substrates. The transistor is connected in series; wherein the base of each of the low-voltage substrate isolation type transistors is not connected to a substrate, and a breakdown voltage of the low-voltage base triggering electrostatic current discharge circuit is a breakdown of the low-voltage substrate isolation type transistors a sum of voltages; wherein each of the low-voltage substrate isolation type electro-crystal system has a gate, a gate doped region and a source doped region formed on a substrate; wherein the gate includes a gate insulating sidewall The drain doping region and the source doping region are respectively located on the two sides of the gate, and the drain doping region is between the side closest to the gate and the sidewall of the gate insulating layer of the gate Maintaining an interval; and a switching circuit comprising a plurality of semiconductor switching elements respectively connected between the electrostatic detecting circuit and the corresponding low-voltage substrate isolation type transistor, and being touched by the static detecting circuit Which corresponds to the low-pressure triggered electrically isolated crystal substrate is turned; group wherein each of the semiconductor switching element is connected to the substrate.

The high-voltage electrostatic protection circuit of the present invention mainly uses a low-voltage substrate isolation type transistor as an electrostatic current discharge path. Since the breakdown voltage of each low-voltage substrate isolation type transistor cannot be applied to a high-voltage system power supply, a plurality of low-voltage substrate isolation type transistors are used. (for example, 5V ISO-GRNMOS) is connected in series to form a low-voltage base-triggered electrostatic current discharge circuit whose breakdown voltage is the sum of the breakdown voltages of the low-voltage substrate isolation transistors, and is applicable to a high-voltage system power supply; In order to avoid false triggering of the low voltage of the low voltage substrate isolation type transistor to the substrate and the noise interference from the substrate, the base is not directly connected to the substrate, but is connected to the switch circuit; When the static detecting circuit detects the occurrence of static electricity, the switching circuit can be triggered to trigger the conduction of the low-voltage substrate isolation type transistors to smoothly eliminate the electrostatic current; further, due to the gate doping region of each low-voltage substrate isolation type transistor It is kept at a distance from the sidewall of the gate insulating layer of a gate, and its high electrostatic discharge tolerance can be relatively increased.

Furthermore, the main technical means used in the present invention to achieve the above object is that the low-voltage base-triggered electrostatic current discharge circuit comprises: a plurality of low-voltage substrate isolation type transistors connected in series; wherein each of the low-voltage substrate isolation type transistors The base electrode is not connected to a substrate, and a breakdown voltage of the low voltage base triggering electrostatic current discharge circuit is a sum of breakdown voltages of the low voltage substrate isolation type transistors; wherein: the low voltage substrate isolation type electric crystal system Forming a gate, a drain doping region and a source doping region on a substrate; wherein the gate comprises a gate insulating sidewall, and the drain doping region and the source doping region respectively Positioned on the two sides of the gate, and the drain-doped region maintains a space between the side closest to the gate and the sidewall of the gate insulating layer of the gate.

It can be seen from the above description that the low-voltage base-triggered electrostatic current discharge circuit of the present invention is applicable to a high-voltage system power supply, so that a plurality of low-voltage substrate isolation type transistors (for example, 5V ISO-GRNMOS) are connected in series to form a low-voltage base. Triggering an electrostatic current discharge circuit, the breakdown voltage is the sum of the breakdown voltages of the low-voltage substrate isolation type transistors; and avoiding the undervoltage of the low-voltage substrate isolation type transistor to the substrate and the noise from the substrate Interference and false triggering, the base is not directly connected to the substrate, and the drain doping region of each low-voltage substrate isolation type transistor is kept at a distance from the sidewall of the gate insulating layer of a gate to improve its high electrostatic discharge. Tolerance.

The present invention is directed to an improvement of a high voltage electrostatic protection circuit. The circuit characteristics and effects of the high voltage electrostatic protection circuit of the present invention will be described in detail below with reference to the drawings.

Referring to FIG. 1 , a first preferred embodiment of a high voltage electrostatic protection circuit of the present invention includes an electrostatic detection circuit 10 , a low voltage base triggered electrostatic current discharge circuit 20 , and a switch circuit 30 ; The low-voltage base-triggered electrostatic current discharge circuit 20 is connected in parallel to the electrostatic detection circuit 10, and the switch circuit 30 is connected between the electrostatic detection circuit 10 and the low-voltage base-triggered electrostatic current discharge circuit 20.

In this embodiment, as shown in FIG. 1, the electrostatic detecting circuit 10 includes a resistor R1, a capacitor C and an inverter 11; wherein the resistor R1 and the capacitor C are connected in series, and the inverter 11 is further connected. The resistor R1 and the capacitor C are connected in parallel, and an input terminal I/P of the inverter 11 is connected to the series connection node N1 of the resistor R1 and the capacitor C, and an output terminal O/P thereof is connected to The switch circuit 30.

In this embodiment, as shown in FIG. 1, the capacitor C is a first high voltage PMOS transistor, and the gate G is connected to the low potential terminal HV_VSS of a high voltage system power supply; and the inverter 11 includes one a second high voltage PMOS transistor 111 and a second high voltage NMOS transistor 112. The source S of the second high voltage PMOS transistor 111 is connected to the high potential terminal HV_VCC of the high voltage system power supply, and the second high voltage NMOS transistor is connected. The source S of the 112 is connected to the low potential terminal HV_VSS of the high voltage system power supply, and the gate G thereof is connected to the gate G of the second high voltage PMOS device 111, and is connected to the input terminal I of the inverter 11 P is connected, and the drain D of the second high voltage NMOS device 112 is connected to the drain D of the second high voltage PMOS device and is connected to the output terminal O/P of the inverter 11.

As shown in FIG. 1 , in the embodiment, the low-voltage base-triggered electrostatic current discharge circuit 20 includes a plurality of low-voltage substrate isolation type transistors 21, and the low-voltage substrate isolation type transistors 21 are connected in series; The base B of the low-voltage substrate isolation type transistor 21 is not connected to a substrate but is connected to the switch circuit 30. Since the low-voltage base-triggered electrostatic current discharge circuit 20 is formed by the low-voltage substrate isolation type transistors 21 connected in series, the breakdown voltage is the breakdown voltage of the series low-voltage substrate isolation type transistors 21. Adding, according to the voltage range of the high voltage system power source used, determining the breakdown voltage of the low voltage base trigger electrostatic current discharge circuit 20, and thereby determining the number of the low voltage substrate isolation type transistors 21 connected in series; In other words, the trigger voltage V _t and the breakdown voltage V _{B of} the low-voltage base-triggered electrostatic current discharge circuit 20 can be determined by serially connecting different numbers, as shown in the following table, wherein the data is 5V for the low-voltage substrate isolation type transistor. Isolated gate resistor NMOS transistor (Ioslated-Gate Resistance NMOS; ISO-GRNMOS) voltage data. <TABLE border="1"borderColor="#000000"width="85%"><TBODY><tr><td> 5V ISO-GRNMOS Quantity</td><td> Trigger Voltage V<sub>t</ Sub>(V) </td><td> Crash voltage V_B(V) </td></tr><tr><td> 2 </td><td> 16.1 </td><td> 22 </td></tr><tr><td> 3 </td><td> 25.24 </td><td> 33 </td></tr><tr><Td> 4 </td><td> 34.38 </td><td> 44 </td></tr><tr><td> 5 </td><td> 48.53 </td><td> 55 </td></tr><tr><td> 6 </td><td> 60.55 </td><td> 66 </td></tr></TBODY></TABLE>

In this embodiment, as shown in FIG. 2, each of the low-voltage substrate isolation type transistors 21 is a low-voltage NMOS transistor, and the semiconductor structure 211 of each of the low-voltage NMOS transistors is formed in a P-type substrate 212. The P-type substrate 212 is formed with an N-type deep well 213 (DEEP N-WELL) in an element region of each of the low-voltage NMOS transistors, and a P-type well 214 is formed in the N-type deep well 213 (P- WELL); a drain doping region 215, a source doping region 216 and a base doping region 217 of each of the low voltage NMOS transistors are respectively formed in the P-type well 214; and each of the low voltage NMOS The gate G of the transistor is formed on the P-type well 214 and located between the drain doping region 215 and the source doping region 216; wherein the drain doping region 215 and the source doping The region 216 is located on the two sides of the gate G, and the gate doping region 215 is spaced from the side closest to the gate G to the gate insulating layer sidewall 218 of the gate G to maintain a gap d; In addition, the source doping region 216 may also maintain a spacing d between the side closest to the gate G to the gate insulating layer sidewall 218 of the gate G; the base doping region 217 is formed. The other side of the source doping region 216, to improve the efficiency of the trigger. Moreover, in the semiconductor structure 211 of the low-voltage substrate isolation type transistor 21, a metal germanium 215a, 216a is formed on the drain doping region 215 and the source doping region 216, respectively, and the drain doping region 215 is formed. The upper metal halide 215a does not completely cover the gate doped region 215, but only partially covers the gate doped region 215.

Therefore, the semiconductor structure 211 of each of the low-voltage substrate isolation type transistors 21 is formed in the P-type well 214 of the P-type substrate 212, and the P-type well 214 is surrounded by the N-type deep well 213, and the P The base substrate 212 is isolated, so that the base B of each of the low-voltage NMOS transistors 21 is not connected to the substrate 212, effectively improving the withstand voltage of the low-voltage NMOS transistor and blocking interference from the substrate 212, thereby avoiding false triggering; The drain doping region 215 and the source doping region 216 of the low voltage NMOS transistor are respectively located on two sides of the gate G, and are respectively spaced apart from the nearest sidewall G of the gate G insulating layer 218 by a certain interval d. The electrostatic discharge withstand is improved by the distance D from the drain D and the distance between the polysilicon layer of the gate G, or the distance between the drain D and the source S and the polysilicon layer of the gate G, respectively.

Further, the gate G of each of the low-voltage NMOS transistors is connected to its source S, the base B thereof is connected to the switch circuit 30, and the drain D is connected to the source S of the low-voltage substrate isolation type transistor 21 of the previous stage. The drain D of the first stage low voltage NMOS transistor 21 of the low voltage base triggered electrostatic current discharge circuit 20 is connected to the high voltage terminal HV_VCC of the high voltage system power supply, and the source S of the last stage low voltage NMOS transistor 21 is connected to The low voltage terminal HV_VSS of the high voltage system power supply. Furthermore, a resistor R2 may be further connected between the gate G of each of the low voltage NMOS transistors and the source S.

In this embodiment, as shown in FIG. 1 , the switch circuit 30 includes a plurality of semiconductor switching elements 31 connected to the static detecting circuit 10 and the corresponding low-voltage substrate isolation type transistor 21, and is subjected to The static detecting circuit 10 is triggered to trigger its corresponding low-voltage substrate isolation type transistor 21 to be turned on. Each of the semiconductor switching elements 31 is a first high voltage NMOS transistor, and is connected to the first semiconductor switching element 31 of the first stage low voltage NMOS transistor 21, as shown in FIG. Formed in the P-type substrate 212, the base B _{H is} directly connected to the substrate 212, the drain D _{H is} formed in a lightly doped region NDD, and the drain D _H system is together with the gate G _H Connected to the output O/P of the electrostatic detection circuit 10, the source S _H is connected to the base B of its corresponding low voltage NMOS transistor.

The above is a circuit diagram description of the first preferred embodiment of the high voltage static electricity protection circuit of the present invention. The circuit operation of the high voltage static electricity protection circuit will be further described below.

As shown in FIG. 1, when static electricity occurs, the first high voltage PMOS element as the capacitor C is regarded as a short circuit, and the input terminal I/P voltage of the inverter 11 is pulled down to the low potential HV_VSS of the high voltage system power supply; When the second high voltage PMOS transistor 111 is turned on, and the second high voltage NMOS transistor 112 is not turned on, the output O/P voltage of the inverter 11 is pulled up to the high potential HV_VCC of the high voltage system power supply. Thus, the first high voltage NMOS transistors of the switch circuit 30 are turned on, and the first high voltage NMOS transistors that are turned on trigger the base B of the corresponding low voltage NMOS transistor 21 to turn on all the low voltage NMOS transistors 21. Thus, the low-voltage base-triggered electrostatic current discharge circuit 20 constitutes an electrostatic discharge current path, and the electrostatic current is smoothly eliminated.

Referring to FIG. 4, it is a second preferred embodiment of the high voltage electrostatic protection circuit of the present invention, which is substantially the same as the first preferred embodiment, and both includes an electrostatic detecting circuit 10 and a low voltage base. The electrostatic current discharge circuit 20' and the switch circuit 30 are triggered; but the low voltage base trigger electrostatic current discharge circuit 20' includes a plurality of low voltage substrate isolation type transistors 21', and the low voltage substrate isolation type transistors 21' are mutually The low voltage substrate isolation type transistor 21' may be a low voltage NMOS transistor. The semiconductor structure 211' of each of the low-voltage NMOS transistors shown in FIG. 5A and FIG. 5B is formed in a P-type substrate 221, and the P-type substrate 221 is formed with a N in the component region of each of the low-voltage NMOS transistors. Forming a buried layer 222 (N+ Buried Layer; NBL), further forming a high voltage P-type well 223 on the N-type buried layer 222, and finally forming a P-type well 224 in the high-voltage P-type well 223; A high-voltage N-type well 225 is formed on the outer side of the high-voltage P-type well 223, and a drain-doped region 215, a source-doped region 216, and a base of each of the low-voltage NMOS transistors. The pole doped regions 217 are respectively formed in the P-type well 224; and the gate G of each of the low-voltage NMOS transistors is formed on the P-type well 224 and located in the drain-doped region 215 and the source Between the doped regions 216, wherein the drain doping region 215 and the source doping region 216 are respectively located on two sides of the gate G, and the drain doping region 215 is closest to the gate G. A gap d is maintained between the sidewalls 218 of the gate insulating layer G of the gate G; furthermore, the source doping region 216 is closest to the gate of the gate to the gate of the gate G A spacing d may also be maintained between the sidewalls 218 of the edge layer; the base doping region 217 is formed on one side of the source doping region 216 to improve the triggering efficiency. Moreover, in each of the semiconductor structures 211' of the present embodiment, a metal germanium 215a, 216a is formed on the drain doping region 215 and the source doping region 216, respectively, and the drain doping region 215 is formed. The metal telluride 215a does not completely cover the drain doped region 215, but only partially covers the drain doped region 215.

Therefore, the semiconductor structure 211 of each of the low-voltage substrate isolation type transistors 21' is formed in the P-type well 224 of the P-type substrate 221, and the P-type well 224 is composed of the high-voltage P-type well 223 and the high-voltage N-type well. The 225 and the N-type buried layer 222 are surrounded by the P-type substrate 221, so that the base B of each of the low-voltage NMOS transistors 21' is not connected to the substrate 221, thereby effectively improving the low-voltage NMOS transistor. Withstand voltage and block interference from the substrate 221; and the drain doping region 215 and the source doping region 216 of each of the low voltage NMOS transistors are respectively located on two sides of the gate G, and respectively with the nearest gate The sidewall G of the gate G insulating layer 218 is maintained at a certain interval d, and the distance between the gate D and the polysilicon layer of the gate G is pulled by the drain D, or the drain D and the source S are respectively opened and opened by the gate G. The distance of the layers to increase the electrostatic discharge tolerance.

The drain D of the first stage low voltage NMOS transistor 21' is connected to the high voltage terminal HV_VCC of the high voltage system power supply, and the source S of the last stage low voltage NMOS transistor 21' is connected to the low voltage terminal HV_VSS of the high voltage system power supply. In addition, the gate G of each of the low-voltage NMOS transistors is connected to the source S and the base B thereof, and the base B is further connected to the switch circuit 30, and the drain D is connected to the front-stage low-voltage substrate isolation type transistor. Source S of 21'. Moreover, the high voltage N-well 225 is formed with an N-type doping region 225a, and an insulating layer 225b is formed between the high-voltage N-type well 223, and the drain D of each of the low-voltage NMOS transistors 21' is further connected to the N Type doped region 225a. Furthermore, a resistor R2 may be further connected between the gate G of each of the low voltage NMOS transistors and the source S.

In this embodiment, as shown in FIG. 4, the switch circuit 30 includes a plurality of semiconductor switching elements 31, and each of the semiconductor switching elements 31 is connected to the static detecting circuit 10 and the corresponding low-voltage substrate isolation type transistor 21', and Triggered by the electrostatic detecting circuit 10 to trigger the corresponding low-voltage substrate isolation type transistor 21' to be turned on. Each of the semiconductor switching elements 31 is a first high voltage NMOS transistor, and is connected to the first semiconductor switching element 31 of the first stage low voltage NMOS transistor 21, as shown in FIG. Formed in the P-type substrate 221, the base B _{H is} directly connected to the substrate 221, the drain D _{H is} formed in a lightly doped region NDD, and the drain D _H is together with the gate G _H Connected to the output O/P of the electrostatic detection circuit 10, the source S _H is connected to the base B of its corresponding low voltage NMOS transistor.

The above is a circuit diagram description of the second preferred embodiment of the high voltage static electricity protection circuit of the present invention. The circuit operation of the high voltage static electricity protection circuit will be further described below.

As shown in FIG. 4, when static electricity occurs, the first high voltage PMOS element as the capacitor C is regarded as a short circuit, and the input terminal I/P voltage of the inverter 11 is pulled down to the low potential HV_VSS of the high voltage system power supply; When the second high voltage PMOS transistor 111 is turned on, and the second high voltage NMOS transistor 112 is not turned on, the output O/P voltage of the inverter 11 is pulled up to the high potential HV_VCC of the high voltage system power supply. Thus, the first high voltage NMOS transistors of the switching circuit 30 are turned on, and the first high voltage NMOS transistors that are turned on trigger the base B of the corresponding low voltage NMOS transistor 21' to make all the low voltage NMOS transistors 21 'Conduction; thus, the low-voltage base trigger electrostatic current discharge circuit 20' constitutes an electrostatic discharge current path, and the electrostatic current is smoothly eliminated.

In summary, the high-voltage electrostatic protection circuit of the present invention mainly uses a low-voltage substrate isolation type transistor as an electrostatic current discharge path. Since the breakdown voltage of each low-voltage substrate isolation type transistor cannot be applied to a high-voltage system power supply, a plurality of low voltages are used. The substrate-isolated transistors are connected in series to form a low-voltage base-triggered electrostatic current discharge circuit, and the breakdown voltage is a sum of breakdown voltages of the low-voltage substrate isolation transistors, and is applicable to a high-voltage system power supply; however, The anode of each low-voltage substrate isolation type transistor is prevented from being erroneously triggered by the undervoltage of the substrate and the noise interference from the substrate, and the base is not directly connected to the substrate, but is connected to the switch circuit; thus, when the electrostatic inspection Knowing that the circuit detects the occurrence of static electricity, it can trigger the switching circuit to trigger the conduction of the isolation transistors of the low-voltage substrate to smoothly eliminate the electrostatic current; in addition, due to the gate doping region and the gate of each low-voltage substrate isolation type transistor a gate of the gate insulating layer is maintained at a spacing, or a drain and a source doped region are respectively connected to a gate of a gate Edges of each sidewall layers to maintain a spacing between its high ESD tolerance can be relatively increased.

The above is only the embodiment of the present invention, and is not intended to limit the scope of the present invention. The present invention has been disclosed by the embodiments, but is not intended to limit the invention, and any one of ordinary skill in the art, In the scope of the technical solutions of the present invention, equivalent modifications may be made to the equivalents of the embodiments of the present invention without departing from the technical scope of the present invention. Any simple modifications, equivalent changes and modifications made to the above embodiments are still within the scope of the technical solutions of the present invention.

10‧‧‧Electrostatic detection circuit
11‧‧‧Inverter
111‧‧‧Second high voltage PMOS transistor
112‧‧‧Second high voltage NMOS transistor
20‧‧‧Low-voltage base triggered electrostatic current discharge circuit
21, 21'‧‧‧ Low-voltage substrate isolation type transistor
211, 211'‧‧‧ semiconductor structure
212‧‧‧Substrate
213‧‧‧N type deep trap
213a‧‧‧N-doped area
214‧‧‧P-well
215‧‧‧汲polar doped area
215a‧‧‧metal telluride layer
216‧‧‧ source doped area
216a‧‧‧metal telluride layer
217‧‧‧base doping area
218‧‧‧ gate insulation sidewall
221‧‧‧Substrate
222‧‧‧N type buried layer
223‧‧‧High-voltage P-well
224‧‧‧P-type well
225‧‧‧High voltage N-well
225a‧‧‧N-doped area
225b‧‧‧Insulation
30‧‧‧Switch circuit
31‧‧‧Semiconductor switching elements
311‧‧‧Semiconductor structure
50‧‧‧Static detection circuit
60‧‧‧Gate-triggered transistor

Figure 1 is a circuit diagram of a first preferred embodiment of the high voltage electrostatic protection circuit of the present invention. Figure 2 is a semiconductor block diagram of the low voltage base triggered electrostatic current discharge circuit of Figure 1. FIG. 3 is a semiconductor structural diagram of one of the semiconductor elements of the low-voltage base-triggered electrostatic current discharge circuit of FIG. 1 and one of the semiconductor switching elements of a switching circuit. Figure 4 is a circuit diagram showing a second preferred embodiment of the high voltage electrostatic protection circuit of the present invention. 5A and 5B are diagrams showing a semiconductor structure of the low-voltage base-triggered electrostatic current discharge circuit of FIG. FIG. 6 is a semiconductor structural diagram of one of the semiconductor elements of the low-voltage base-triggered electrostatic current discharge circuit of FIG. 4 and one of the semiconductor switching elements of a switching circuit. Figure 7: A circuit diagram of a high voltage electrostatic protection circuit.

Claims (15)

A high-voltage electrostatic protection circuit with a low-voltage base-triggered electrostatic current discharge circuit, comprising: an electrostatic detection circuit; a low-voltage base-triggered electrostatic current discharge circuit, which is connected in parallel with the electrostatic detection circuit, and is isolated by a plurality of low-voltage substrates The crystal is connected in series; wherein the base of each of the low-voltage substrate isolation type transistors is not connected to a substrate, and a breakdown voltage of the low-voltage base triggering electrostatic current discharge circuit is a breakdown voltage of the low-voltage substrate isolation type transistors Each of the low-voltage substrate isolation type electro-crystal system has a gate, a gate doped region and a source doped region formed on a substrate; wherein the gate includes a gate insulating sidewall The drain doping region and the source doping region are respectively located on the two sides of the gate, and the drain doping region is maintained between the side closest to the gate and the sidewall of the gate insulating layer of the gate And a switching circuit comprising a plurality of semiconductor switching elements respectively connected between the electrostatic detecting circuit and the corresponding low-voltage substrate isolation type transistor, and being touched by the static detecting circuit Which corresponds to the low-pressure triggered electrically isolated crystal substrate is turned; group wherein each of the semiconductor switching element is connected to the substrate. The high voltage electrostatic protection circuit of claim 1, wherein the source doping region of each of the low voltage substrate isolation transistors is maintained between a side closest to the gate and a sidewall of the gate insulating layer of the gate. interval. The high voltage electrostatic protection circuit of claim 2, wherein: the substrate is a P-type substrate, a plurality of N-type deep wells are formed on the P-type substrate, and a P-type well is formed in each of the N-type deep wells; The low-voltage substrate isolation type electric crystal system is a low-voltage NMOS transistor, and the drain-doped region and the source-doped region are formed in the P-type well, and the gate is formed on the P-type well, and Positioned between the drain doping region and the source doped region; and each of the semiconductor switching elements is a first high voltage NMOS transistor, and a semiconductor structure is formed in the P-type substrate to have a base Directly connected to the P-type substrate, and the drain is formed in a lightly doped region, and the drain and the gate are connected together to the electrostatic detecting circuit. The high voltage electrostatic protection circuit of claim 2, wherein: the substrate is a P-type substrate, the P-type substrate is formed with a plurality of N-type buried layers, and each of the N-type buried layers is formed with a high-voltage P-type well. a P-type well is formed in the high-voltage P-type well; wherein a high-voltage N-type well is formed on the outer side of the N-type buried layer and the high-voltage P-type well; each of the low-voltage substrate isolation type electro-crystal system is a low-voltage NMOS a crystal, the drain doped region and the source doped region are formed in the P-type well, the gate is formed on the P-type well, and is located in the drain doped region and the source is doped Between the inter-cells; and each of the semiconductor switching elements is a first high-voltage NMOS transistor, the semiconductor structure of which is formed in the P-type substrate, the base thereof is directly connected to the P-type substrate, and the drain is formed In a lightly doped region, the drain and the gate are connected to the electrostatic detection circuit. The high voltage electrostatic protection circuit of claim 4, wherein the high voltage N-type well of each of the low voltage NMOS transistors forms an N-type doped region, and an insulating layer is formed between the high voltage P-type well; A drain of the NMOS transistor is further coupled to the N-type doped region of the high voltage N-well. The high voltage electrostatic protection circuit according to any one of claims 1 to 5, wherein the gate doped region and the germanium source doped region are respectively formed with a metal telluride, and the metal telluride on the drain doped region Partially covering the drain doped region. The high voltage electrostatic protection circuit according to any one of claims 3 to 5, wherein each of the low voltage substrate isolation type transistors further comprises a first resistor connected to a gate and a source of the corresponding low voltage substrate isolation type transistor. between. The high voltage electrostatic protection circuit of claim 2, wherein the electrostatic detection circuit comprises: a second resistor connected in series with a capacitor; and an inverter connected to the second resistor and capacitor connected in series In parallel, an input terminal is connected to the series connection node of the second resistor and the capacitor, and an output end thereof is connected to each semiconductor switching element of the switch circuit. A low-voltage base-triggered electrostatic current discharge circuit includes a plurality of low-voltage substrate isolation type transistors connected in series; wherein a base of each of the low-voltage substrate isolation type transistors is not connected to a substrate, and the low-voltage base triggers electrostatic current discharge a breakdown voltage of the circuit is a sum of breakdown voltages of the low-voltage substrate isolation type transistors; wherein: each of the low-voltage substrate isolation type electro-crystal system forms a gate, a drain doping region and a source on a substrate a pole doped region; wherein the gate includes a gate insulating sidewall, and the gate doped region and the source doped region are respectively located on the gate side, and the gate doped region is away from the gate A space is maintained between the very nearest side and the sidewall of the gate insulating layer of the gate. The low-voltage base-triggered electrostatic current discharge circuit of claim 9, wherein the source-doped region of each of the low-voltage substrate isolation transistors is from a side closest to the gate to a sidewall of the gate insulating layer of the gate The interval is maintained at an interval. The low-voltage base-triggered electrostatic current discharge circuit of claim 10, wherein: the substrate is a P-type substrate, the P-type substrate is formed with a plurality of N-type deep wells, and a P is formed in each of the N-type deep wells. And the low-voltage substrate isolation type electric crystal system is a low-voltage NMOS transistor, wherein the drain-doped region and the source-doped region are formed in the P-type well, and the gate is formed in the P The well is located between the drain doped region and the source doped region. The low-voltage base-triggered electrostatic current discharge circuit of claim 10, wherein: the substrate is a P-type substrate, and the P-type substrate is formed with a plurality of N-type buried layers, and each of the N-type buried layers is formed a high-voltage P-type well having a P-type well formed therein; wherein a high-voltage N-type well is formed over the N-type buried layer and outside of the high-voltage P-type well; and each of the low-voltage substrate isolation type electro-crystal system a low-voltage NMOS transistor, the drain-doped region and the source-doped region are formed in the P-type well, the gate is formed on the P-type well, and is located in the drain-doped region And between the source doped regions. The low-voltage base-triggered electrostatic current discharge circuit of claim 12, wherein the high-voltage N-type well of each of the low-voltage NMOS transistors forms an N-type doped region, and an insulating layer is formed between the high-voltage P-type well; A drain of each of the low voltage NMOS transistors is further connected to the N-type doped region of the high voltage N-type well. The low-voltage base-triggered electrostatic current discharge circuit according to any one of claims 9 to 13, wherein a metal telluride is formed on the drain-doped region and the drain-doped region, respectively, and the drain-doped region is formed. The upper metal halide portion partially covers the drain doped region. The low-voltage base-trigger electrostatic current discharge circuit according to any one of claims 11 to 13, wherein each of the low-voltage substrate isolation type transistors further includes a first resistor connected to a gate of the corresponding low-voltage substrate isolation type transistor. Between the source and the source.