TW432545B - Method and improved SOI body contact structure for transistors - Google Patents
Method and improved SOI body contact structure for transistors Download PDFInfo
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- TW432545B TW432545B TW088101968A TW88101968A TW432545B TW 432545 B TW432545 B TW 432545B TW 088101968 A TW088101968 A TW 088101968A TW 88101968 A TW88101968 A TW 88101968A TW 432545 B TW432545 B TW 432545B
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- 238000000034 method Methods 0.000 title claims abstract description 17
- 238000004519 manufacturing process Methods 0.000 claims abstract description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 239000013078 crystal Substances 0.000 claims 3
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 claims 2
- 239000000463 material Substances 0.000 claims 2
- PCTMTFRHKVHKIS-BMFZQQSSSA-N (1s,3r,4e,6e,8e,10e,12e,14e,16e,18s,19r,20r,21s,25r,27r,30r,31r,33s,35r,37s,38r)-3-[(2r,3s,4s,5s,6r)-4-amino-3,5-dihydroxy-6-methyloxan-2-yl]oxy-19,25,27,30,31,33,35,37-octahydroxy-18,20,21-trimethyl-23-oxo-22,39-dioxabicyclo[33.3.1]nonatriaconta-4,6,8,10 Chemical compound C1C=C2C[C@@H](OS(O)(=O)=O)CC[C@]2(C)[C@@H]2[C@@H]1[C@@H]1CC[C@H]([C@H](C)CCCC(C)C)[C@@]1(C)CC2.O[C@H]1[C@@H](N)[C@H](O)[C@@H](C)O[C@H]1O[C@H]1/C=C/C=C/C=C/C=C/C=C/C=C/C=C/[C@H](C)[C@@H](O)[C@@H](C)[C@H](C)OC(=O)C[C@H](O)C[C@H](O)CC[C@@H](O)[C@H](O)C[C@H](O)C[C@](O)(C[C@H](O)[C@H]2C(O)=O)O[C@H]2C1 PCTMTFRHKVHKIS-BMFZQQSSSA-N 0.000 claims 1
- 241000283690 Bos taurus Species 0.000 claims 1
- 230000005611 electricity Effects 0.000 claims 1
- 238000009434 installation Methods 0.000 claims 1
- 229910052742 iron Inorganic materials 0.000 claims 1
- 239000004576 sand Substances 0.000 claims 1
- 229910052814 silicon oxide Inorganic materials 0.000 claims 1
- 210000000988 bone and bone Anatomy 0.000 abstract description 7
- 230000000694 effects Effects 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 27
- 150000004767 nitrides Chemical class 0.000 description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 8
- 238000001020 plasma etching Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 3
- 239000002019 doping agent Substances 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 3
- 235000006508 Nelumbo nucifera Nutrition 0.000 description 2
- 240000002853 Nelumbo nucifera Species 0.000 description 2
- 235000006510 Nelumbo pentapetala Nutrition 0.000 description 2
- 238000004364 calculation method Methods 0.000 description 2
- 230000002079 cooperative effect Effects 0.000 description 2
- 230000000875 corresponding effect Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 229910007277 Si3 N4 Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 208000022531 anorexia Diseases 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 206010061428 decreased appetite Diseases 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 210000000689 upper leg Anatomy 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
- H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
- H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
Landscapes
- Thin Film Transistor (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
Description
經濟部中央螵準局員工消費合作社印製 鼸43254 5 五、發明説明(i ) 發明領域:本發明係關於電晶體,特別係關於改良s〇i本 體接觸結構及於製造環境形成此種結構之方法。 相關申請案:與本案同時提出申請之_請案名稱「具有 改良SOI本體接觸結構之電晶體」,美國專利申請案第號 ,申請曰一與本案相關且由同一發明人提出申請並讓與相 同受讓人亦即美國紐约州安莫克國際商務機器公司。 詞彙: BC表示本體接觸型電晶體。 P C表示多晶<5夕結構形狀。 R X表示場氧化物開口暴露出活性矽之形狀。 △ 爲製造成品尺寸於設計時緣製尺寸之差。 狗骨頭或狗骨表示圖1 1所示具有類似「Η」、狗骨或股 骨形狀之接觸形狀。 顶對頂Γ Τ」表示概略表示兩個「τ」字形,其彼此爲鏡 V,且如圖丨〇示例説明具有頂端於概略平行方向對正。 談册商標:S / 3 9 0及ί Β Μ爲美國紐约州安莫克國際商務機器 公司之註册商標:及蓮花爲其子公司蓮花開發公司之註册 商標’此乃紐約州安莫克國際商務機器公司之獨立子公司 。其它名稱爲IBM公司或其它公司之註册商標或商品名。 背景: 將參照如下圖8繪製説明標準非本體接觸型電晶體。標示 爲「s」及rD」之區域表示電晶體之源極及及極3閘極標 示爲「閘極」》此種電晶髗之有效寬度僅藉氧化物之厌父開 口見度測定’ RX開口於本示例説明例爲外部矩形。任何△ 未紙蘇尺度边/η中郎家轉这f CNS ) A4规格(:丨ox29?公.空) 11:--:-----装------II------泉 C請先"讀背面之注意事項再"寫本頁) 經濟部中央標準局頁工消費合作社印袈 14 325 4 5 at ______B7__五、發明説明(2 ) -W係來自於氧化物開口之偏移。計算寬度時須包括的公差 有R X影像大小及△ - w之任何公差。特別使用現有方法, 可改良標準電晶體結構’且可用於製造複雜電路例如IBM S/390處理器使用的電路3先前及現有s〇i「bc」型本體接 觸結構之問題爲有效電晶體寬度改變起因隨p C與Rx階間 之覆蓋層公差改變。 發明概述: 本發明示例説明於圖7之上圖,提供一種電晶體,其中電 晶體之頂邵件可且較同現有結構,但底部件爲頂部件之鏡 像,且於底部件中’ PC對RX復蓋層之影響顚倒,「向上」 未對正將使裝置寬度變大,而「向下」未對正將使裝置寬 度縮小。如此由有效電晶體宽度去除覆蓋層公差。 圖式之簡單説明: 圖1係以圖1 A - 1 D逐步説明,其顯示圖7沿線1 D - - 1 D所 取之電晶體剖面圖,此處將形成本體接觸。 圖2以圖2 A - 2 D示例説明沿圖7之剖面圖2 D — 2 D施用至 閘極之各步骤。 圖3顯示#刻圖7電晶體之氮化物層及多晶碎層後沿線 1 D - - 1 D所取之相同區域。 圖4示例説明次一步驟,其中服貼CVD氮化物(或氧化饬-氮化物)層已經沉積於晶圓上。 圓5示例說明於習知RIE方法方向性蚀刻介電層而接近基 材及形成側壁= 圖6顯示沉積多晶矽層140,以適當攙雜劑攙雜,圖樣化 (請先閱讀背面之注意事項再填寫本頁) 本紙乐尺度適月中國國家標準(CNS 规格1 N0X297公釐) A7 M32545 五、發明説明(3 ) 及退火而形成圖7示例説明之電晶體之本體接觸。 圖7不例説明根據本發明構成之電晶體之較佳具叫 視圖。 、吆例之項 圖8不例説明標準非本體接觸型電晶體。 圖9示例説明如美國專利5,4〇5,795所述之一「Bc」刑 接觸型電晶體,其表示於圖工_ 7及〗〇示例説明之較之本靉 例中藉本發明改良之先前技術;及 A圭具體 圖1 〇爲藉前述方法製造之圖7新穎S0I電晶體之 例之視圖。 \圭具體 圖I〗顯示藉狗骨頭光罩方法製造之本發明之替代 形具體例。 β頊 發明之詳細說明: - 於敘述新穎SOI電晶體(如圖]0示例説明)之較佳具體例之 W,將説明標準非本體接觸型電晶體,通常繪製爲如下圖8 所π。標示爲「S」及「D」之區域表示本體接觸型晶格之 電晶體源極及汲極。閘極標示爲「閘極」一詞。此種電晶 體之有效寬度僅係由RX開口寬度決定’ Rx開口於本示例 説明例爲外部矩形。任何△_ w係來自於氧化物開口之偏移 。计算見度時須包括之公差有R X影像大小及△,W之任何 公差。 「B C」型本體接觸型電晶體其係顯示於圖9 3此乃美 國專利5,405,795所述電晶體》如同圖8,標示爲「s」及「 D」之區域表示電晶體之源極及汲極,而閘極標示爲「閘 極」一詞=此外加上新的接觸標示爲「本體」,如圖9所示 -6- 本纸疚尺度適用中國國家標準(CNS ) A4規格(2!0';< 297公釐) — ^ ^ Μ------訂------泉 Α靖先閱讀背面之注意事項再填考本頁} 經濟部中央標準局—工消资合作社印製 經濟部央標準局負工消費合咋社印製 1432545 A7 B7 五、發明説明(4 ) Ώ假定本體接觸係以作爲電晶體本體之樣本極性(及源極與 汲極I相反極性)攙雜。如此進行之光罩爲求簡明起見並未 顯示3 圖9示例説明之此型現有本體接觸型電晶體中’寬度係由 RX於左邊但由PC於另一邊決定。左緣之A_w係同圖8示 例説明之標準電晶體,亦即氧化物開口偏位。但於右緣, A - W係來自於電晶體閘極之「τ」字形部件下方電流之「 有效見度」。除了標準電晶體之公差外,須包括P C與R X 間之覆蓋層公差。 . 例如圖9中,若P C比R X更爲「向左」對正,則裝置寬度 將減少該數量。若PC比RX Γ向上」或「向下」對正,則 對^ η日aa見度典影響。若比R )(更「向右」對正’則裝置宽 度將增加該數量。 本揭示内容之結構改良可利用製造時使用的處理器達成 ,處理器將參照圖1 - 7説明及顯示於圖〗〇。如圖1 〇所示, 幸父佳具體例中,SOI本體接觸型電晶體之左部件同圖9。但 由上方視電晶體閘極凹凸部之右部件爲左部件之鏡像。 如前述,標示爲「SJ及rDj之區域表示本體接觸型電晶 體之源極及汲極,閘極標示爲「閘桎」一詞,及本體接觸 標π A「本體」一詞。假定本體接觸係以電晶體本體之樣 本極性(及源極及汲極之相反極性)攙雜。爲求簡明起見, 達成此項目的之光罩未顯示於附圖。 圖1 0所示較佳具體例之右方,PC對RX覆蓋層之影響顚 倒:「向左」未對正將使裝置寬度加大,而「向右」未對 --- I----n ----I -訂-------泉--- (請先閱讀背面之注意事項再填寫本頁) (CNS ) A4規格(2丨0:<297公旖) 經濟部中央檩华局員工消費合作社印製 A7 B7 五、發明説明(5 正將使裝置寬度縮小。 當使用圖ίο之四凸部且如圖10形成之二電晶體爲並聯連 结’「SJ連結至rs」’「D」連結至「D」及閘極連結 至閘極時,P C對RX未對正之影響將抵消,任何右方尺寸 的改變將由等量左方相反改變補償。 替代實施例顯示於圖U (「狗骨頭形J版本)。端子伊示 以字母「S j及「D」來表示源極及汲椏。「閘極」—气表 示閘極’及「本體」-詞表示本體連結點。本實施例具= 圖1 0之相同性質’亦即於裝置左方之P C對R χ未對正將於 裝置右方被抵消。 1 主„發明之製造方法 此種結構之最佳實務爲如圖1 〇所示之自行對正本體接觸 型結構,表示SOI電晶體之較佳具體例。 如圖7之上圖示例説明,提供一電晶體晶格其中電晶體頂 邵件可且較佳同現有結構,但底部件爲頂部件之鏡像:及 底部件中,PC對RX覆蓋層之影響顚倒,閘極之「向上」 未對正將使裝置寬度變寬’而閘極之「向下」未對正將使 裝置寬度縮,]、。如此由有效電晶體寬度去除覆蓋層公差: 其 施方式係標示爲「本體」區域使用適用於標示爲p c 之閘極的凹凸部部件作爲擴散光罩攙雜至高濃度。當然也 可对各「PC」形之Γ T」罕形擴散光罩部件下方之本體區 作接觸。 圖7中’根據本發明之電晶體之頂視圖顯示源極u 6及及 極U4由閘極U0隔開,其具有自行對正本體接觸B(本體接 -8- 尽纸張尺度適用中國國家標窣(CNS ) A4規格ί 210X 297公釐) ^ . . 裝 訂 ----線 (請先閔讀背面之注意事項再續寫本頁} 經濟部智越財產局員工消費合作社印製 P4 325 4 5 A— A/ -------- 五、發明說明(6) 觸概略以編號212標示)成形於一端3供參考目的之用,第 一軸線稱作平行線2D一2D,由源極延伸至汲極;及第二 抽線稱作間極之向下延伸寬度。圖1 A _丨〇顯示圖7沿線1 〇 --1 D之别面圖’此處將形成本體接觸。5〇1晶圓之含下基材 1 〇 ’ soi氧化物(二氧化矽)層5 〇及部分薄矽層1〇2之部分已 經被圖樣化’然後藉習知步驟分離,習知步驟係將層1〇2之 非期望邵分氧化而形成氧化物6 〇。示例説明之具體例中, 沿源極與汲極間之第—軸線(沿線1 D _ q D )之長度爲約1微 米或以上,MOS裝置之對應閘極長度小於〇 5微米5例如層 102之厚度小於80毫微来3 圖1 B顯tf μ區經歷數個中間步驟之後=已經形成習知閘 極堆@物’包括5 -〗〇毫微米閘極氧化物丨〇 1,( i 〇〇· 2〇〇毫微 米)夕晶碎(poly)層11 〇其用於提供電晶體閘極,及(丨2毫微 米)保沒性亂化物(Si3 N4)閘極介電層1 〇7 ;且已經植入源極 1 16及汲極1丨4且已經退火。 圖1 C中,薄的(]◦毫微米)氧化物層生長於閘極堆疊物邊 緣,隨後沉積3 〇毫微米(:乂1;)氧化物層及蝕刻而於習知方法 形成外侧閘極側壁間隔物〗1 5。 外倒間隔物不僅用於提供LDd源極及汲極,同時也用於 隔離問極與多晶矽升高之源極及汲極接觸件1〇6及1〇8,其 /人.k由選擇性沉積1 50毫微米攙雜CVD多晶矽於源極及汲極 上方之孔眼形成。間隔物1〇6與1〇8頂端藉熱蓋層氧化物7〇 (1 20毫微米)密封3範例具體例中,蓋層氧化物凸起超出閘 極介電層1 07頂端之量足夠於稍後步驟界定—個自行對正的 -9- 本紙張尺度適用t國國家標準(CNS)A4規格(210 X 297公釐) (請先閱讀背面之注意事項再填寫本頁) I a^i n n i I -"s ^4 325 4 5 經濟部智慧財產局員工消費合作社印制衣 A7 B7 五、發明說明(7) 孔眼。沉積一層CVD氮化物服貼層120(圖1D)於閘極上,其 厚度足夠提供側壁夠厚而可保護閘極(大於閘極厚度之半) ’冗成本圖顯示之各步驟。 圖2A-2D顯示相同步驟應用於具有「tj字形凹凸部之 閘極’本圖係由晶圓「頂端」檢視P C結構,貫穿圖7之待 形成閘極結構之剖面2 D - - 2 D。注意圖2 D中氮化物120之側 壁接近會合閘極U 0。圖7以標示爲180之虛線框出之非重要 性光罩可選擇性用於圖1D及2 D所示步驟之後,用於僅暴 露本體接觸區(圖7之212)及保護閘極。虛線125示例説明氮 化物120厚度夠大而使側壁會合的情況,稱作重疊厚度。該 例中無需選擇性框出的光罩。示例説明之具體例中,若閘 極頂端爲名目250毫微米之源極與汲極間距及氮化物12〇之 厚度爲1 5 0朵微米將確保閘極於孔眼蚀刻過程受到保護而無 須框出光罩。 圖3顯示沿線1 D - - 1 D之相同區,但於習知三步骤式氮化 物、多晶矽及氧化物反應性離子蝕刻(RIE)使用適當氣體姓 刻氮化物層120及1 〇7及多晶矽層1 10,停止於矽層1 〇2,及留 下孔眼212'其將容納本體接觸212之後。於此階段,有一由 閘極多晶矽丨10组成之於閘極氧化物1 〇 1上方之侧壁件及由 氮化物120形成的頂側壁,全部皆以編號2〇5概略標示,其 係藉外側壁Π 5而與源極及汲極絕源。業界人士顯然易知須 於孔眼212'内邵有對應側壁來絕緣本體接觸與閘極廷伸件 2 i 0。次一步驟顯示於圖4 ’圖中服贴CVD氮化物(或氧化物 -氮化物)層130已經沉積於晶圓上,伸展入閘極伸展孔眼 -10- 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) --!—1.111____ _________ ;51-——__I I 11^- (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印- 驊4 325 4 5 A7 ___B7 五、發明說明() 212_之内壁及底邵。標示以編號…之區域指示於孔眼界定 過程暴露出的層102部分及多晶矽11〇之内面層13〇沉積前選 擇性進行再度氧化。介電層130於習知RIE方法直接蝕刻而 接近基材,及形成側壁132,如圖5所示d最後,沉積一多 晶矽層140,以適當攙雜劑攙雜,圖樣化及退火形成本體接 觸,如圖6所示。本體接觸之攙雜劑可具有本體之相同極性 (用於N-FET爲P型)。 閘極接觸及源極及汲極接觸可以任何方便方式形成,隨 仗任何方便之彳交端處理可用於完成電路。. 業界人士瞭解閘極延伸件丨10之長度並無特殊限制,原因 爲其可視需要儘量沿第一軸線伸展於源極及汲極之伸展區 ,原因爲閘極延伸件110占據之活性區部分不會促成流經電 晶體之電流流動。如此孔眼212,與閘極延伸件丨1〇之對正並 無特殊限制,原因爲延伸件U〇可製成夠寬而提供舒適的公 形成環繞孔眼212'之侧壁支承件205的閘極〗1 0延伸部用於 对内及外側壁提供支承,藉此使自行對正孔眼變成可行3 圖1 1顯示藉狗骨形光罩描述方法製造之本發明之替代狗 骨形具體例, 雖然已經描述本發明之較佳具體例,但業界人士瞭解現 在及未來可作出多種屬於隨附之申請專利範圍之改良與提 升。此等具體例須视爲對首述發明提供妥善保護。 -11 - 本·紙張&奴財関家辟(CNS)A4祕(21Q χ撕公复) -----------' * 裝.---------訂---------味- (請先閲讀背面之泫意事項再填寫本頁)
Claims (1)
- Αδ Β8 C8 D8 六、申請專利範圍P4 325 4 5 一種製造一絕緣外延矽 含下列步驟: 〈万法’該方法包 :电00 具肴-源極’及-藉-閘極隔開之及木 a /圣具有一本體接觸係由多晶 " 極,及且中一聂霞、、去w 6、』 層先成用於接觸閘 '中暴硌活性矽t成形場氧化物開口係形 y邵’其係.重#隔開源極與及極之閘極結構 =延伸區於成形場氧化物開口上,及-與該線性; =父而界定電晶體間極之區域,如此當間極之凹a 万檢視時,電晶體之第-閘極部件係血第_門扛 部件之第二鏡像閑極部件成鏡像,因此於頂部:: I ’問極凹凸部覆蓋於氧化物開口之影響顚倒,藉此於 弟τ万向之未對正將使電晶體裝置寬度變大,而於與第 一万向相對的第二方向未對正將使裝置寬度變小,而由 :效電晶體寬度去除覆蓋層公差:及其中於形成電晶體 裝直t過程中,本體接觸區係以高濃度攙雜’使用可適 用於間極之凹凸部部分製作—擴散光罩區,及於該擴2 光罩區下方製作與本體之本體接觸3 一種根據申請專利範園第丨项之方法而於基材上形成的 本體接觸型SOI電晶體,其中該閘極結構係由—對頂至 TR「T」字形元件形成,該等元件係舖設成可結合單一 本體與一區域,該區域係與各「τ」字形對正之線性延 伸區正交且概略彼此平行,因而結合及接觸電晶體裝置 之本體接觸區。 —種根據申請專利範園第1項之方法而於基材上形成的 -12 本紙铁尺度適用中國國家標準(CNS ) Λ4規格(2I0X 297公聲) (請先閲讀背面之注意事項再填寫本頁) '裝 <1T—* ί ί—.— 經濟部智惡財產局負工消貪合作社印製 A8 B8 C8 D8 六'申請專利範圍 本體接觸型SOI電晶體,其中 —電晶體裝置之源極及没極端子有—間極成形於其間, 及及閘極於其兩端具有閘&延伸部其係與閘極方向正交 ,及其結合與接觸一本體接觸於閘極結構各端3 2申叫專利範園㊉3項之於基材上形成的本體接 電晶體,其中 Ui 該間接結構具有狗骨頭形圖樣,及朝向裝置氧化物開 口邊之未對正邵份將於裝置之相對邊抵消。 晶==材上之本體接觸型絕緣外延砂⑽)電 -電晶體具有一源極,及一藉_閘極隔開之汲極,兮 —本體接觸係由多晶碎層形成用於接觸問極; 其中-暴露活性矽之成形場氧化物開口成形有 ,其係重疊隔開源極與汲極之閘極結構,及 延伸區於成形場氧化物開口 叫〃、]線性 二 、'、4線性延伸區正 父而界定電晶體間極之區域,如此當閘極之凹凸A :檢”’電晶體之第—閘極部件係與第1極 中一鏡像閘椏部件成鏡像,因此於頂部件之鏡像 , 極凹凸邵復蓋於氧化物開口之影響顚倒,藉此一間 Α 土#丄~r心.,.A。. 巧"弟一方 而 電 4:、纸張尺度適用申國國家標辛(CNS ) A4規格(21〇\297公董) I I · ί — 4—Jli --- i 1 - - - ί - - I i----- 一ΐτ {請先閣讀背面之注意事碩-填寫本頁〕 經濟部智慧財產局員工消費合作社印製 向之未對正將使電晶體装置寬度變大、 相對的第二方向未對正將使裝置宽万向 趙宽度去㈣蓋層領备十響〜有故電晶 如t請專利範園第上^^ „ , 令扯接觸型so. :_其中該繼構係由一,「Tj字形元 -13 »432545六、申請專利範圍 ABCD 8 . :牛形成’該等元件係舖設成可結合單-本體與—區域, 孩區域係與各「T」字形對正之線性延伸區正交且概略 彼此平行,因而結合及_韙之本體接觸區。 =第5項^置乾.占本體接觸型s〇i私印體裝置之源極及汲極端子有一閘極成形於其間, 及Μ閘椏於其兩端具有閘極延伸部其係與閘極方向正交 ,及其結合與接觸一本藤#於,¾結構各端。亡本體接觸型SOI 園第7項义該問極結構具有狗骨頭形圖樣,及朝向裝置氧化物開 口一邊之未對正部份將於裝置之相對邊抵消。 -----------* 艮------ ,v*t> (請先聞讀背面之注意事項再填寫本頁) 經濟部智^財產局員工消費合作社印製 -14. 本紙弦尺度適用中國國家標孪(CNS ) /\4々見格(210x 297公釐)
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US09/130,356 US6316808B1 (en) | 1998-08-07 | 1998-08-07 | T-Gate transistor with improved SOI body contact structure |
US09/130,357 US6387739B1 (en) | 1998-08-07 | 1998-08-07 | Method and improved SOI body contact structure for transistors |
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TW088101968A TW432545B (en) | 1998-08-07 | 1999-02-09 | Method and improved SOI body contact structure for transistors |
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US (1) | US6177708B1 (zh) |
JP (1) | JP2000058857A (zh) |
KR (1) | KR100342289B1 (zh) |
TW (1) | TW432545B (zh) |
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