TW408338B - Novel flash memory array and decoding architecture - Google Patents

Abstract

A flash memory circuit having a word line decoder with even and odd word line latches and a source line decoder with a source line latch is disclosed. The word line decoders and source line decoder provide the capability of erasing the memory cells of two adjacent word lines in a flash memory simultaneously and verifying the memory cells word line by word line. By erasing two adjacent rows simultaneously, the embodiments of this invention eliminates over-erasure and source disturbance problems associated with conventional flash memory circuits. The decoding architecture provides flexible erase size that can be from a pair to a large number of multiple pairs of word lines. By dividing the memory cells of a word line into a number of segments, the decoding circuit further provides the capability of selecting the memory cells of a word line segment for erasing.

Description

A7 B7 V. Description of the invention () The present invention is a continuation of the US patent application entitled "Novel Flash Memory Array And Decoding Architecture", which was filed on June 5, 1997. The inventor is the same as the inventor of this case . The invention relates to the design and circuit structure of a flash memory, in particular to the structure of a word line and source line decoder in the flash memory. In recent years, flash memory devices have been widely used in computer-related equipment and other electronic devices such as storage devices. Flash memory's non-volatile and on-chip programmability are important for storing data in many applications. For example, flash memory is commonly used in personal computer BIOS storage devices. In addition, the size characteristics of flash memory are very suitable for portable devices. So portable devices like mobile phones, digital cameras and video game platforms are equipped with flash memory to store programs and data. Different from the general random access memory (RAM) bit-based random reading, erasing, and programming, the consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs and the Intellectual Property Bureau printed the conventional EPROM-type flash memory. Byte blocks are byte-stylized and block-erased. Because the data in the memory block cannot be individually selected for erasing operation, the flash memory must erase the data of the entire memory unit block, that is, erase an entire block, and then one byte at a time. Set of stylized new data. Block erasure is not only inelastic, but also causes excessive erasure. Excessive erasure is caused by the different erasure rate of each memory unit. Because a large number of memory cells are erased together, the memory cells with a fast erasure rate will be over-erased, but the memory cells with a slow erasure rate will not be successfully erased. Excessive erasing of memory unit will conduct 1 paper size applicable to Chinese National Standard (CNS) A4 specification (210 X 297 mm) ⑽ 8 A7 __ B7 V. Description of the invention () Streaming and make bit line (BL) sensing Device malfunction. In order to be able to flexibly erase the memory unit, it is necessary to isolate the non-selected memory and avoid disturbing the stored data, and the US patent 5 Mg 551 • 7K-a negative voltage decoder, which can save the memory unless volatile A memory unit of the body or an entire block memory unit. Actually, it is necessary to have a word line erasure method with small g (multiple bytes) and flexible (random and multiple word lines) g without memory disturbance and excessive erasure. Flash memory is erased. The invention overcomes the shortcomings of the conventional flash memory. The main object of the present invention is to provide a circuit structure capable of erasing a memory cell with a small and flexible number of word lines. Another object of the present invention is to provide a method for erasing a plurality of sub-line pairs when asked, and to verify individual sub-lines at a time. Still another object of the present invention is to provide a memory circuit structure and a gp-dependent body circuit operation method for removing memory disturbance and excessive erasure, wherein excessive erasure often occurs in the conventional & closed discipline. A further object of the present invention is to provide a source line circuit having a segment source line, which enables the memory unit of a small paragraph on a word line to be erased without source disturbance. Still another object of the present invention is to provide a new bias condition to eliminate one or more paragraphs' in a word line to reduce gate disturbance to unselected paragraphs. The present invention also has another object to provide a new erasing operation procedure to reduce excessive erasure and disturbance 'to achieve accurate memory cell critical voltage control. The memory unit of the flash memory circuit of the present invention is divided into a plurality of memory bands. The memory unit of each §5 memory is divided into multiple columns and the paper size applies the Chinese National Standard (CNS) A4 specification (21 × X 297). (Please read the precautions on the back before filling this page) ———————— Order ------, —— Line. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 408338 A7 B7 i. Description of the invention () The source of the memory cells in the two adjacent columns is connected to Together, and received a total of. (Please read the precautions on the back before filling out this page) Corner source line. Each memory band of the present invention has its own word line decoder and source line decoder. The source line decoder has a source line latch that provides the necessary voltage levels for different memory operations. The address line to word line decoder and source line decoder will select the word line and source line to be used for memory operation. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. In the first embodiment, each word line decoder has odd and even number line latches. For erasing, the preferred operation mode of the present invention is to select adjacent two word lines, which share a common source line for erasing memory. When the adjacent two word line memory cell is erased, a negative voltage is applied to the two word line through the word line latch, and a voltage of, for example, 5V is passed through the source line latch to provide an appropriate bias condition for the erase. When the memory cell is erased and verified, the verified word line is applied with a verification voltage through the word line latch, and the other word line latches provide a sufficiently low voltage to turn off the excessively erased memory cells on the unverified word line. Therefore, when verifying a single word line, the erroneous read operation that often occurs can be eliminated. In addition, after each word line is verified, the appropriate voltage is passed through the relevant word line latch to stop its erasing action, thereby reducing the problem of excessive erasure. According to this embodiment, a plurality of memory bands can be erased at a time, wherein each memory band has two word lines, and the word lines share the same source line. The size can be changed from a single word line pair to a large number of multiple pairs of word lines. In the second embodiment of the present invention, there are also two latches related to the decoder. One of the latches is used to control whether the word line voltage of the selected memory column is provided by other latches or address lines. Apply the appropriate voltage to the address line and the paper size of the latch. The Chinese National Standard (CNS) A4 specification (210 X 297 mm) is applied. 408338 A7 B7 5. In the description of the invention (), multiple word line pairs of the memory tape can be simultaneously Perform 'erasure' and verify in ~ word line 1 word line manner. Even so, 'if all word lines of the memory tape are selected for erasing operation', its purpose is to be able to erase or not erase all its word lines at the same time, because the word lines provided in this embodiment The voltage address line is common to all memory cells. Therefore, the preferred mode for erasing is to erase multiple word line pairs which are smaller than the size of a memory band in the erasing operation, or to erase multiple memory bands at the same time. The other two embodiments provide functions similar to the second embodiment. The third embodiment uses another latch to control how the word line voltage is applied. By using the latch, the control circuit device of the word line decoder can be better protected in some cases. The fourth embodiment also uses another latch to reduce the address lines required for the word line decoder and the source line decoder by half. The flexibility and preferred operation modes of the two embodiments are the same as those of the second embodiment. The invention also provides a source line circuit, which can select a small paragraph memory cell in a column to perform a clear operation. The memory cells of a memory band are divided into several paragraphs, each paragraph contains several rows, and the sources of two adjacent columns of memory cells in a paragraph can be connected together to form a paragraph source line. The source lines of the paragraphs on the same word line are connected to the ~ common source line via a source paragraph control crystal, and the gate of each source paragraph control crystal is again connected to the ~ source paragraph control line. So the memory on the sub-line can be deleted one by one. • Although the preferred mode of erasing operation in the present invention is erasing and sharing 7 at the same time (please read the precautions on the back before filling this page) Free ---: I --- Order -------- -Consumption cooperation between employees of the Intellectual Property Bureau of the Ministry of Economic Affairs and the printed $ paper standard is applicable to China's national standard (CNS) A4 size (210 X 297 public love card 408338) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Invention Explanation () Memory cells of two adjacent word lines of the same source line 'but if only one single word line memory cell is deleted at a time' The present invention provides a post-programming method to store disturbed memory cell data. Two A mode for erasing the memory unit was revealed to eliminate multiple word lines and multiple paragraphs on a word line. Each operating mode uses different bias conditions. A hybrid method that has the advantages of both operating modes Is used to eliminate the problem of excessive erasure, which can save erasure time and reduce power consumption. Brief description of the figure: FIG. 1 is a memory band circuit according to a first embodiment of the present invention, including a memory band decoder, a word Line solution And a source line decoder, the word line decoder has even and odd number line latches, and the source line decoder has source line latches. Figure 2 is the word line of the first embodiment in Figure 1. Decoder circuit. Figure 3A shows the memory array circuit of the memory tape and the operating conditions of the decoder circuit when operating with different memories. Figure 3B summarizes the control signals of the first embodiment of the present invention under different memory operations. Figure 4 shows this. A memory band circuit according to a second embodiment of the invention includes a memory band decoder, a word line decoder, and a source line decoder. The word line decoder has a word line latch, and the source line decoder has a source. Figure 5A is the word line decoder circuit of the second embodiment of the present invention.-Figure 5B summarizes the paper control paper size of the second embodiment of the present invention under different memory operations. The Chinese standard (CNS) A4 specification is applicable. (210 X 297 mm) < Please read the notes on the back before filling this page)

408338 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. FIG. 6 is a memory tape circuit according to a third embodiment of the present invention. FIG. 7 is a memory tape circuit according to a fourth embodiment of the present invention. Figure 8 shows a latch circuit that provides three voltage levels. Figure 9 shows a latch circuit that provides two voltage levels. FIG. 10A is a memory array circuit with segmented source lines according to the present invention. Fig. 10B shows another memory array circuit with segmented source lines according to the present invention. FIG. 11 is a layout of the memory array circuit of FIG. 10A. FIG. 12A is another grid device replacing the grid device in FIG. FIG. 12B is another grid device replacing the grid device in FIG. 5. 'FIG. 12C is another grid device replacing the grid device in FIG. 5. FIG. 13 is a flowchart of a post-programming method for a memory cell that is disturbed by data when a memory cell of a word line pair is not simultaneously selected for erasing operation. Fig. 14 shows the erasing operation in the first mode of the present invention, in which a plurality of word line segments are selected for the erasing operation. Fig. 15 shows the erasing operation in the second mode of the present invention, in which a plurality of word line segments are selected for the erasing operation. FIG. 16 shows the erasing operation in the third mode of the present invention, in which the features of FIGS. 14 and 15 are combined to erase the memory cells of a plurality of word lines. Reference number in the drawing (please read the precautions on the back before filling this page). M ---- Order ------: --- line. R This paper size applies to China National Standard (CNS) A4 specifications < 210 297 mm) 408338 Α7 B7 V. Description of invention () 11 10 WL latch 20 WL latch 51 word line (WL) decoder 52 word line (WL) decoder 53 word line (WL) decoder ( (Please read the precautions on the back before filling in this page) 10 WL latch 12 WL latch 30 SL latch 'M -------- Order --------- Line 40 Memory Band Decoder 50 Word Line (WL) decoder 60 source line (SL) decoder 70 word control line (XS) latch 80 memory tape 100 first latch 200 second latch 400 output driver The preferred embodiment of the present invention will be described with reference to the drawings. The invention divides the flash memory into a plurality of memory bands. The Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs has printed the first embodiment of the present invention, wherein the flash memory circuit includes a word line (WL) decoder 50, a source line (SL) decoder 60 and a memory band δ〇. The memory tape 80 has an array of memory cells. Each memory tape has an odd-numbered WL latch 10, an even-numbered WL latch 20, and an SL latch 30. The memory band decoder 40 also displays the WL latch and SL latch controlled by the memory band decoder, which are used to select different memory bands in the flash memory. XT1 to XT4 and XT1 to XTB4 are address lines that work with the WL decoder 50 to pass or prevent the voltage of the SL latching to the source line. The XS word control line is connected to the ground voltage of this embodiment. Using the WL latch 10 or 20 and the SL latch 30, a negative voltage is applied to the word line, and a 5V voltage is applied to the source line. The decoder circuit shown in Figure 1 will eliminate the single paper size and apply the Chinese National Standard (CNS) A4 specification (210 X 297 mm). The consumer cooperation of the Intellectual Property Bureau of the Ministry of Economy will print 408338 A7 _____B7____ V. Description of the invention ( ) Memory unit on a word line. Generally, a single word line includes 128 or 256 bytes. However, in the flash memory design of the present invention, two adjacent word lines share the same source line as shown in FIG. For example, WL1 and WL2 share the source line SL1. If only WL1 is selected for eradication, the erasure perturbation will occur on its adjacent unselected word line WL2. The method that can overcome the disadvantages caused by the single selection of WL is to read the data before erasing and store the programmed data of the memory unit on the adjacent WL. When erasing verification, the neighboring WL is turned off. After the successful verification of the selected WL, the data of the memory cells on the adjacent WL disturbed by the source are restored. Compare read data with stored data. If the data does not match, a program operation is performed to program the stored data into the disturbed memory unit again. Using this method, the circuit shown in the first embodiment of the present invention can more flexibly eliminate any number of selected WLs, as long as the neighboring WLs that will be disturbed are first memorized and stored later. However, the preferred operation of the flash memory circuit in the first embodiment is to simultaneously delete two adjacent WLs having a common source line, so that the verification operation can be completed without disturbance. The odd-numbered and even-numbered WL latches 10 and 20 of the present invention will delete the memory cells on two adjacent WLs together. If the odd and even WL latches of the selected memory band apply a negative voltage to the selected WL pair, and the SL latch of the selected memory band applies a positive voltage to the selected SL, a pair of word lines can Deletion and verification are performed one after the other, as long as the appropriate address signal is added to the address line. All other WLs of the selected memory tape can be grounded through the word line control line XS if they are not selected by the address line for erasing. Therefore, please read (Please read the precautions on the back before filling this page)

This paper size is applicable to the national standard (CNS) A4 specification (210 X 297). 408338 A7 B7 V. Description of the invention () No memory unit is used to bias the erase operation except the selected memory unit. The problem of voltage-induced β-memory disturbance is eliminated. In addition, each memory band has its own odd and even WL latches and SL latches. The erase operation can operate independently without affecting other memory single bands. As a result, the number of erased word lines in the flash memory is very flexible, and can be as small as a WL pair or as large as a negative plural WL pairs. In addition, the memory bands selected for erasing can be distributed almost randomly at any location in the flash memory. To explain the detailed operation of the WL decoder 50, the decoder circuit is shown again in FIG. The p-n transistor pair and another n-transistor control whether each word line is connected to a WL latch or grounded to the word control line XS. It should be noted that the preferred erasure operation in this embodiment is that if multiple WL pairs are to be eradicated at a time, a plurality of memory bands will be selected, and only one WL pair is selected from each memory band Eliminate. With this, disturbance problems can be avoided. From the user's point of view, the logical address of the erasure memory WL may also be continuous. However, the memory band decoder of this embodiment can ensure that only one pair of WLs will be selected from each memory band. Although the circuit shown in FIG. 1 can erase more than one pair of WLs of the memory band at a time, the advantages of the present invention cannot be fully utilized unless only one pair of WLs of each memory band are simultaneously erased. The example of the division two pair WL is used to explain the operating conditions of the decoding circuit shown in FIG. Assuming that WL1 and WL2 of the first and second memory bands are selected for eradication, an appropriate voltage is applied to the address line to select WL1 and WL2, that is, 0V to XT1 '-8V to XT2 ~ XT4' _8V Give XBT1, 0V to XBT2 ~ XBT4. (Please read the precautions on the back before filling in this page.) -------- Order ----- II-- Line: The paper size printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs applies Chinese national standards ( CNS) A4 specifications < 2〗 0 X 297 public issue> 408338 A7 _B7__ 5. Description of the invention () The xs line of this embodiment is always grounded. In the selected two memory bands, do not add -8V to XD1 and XD2 for both the odd and even WL latches. In the word line decoder 50, there are a plurality of word grid devices, and each word grid device has three transistors to control the connection of the word lines. For example, WL1 is controlled by the transistors M1.a, Mlb and Mlc. Each word line can be connected to a WL or a word control line XS. Under this bias condition, Mia and M2a and Mlb and M2b will be turned on, and Mlc and M2c will be turned off to allow XD1 and XD2 to pass to WL1 and WL2. M3a ~ M8a and M3b ~ M8b will be turned off, and M3c ~ M8c will be turned on, let} (S pass to WL3 ~ WL8. So, WL1 and WL2 are added with -8V voltage to eliminate, and WL3 ~ EL8 are grounded to It will not be selected in the two memory bands. The source line decoder 60 includes a plurality of source gate devices, each of which has two transistors for controlling the source line to be connected to the SL latch 30 Or source control line SLS. The address lines ST1 ~ ST4 and STB1 ~ STB4 control the source gate device to connect a source line to the SL latch 30. Generally, ST1-ST4 has the same logic as XT1 ~ XT4, but can have different voltages STB1 ~ STB4 have the same logic as XTB1 ~ XTB4, but they can also have different voltages. For other memory bands that are not selected for erasure, the odd and even numbers of WL will add the ground voltage to XD1 and XD1 respectively. XD2. Because WL has been selected for eradication, the conditions of address lines XT1 ~ XT4 and XTB1-XTB4 have been determined. WL1 and WL2 are connected to the ground voltage of XD1 and XD2 respectively, and WL3 ~ WL8 will also pass XS Ground voltage. Therefore, WL will not be affected by erasure. After a preset erasure time After that, the threshold voltage of each erased memory cell on the WL will be sequentially verified to verify whether the erasure is complete. (Please read the precautions on the back before filling this page) Installation -------- Order -------- Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs The paper size is applicable to the Chinese National Standard (CNS) A4 (210 X 297 mm) 408338 A7 B7 V. Description of the invention () The verified WL is added with a positive voltage, such as 1.5V. For other deleted WLs, a negative low voltage, such as -3V, is added to turn off all memory cells. If any memory cells are over-erased, and the threshold voltage is It will also be turned off between 0V and -3V. The negative voltage that is turned off is related to the threshold voltage of the memory cell being over-erased. Prior to erasure verification, the voltage of the WL is reduced to detect its threshold voltage until The current without the memory cell is sensed. For the detailed process of determining the verification voltage, please refer to US Patent Application Ser. Nr. 08 / 823,571 filed by the patentee of this case on March 25, 1997. Intellectual Property Office, Ministry of Economic Affairs Printed by Employee Consumer Cooperatives (please read first Read the notes on the back and fill in this page again.) Add a small voltage or ground to the non-selected WL, such as 0V. Assuming that the WL1 of the first memory band is verified, the address line is added with an appropriate voltage to select WL1. That is, the power supply voltage Vdd is applied to XT1, -3V to XT2 ~ XT4, -3V to XTB1, and Vdd to XTB2-XTB4. It has been verified that in the first memory band where WL1 is located, the odd WL latch will verify the voltage, which is 1.5V , To XD1, and the even-numbered WL latch will add the shutdown voltage, -3V, to XD2. Under this bias condition, Mia and M2a and Mlb and M2b will be turned on, while Mlc and M2c will be turned off, and XD1 and XD2 are passed to WL1 and WL2, respectively. M3a ~ M8a and M3b ~ M8b are turned off, and M3c ~ M8c are turned on to pass the XS signal to WL3 ~ WL8. Therefore, WL1 is added with a verification voltage of 1.5V, WL2 is added with a shutdown voltage of -3V, and WL3 ~ WL8 are connected to the ground potential of the memory tape. In the second memory tape with an unverified division WL1, the odd and even WL latches are applied with negative turn-off voltages of -3V to XD1 and XD2, respectively. Because the address lines are shared, the bias conditions connect WL1 and WL2 to the off voltage of XD1 and XD2 · -3V, respectively, and WL3 to WL8 pass the XS ground voltage. For each paper size, the Chinese National Standard (CNS) A4 specification (210 X 297 mm) is applied. 408338 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7. 5. Description of the invention () No other memory tapes were selected for removal In other words, the WL latches add 0V voltages to XD1 and XD2, respectively. Therefore, WL1 and WL2 are both grounded to the 0V voltage of XD1 and XD2, and WL3-WL8 is grounded to the 0V voltage of XS. After verification, if the WL1 of the first memory band fails the erasure verification, it will be erased again under the same conditions as described above. If the erasure verification is passed, WL1 will apply a negative shutdown voltage to stop the erasure operation, and at the same time turn off the over-erased memory unit, if there is an excessive erasure unit. In this case, the operating conditions for the next erasure cycle will be similar to those described above, except that the odd-numbered WL latches of the first memory band will add a negative shutdown voltage to XD1. Based on the above description, the present invention provides a decoder circuit for simultaneously dividing a plurality of random WL pairs'. It should be noted that the erasing operation of each WL can be stopped independently. Since each erasure WL is controlled by an even WL latch or an odd WL latch, its corresponding WL latch can be reset to the erasure prohibition state to stop the erasure operation on the WL that has passed the erasure verification. You do not need to wait for the slowest erasure rate WL to be completely erased before the other WL stops clearing. The advantage of being able to stop the erasure operation independently is that the excessive erasure problem of conventional flash memory will be greatly reduced. Strict readers may notice that if a pair of WLs sharing the same SL are simultaneously erased 'unless the adjacent WLs are closed, their verification WLs will be subject to erroneous read operations unless the adjacent WLs are closed. Traditionally, the control gate of a non-verification WL is grounded. However, if the memory cell on the adjacent WL has been over-erased, its control gate cannot be closed to ground. Because the over-erased memory unit will conduct current and share the same source line with the verified WL. Therefore, the erasure verification will produce an error. The paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm). Li> (Please read the precautions on the back before filling this page). Loading ... !!! Order ------------ Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 408338 A7 _B7_ V. Invention Explanation () Result. As described in the above example, the negative shutdown voltage determined by US patent application 361: .heart.08 / 82: 3,571 can be added to the adjacent cymbals to avoid the problem of erroneous reading. It should be noted that when the verification is performed, the flash memory of the present invention needs three control gate voltages for the WL. In addition to the verification voltage and ground voltage used in the conventional flash memory, it also needs the previous The aforementioned negative shutdown voltage. US patent applications Ser.Nr.08 / 645,630 and Ser.Nr.08 / 676,066 filed by the patentees of the present invention disclose a method for providing at least three voltages from a WL latch. This technology and The present invention combines to provide three Different control gate voltages to WL. Figure 3A shows the memory array circuit of the memory tape and the operating conditions of the decoder circuit during different memory operations. It is assumed that WL1 and WL2 are both selected for erasing operation, that is, XD1, XD2 and SLX uses address lines to connect to WL1, WL2, and SL1. The erasure operation and erasure verification conditions have been described in Figure 2. For the erasure operation, XD1 and XD2 are -8V, and SLX It is 5V. For the clearance verification of WL1, XD1 is 1.5V, XD2 is the negative turn-off voltage -Vx, in the description it is assumed to be -3V, and SLX is 0V. For the excessive elimination of WL1, XD1 is 0.5 V, XD2 is the negative shutdown voltage -Vx, and SLX is 0V. For repair of WL1, XD1 is + 5V, XD2 is the negative shutdown voltage -Vx, and SLX is 0V. For the programming of WL1, XD1 is 8V, XD2 and SLX are all 0V. The following summarizes the WL voltage required in this embodiment for different operations. Three voltages are required for erasing, erasing verification, excessive erasing verification, and repair operations. For deleted WL, one will be used (Please read the precautions on the back before filling out this ) ', 敕 II Order · -------- Line. This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm). Intellectual Property Bureau, Ministry of Economic Affairs, Consumer Consumption Du Print 408338 A7 B7 5. Description of the invention () Operation voltage. For WL that has been erased or over-erased, verification or repair voltage will be used. For WL that has been erased but not in verification mode, a negative shutdown voltage is used Close the WL. WLs that are not selected for eradication are grounded. It should be noted that after the repair operation, all overly deleted WLs will be restored. It is no longer necessary to close the excessive erasing memory unit. Therefore, only two voltages are required for programming and reading. The operating voltage is applied to the WL that has been programmed or read, while the other WLs are grounded. Fig. 3B summarizes the control signals of the first embodiment of the present invention under different memory operations. Figure 4 shows a second embodiment of the present invention. In this embodiment, the flash memory billion-body circuit includes a memory band 80, a word line decoder 51, and a source line decoder 60. The memory band 80 has an array of memories. Each memory strip has a WL latch 11, an SL latch 30, and a word control line (XS) latch 70, which are related to the memory strip. The memory band decoder 40 selects different memory bands in the flash memory. The SL decoder 60, the SL latch 30, the memory tape 80, and the memory tape decoder 40 are the same as those of the first embodiment. Figure 4 uses the same reference numbers as Figure 1 to identify the circuit blocks. In the word line decoder 51, there are a plurality of word grid devices, each of which has three transistors to control the connection of the word lines. For example, WL1 is controlled by a word grid device with transistors Mia, Mlb and Mlc. Using the WL latch 11, the SL interrogator 30, and the XS latch 70, the WL decoding circuit 51 of FIG. 4 can connect each WL in the memory band to its address line XT (XT1 to XT4) or to the XS latch 70. If the number of WLs selected for erasure is smaller than the number of word lines of the memory tape, the WL latch 11 of the memory tape will send a negative voltage to XD, which XD allows memory ------------ -: Install --- (Please read the precautions on the back before filling this page) Order --------- The size of thread paper is applicable to China National Standard (CNS) A4 (210 x 297 mm) Economy Printed by the Ministry of Intellectual Property Bureau's Consumer Cooperatives 408538 A7 B7 V. Description of the Invention () Each WL in the band is connected, and the simple connection method is related to its corresponding address line XT. If the address line is a negative voltage, its corresponding pin will be connected to the XS latch 70 to provide a negative voltage for the division. If the address line is grounded, its corresponding WL must also be grounded. Because the decoder 51 is less flexible, if the number of WLs selected for erasing is greater than the number of word lines of the memory band, then this embodiment can only delete all WLs of one or more memory bands together. At the same time, the number of deleted word lines must be a multiple of the number of multiple word lines of the memory band. In other words, 'if all milk in the memory band is selected for eradication, then all WLs in other memory bands must be selected for eradication or not selected for eradication. Although the magnitude of the erasure is not as flexible as the first embodiment, it is possible to use the erasing operation twice to have a very flexible erasure size. As shown in Figure 4, adjacent two word lines share the same source line. It is difficult to avoid memory disturbances. As described in the first embodiment, 'Although any number of WLs smaller than the size of the memory band can be selected for erasure, it is preferable that two adjacent WLs are simultaneously deleted at the same time, so' the decoder of this embodiment The preferred operation mode has an erasing size that is smaller than the number of word lines of the memory band or a multiple of the number of word lines of the memory band. To explain the operation of the second embodiment, the WL decoding circuit 51 of the memory tape is shown in FIG. 5A again. Each memory tape has only one WL latch, which generates XD signals. The XD signal is sent to the common gate of the p-n transistor pair as shown in Figure 5A. Each address line XT is sent to the drain of a p-MOS transistor. The drains of the two n-MOS transistors are connected to the XS latch 70. Therefore, depending on the XD signal, XT or XS passes to a WL. This example shows that eight WLs are on a memory tape (please read the precautions on the back before filling this page). Loading-^-Order --------- The paper size of the paper is applicable to the Chinese National Standard (CNS ) A4 specification (210 X 297 mm) 408338 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 5. In the description of the invention (). In order to understand how the decoder operates, we first discuss selecting only the number of WLs which is smaller than the number of word lines of the memory band division. The voltage of XT1 ~ XT4 is -8V, XT5-XT8 is OV, XTB1 ~ XTB4 is IV, XTB5 ~ XTB8 is -8V, and WL1 ~ WL4 of the memory tape is selected for elimination. The WL latch and XS latch of the selected memory tape apply -8V to XD and XS, respectively. At this time, Mla ~ M4a will be closed with: ^ Mlb ~ M4b, and Mlc ~ M4c will be opened, allowing negative voltage -8V to pass from XS to WL1 ~ WL4. At the same time, M5b ~ M8b and M5c ~ M8c will be turned off and M5a ~ M8a will be turned on, allowing 0V voltage to pass from XT5 ~ XT8 to the unselected word line WL5-WL8. Because XT1 ~ XT and XT1 ~ XT8 are shared by the corresponding WL of each memory band, the bias conditions of XT1 ~ XT8 and XT1 ~ XTB8 have been determined by the memory band WL selected for erasure, such as Previously mentioned. The control of the memory tape that is not selected for erasing must be performed using the excessive XD and XS voltages in the memory tape. For memory tapes that are not selected for erasing, \ 0 is applied with a voltage of -8V and XS is applied with a voltage of 0V. Because the voltages of WL1 to WL4 pass through XS as described above, they are 0V. The voltage test passed from XT5 to XT8 and WL5 to WL8 is 0V. Therefore, all WLs were not selected for erasing operations. In order to stop the erasing operation of any word line on the selected WL, the corresponding χτ can be added to a negative shutdown voltage and passed to WL. For example, if only one WL1 passes the verification verification, the negative shutdown voltage that can turn off the memory cell on WL1 is added to XT1. The negative shutdown voltage is lower than a preset threshold voltage as in the aforementioned U.S. patent application Ser. Nr. 08 / 823,571. A good example of this negative turn-off voltage is -3V. XT1B is also applied with -8V voltage. Mlc is closed and this paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) ---------------. -------- Line · I < Please read the notes on the back before filling in this page) 408338 A7 __B7_ 5. Description of the invention () And the negative bias voltage will open Mia and pass to WL1. The other word lines WL2 ~ WL4 are not affected, and their erasing operations continue. After the elimination of WL1-WL4, each word line can be verified individually. When verifying the word line WL1, for example, a verification voltage of 1.5V is applied to XT1, a voltage of 3v is applied to XT2 to XT4, and a voltage of 0V is applied to XT5 to XT8. XTB1 is added with a voltage of -3V, XTB2 ~ XTB4 are added with a voltage of 0V, and XTB5 ~ XTB8 are added with a voltage of -3V. XD and XS are applied with -3V voltage from WL latch and XS latch, respectively. At this time, M2a ~ M4a and M2b ~ M4b are turned off, and M2c ~ M4c are turned on so as to pass from the -3V voltage of XS to the word line WL2-WL4 which has been erased but not verified. At the same time, M5b ~ M8b and M5c ~ M8c are turned off, and M5a ~ M8a are turned on so that the 0V voltage from XT5 ~ XT8 passes to the unselected word lines WL5 ~ WL8. During verification, Mlb and Mlc are turned off, and Mia is turned on to pass the 1.5V verification voltage from XT1 to the verified word line WL1. As described above, the second embodiment can erase several memory bands at the same time. All WLs for each selected memory tape must be erased or stopped together.淸 When dividing several memory bands, apply 0V to XT1 ~ XT8, and apply -8V or 0V to XTB1 ~ XTB8. For the memory tape selected for eradication, the corresponding WL latch is added with 0V to XD, and the corresponding XS is added with -8V to XS. At this time, M1a ~ M8a will be closed, and Mlb ~ M8b and Mlc ~ M8c will be opened. Therefore, a voltage of -8V is applied to WL1 to WL8, and the voltage is erased by XS. For memory bands that are not selected for eradication, the corresponding WL latches are -8V to XD, and the corresponding XSs are 0V to XS. As a result, Mla ~ M8a will turn on, while Mlb ~ M8b and Mlc ~ M8c will turn off. Therefore, WL1 ~ WL8 plus 0V voltage pass through XT1 ~ XT8 respectively. • Although each selected memory band WL must be deleted or stopped together (please read the precautions on the back before filling in this page) ^ •! ---- I subscribe * ----- 丨 ---- line economy Printed by the Ministry of Intellectual Property Bureau ’s Consumer Cooperatives This paper is printed to the Chinese National Standard (CNS) A4 (210 X 297 mm) 408338 A7 B7 Printed by the Intellectual Property Bureau ’s Consumer Cooperatives of the Ministry of Economic Affairs As other memory tapes continue to be erased, one memory tape may be stopped. When it is necessary to stop the selected memory tape, the XS latch applies the above-mentioned negative shutdown voltage of -3V to XS. The negative shutdown voltage of XS is passed to all WLs of the memory tape to close the memory unit, because Mla ~ M8a will be closed, and Mlb ~ M8b and Mlc ~ M8c will be opened. Each cleared WL must be verified individually. If WL1 of the memory tape is to be verified, XT1 is added with 1.5V verification voltage, and XT2 ~ XT8 are added with -3V negative shutdown voltage. XTB1 plus -3V negative turn-off voltage and XTB2 ~ XTB8 plus 0V. For memory tapes with verified WL1, XD and XS are applied with a negative -3V off voltage from the WL latch and XS latch, respectively. At this time, M2a ~ M8a and M2b ~ M8b will be turned off, and M2c ~ M8c will be turned on to pass the negative shutdown voltage from XS to -3V to. The word lines WL2 ~ WL8 which have been erased but not verified. At the same time, Mlb and Mlc will be turned off, and Mia will be turned on to pass the verification voltage from XT1 to 1.5V to WL1 for verification operation. For other erased but unverified memory tapes, the corresponding WL latches will apply the IV voltage to XD, and the corresponding XS latches will apply the negative shutdown voltage -3V to XS. At this time, Mla ~ M8a will be closed, and Mlb ~ M8b will be opened. Mlc will turn off and M2c ~ M8c will turn on. It can be understood that all the word lines WL1 ~ WL8 are added with a negative shutdown voltage of -3V from XS, so that the verification of the selected memory band WL1 will not be disturbed. For memory tapes that have not been selected for erasure, the corresponding WL latch applies IV voltage to XD, and the corresponding XS latch applies 0V voltage to XS. Result 'Mla ~ M8a is closed and Mlb ~ M8b is opened. Mlc is turned on and M2c ~ M8c are turned off. This circuit condition allows WL1 ~ WL8 to add 0V voltage from XS. Figure 5B summarizes the second implementation of the present invention under different memory operations. The paper size applies the national standard (CNS > A4 specification (210x297 cm)) --I I ------------- I — Order-- |! 1! Aunt {Please read the note on the back before filling this page) 408338 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. Fig. 6 shows a third embodiment of the present invention. In this embodiment, the flash memory circuit includes a WL decoder 52, an SL decoder 60, and a memory band 80. The memory band has an array of memory cells. Each memory strip has a first WL latch 11 ', a second WL latch 12, an SL latch 30, and an XS latch 70 associated with the memory strip. A memory band decoder 40 selects different memory bands in the flash memory. This embodiment is almost the same as the second embodiment described above except that two WL latches are used to send XD1 and XD2 signals to the gates of the transistors p-MOS and n-MOS in the WL decoder 52, respectively. This embodiment provides some protection for the P-n transistor, because the two gates of each p-n transistor pair are not connected together, while the two WL latches can provide different voltages. For example, XD2 plus IV voltage, turn on the n-MOS and let the XS signal pass to a WL, add 0V voltage to XD1 to turn off the p-MOS transistor to avoid the large voltage between its source and gate Bad and crashed. Fig. 7 shows a fourth embodiment of the present invention. In this embodiment, the flash memory circuit includes a WL decoder 53, a SL decoder 60, and a memory band 80. The memory band has an array of memory cells. Each memory band has an odd-numbered WL latch 10, an even-numbered WL latch 20, an SL latch 30, and an XS latch 70 associated with the memory band. A memory band decoder 40 selects different memory bands in the flash memory. This embodiment is almost the same as the second embodiment described above, except that even-numbered WL latches and odd-numbered WL latches are used to control the even-numbered and odd-numbered WLs of the memory band. As shown in FIG. 7 ', the WL decoder 53 of this embodiment requires only half the address lines. In other words, 'Each pair of WLs controlled by even WL latches and odd WL latches share one bit address line of XT1-XT4. With the 1st -----! .. Outfit.! ---- Order ---- I ---- Green (please read the notes on the back before filling this page) ^ paper @ applicable ^ Park National Standard (cNS) A4 specification (210 X 297 mm) Ministry of Economic Affairs Printed by the Intellectual Property Bureau employee consumer cooperative 408338 Α7 Β7 V. Description of the Invention (2) For comparison of the second embodiment, the additional WL latch 20 saves half of the address line of this embodiment, but it can also provide a considerable decoding function. It is to be noted that all embodiments of the present invention require three voltages to control the XD signal of the first embodiment or the XT signal of the second, third, and fourth embodiments. A previous US patent application 08 / 676,066 filed by the patentee of the present invention discloses a latch circuit capable of providing three different voltages. Another application 08 / 823,571 discloses a method of memory operation, using different voltages to avoid the problem of excessive erasure. The WL latch of the present invention uses a latch circuit and the method disclosed in the aforementioned patent application. An example of this latch circuit is shown in Figure 8. The circuit includes a first latch 100, a second latch 200, and an output driver 400. If the second latch 200 stores a high voltage level to the point B, the output driver 400 provides V3 to VOUT. Otherwise, the output driver will provide VI or V2 according to the high or low voltage level stored in the first latch 100 to point A. RES1, RES2, SI, S2 and S3 are control signals for setting and resetting the latch circuit and control in different operation modes. Some control lines of the present invention, such as XS, SLX and XD of the second embodiment, and XT of the first embodiment, need latches capable of providing two kinds of voltages. Figure 9 shows a two-voltage latch that can be used. Its operation is similar to that of Figure 8, except that only two voltages are available. According to the present invention, two adjacent WLs as shown in Figures 1, 4, 6, and 7 share a source line. In the memory array, each WL has an n-type transistor whose gate is coupled to the WL, and the source is connected to the common source line, and the drain is connected to Figures 1, 4, 6, and 7 A shared SLY line is shown. The η-type transistor is represented by M100 in FIG. 1. Total for the source line (please read the note on the back before filling this page). -------- Order -------- 丨 'This paper size applies to China National Standard (CNS) A4 Specifications (21 × X 297 mm) 408338 A7 B7 V. Description of the invention () Using SLY wire and transistor M100, when the stylized operation of the memory array is needed, a large amount of current parallel to several bits will be conducted out . Therefore, for circuit layout, a narrow metal with a word line width can be used for each source line. A reference, "New Decoding Scheme and Erase Sequence for 5V Only Sector Erasable Flash Memory» from 1992 Symposium on VLSI Circuit Digest of Technical Papers proposed by Mitsubishi, The wide wide metal line is used for the two source lines because the programming requires a large amount of current. Sharing the SLY line and the transistor M100 in the present invention makes it possible to give narrow metal lines to the common source line. The four currently mentioned The embodiments all provide an erasing operation with a number of elastic holes, from two WLs to a large number of WLs. The present invention further provides a new segmentation method, which divides a WL pair into a plurality of paragraphs, so that the memory unit of each paragraph on the WL pair Can be selected for division. As shown in FIG. 18, 'assuming that the memory cell of the memory array has a plurality of bit lines BL1, BL2'... 'BLN' BL (N + 1), ..., BL ( 2N), ..., etc. The word line pairs WL1 and WL2 are divided into a plurality of paragraphs with N bit lines. The bit lines with bit lines BL1 ′ BL2,..., BLN are taken as the first paragraph as examples. These Source of memory unit Connected together to form the source line SL11 of the paragraph and then connected to the source line SL1 via the n-MOS transistor M50. Similarly, the source of the memory cell pair of WL3 and WL4 on the first paragraph is connected together to form the source of the paragraph Line SL12 'is then connected to source line SL2 via another n-MOS transistor M60. The gate of transistor M50 and transistor M60 are connected to a source segment control line SLC1. This paper standard applies to the Chinese National Standard (CNS) A4 specification (21〇x 297mm) (Please read the precautions on the back before filling this page) -Install --------- Order ---- 1 ----% "Intellectual Property of the Ministry of Economic Affairs Printed by the Bureau ’s Consumer Cooperative 408338 Printed by the Consumer ’s Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention () The control line SLC1 determines whether the transistor M50 and transistor M60 are to be turned on, so as to connect the corresponding source line SL11 Or SL12 to SL1 or SL2. By controlling the voltage of SLC1, the present invention can further delete only the memory cell of one paragraph on each WL. In other words, the sub-WL is cleared by the circuit structure shown in Fig. 10A. Fig. 10B shows another circuit structure for providing the source line of the paragraph. In FIG. 10B, each segment source line of SL1I has two source segment control lines and two transistors M50a and M50b on the second side of the paragraph (but connected to the same control line voltage SLC1) to control SL11. Connection to SL1. In order to multiply and flexibly divide the number of word lines, a method using SLCN latches to each SLCN signal can be used. For the operation details of this method, please refer to U.S. Patent Application No. 08 / 624,322 filed by the patentee of the present invention. U.S. Patent No. 4,949,309 discloses a similar but different source line circuit that also has two transistors to control the circuit. In the layout in U.S. Patent No. 4,949,309, the first metal layer is for bit lines and vertical source lines, and the control transistor is formed of a second polycrystalline silicon (Poly2) layer. An example of the circuit structure of FIG. 10A is shown in FIG. This layout shows the four WLs of the second paragraph. SLC1 and SLC2 are the source paragraph control lines for the first and second paragraphs, respectively. In the layout of the flash memory, the first polysilicon (Polyl) layer is used to form the floating gate of the memory cell, and the second polysilicon (Poly2) layer is used for the word line. Due to its high density, there is no room for other transistors to be built on the Poly2 layer. The present invention proposes the circuit layout of Fig. 11, in which the source segment control lines SLC1 and SLC2, and the transistors M50 and M60 are constructed on Polyl. Because the paper size of the flash memory applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (please read the notice on the back before filling out this page) .k ----- 丨 丨 1 --------- line ... &Quot; Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 408338 A7 B7 V. Description of Invention () In the manufacturing technology of the body, the Polyl layer is used to form all memory units The suspended smell pole is isolated, so the Polyl layer without the Poly2 photomask layer will be cut off. This is done with a special SAE mask using self-aligned uranium engraving (SAE) technology. However, in the present invention, the transistors M50 and M60 and the control lines SLC1 and SLC2 must be protected without being etched away. Therefore, the traditional SAE layer can be changed to exclude the Polyl device and the Polyl gate from the normal Polyl line, which overlaps the first metal line of the bit line. No additional mask is required. In the above description, there are two kinds of gate devices for controlling the connection of a word line to a word line latch, an XS latch or an XT address line on a word line decoder. The transistors Mia, Mlb and Mlc of FIG. 2 form a gate device for the first embodiment, and the transistors Mia, Mlb and Mlc of FIG. 5 form another gate device for the second embodiment. It is to be noted that the gate device can be changed into many forms by a suitably designed circuit. For example, the circuit in Figure 12A can replace Mia, Mlb, and Mlc in Figure 2. Similarly, the circuit of Fig. 12B has the same function as the circuit formed by Mia, Mlb and Mlc in Fig. 5. The above examples are provided merely to facilitate the operation of the present invention. Those skilled in the art should be able to make modifications based on the above principles within the spirit of the present invention. Although in the above description, the fixed voltages used for the selected word line, such as XD = -8V, SLX = 5V, and other bias conditions have been explained for the operation of different embodiments, these biases Conditions should not be used to limit the scope of rights of the invention. For example, when the memory unit is deleted, in some circuit systems, the embodiment of FIG. 1 is best to use XD = 0V, ------------ ^ -------- order · ---- I --- line e .. (Please read the notes on the back before filling this page) This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 408338 A7 _____B7____ V. Description of the invention () SLX = 12V and ST1 ~ ST4 = 13V. In addition, the negative shutdown voltage mentioned many times in the above description is a variable voltage depending on the progress of the verification operation. This voltage is used to determine the optimal programming and erasing voltage. Using the disclosed embodiments, persons familiar with the field should be able to select different bias conditions based on the needs of different systems in actual applications to achieve optimal memory operation. As mentioned above, it can be seen that the flash memory decoding circuit provides appropriate bias conditions for different memory exercises to ensure that the flash memory can operate normally. In the flash memory industry, two traditional bias conditions are widely used in erasing operations. Generally, it can be classified into source elimination method and negative gate elimination method. These two methods, based on the Fowler-Nordheim tunneling mechanism, pull electrons from the floating gate, pass through a very thin oxide layer in the overlapping area between the floating gate and the source, and reach the source. To induce a tunneling current, a sufficiently high electric field must be applied between the source and gate. The source elimination method is to apply 12V to the source line, 0V to the word line, and leave the bit line unconnected. Use a very high source voltage to provide a sufficiently high electric field to complete the erase operation. The negative gate elimination method is to apply -8V to the word line, 5V to the source line, and leave the bit line unconnected. Because the gate has a negative voltage, this method requires a lower source voltage to provide sufficient electric field for the erasing operation. The disadvantage of the source elimination method is that a high source voltage increases the demand for higher breakdown voltages of the memory cell and its peripheral circuits. Therefore, the surrounding transistor needs to have a deeper junction and a thicker gate oxide layer. These needs will be (please read the notes on the back before filling this page). Packing --------------- Green, the Intellectual Property Bureau of the Ministry of Economy, Employees' Cooperatives printed this paper. The paper standards are applicable to Chinese national standards ( CNS) A4 specification (210 X 297 mm) 408338 A7 ____ B7 ______-_ V. Description of the invention () (Please read the precautions on the back before filling this page) Make the memory device smaller. In addition, higher source voltages increase the difficulty of current supply, and if the voltage is generated from a circuit on the chip, it becomes a serious problem. In general, the voltage generator must supply about 5MA to drive the erasure of a 64KB memory cell (10nA / cell). However, the supply current of the high-voltage generator will be greatly reduced if the output voltage is increased. Therefore, the source elimination method is more unsuitable and generally has only a single power supply Vcc and portable applications that need to generate high voltage on the chip. As a result, the negative gate elimination method is more commonly used because of its source voltage. The lower source voltage can easily be generated on the chip, or directly from the power supply Vcc, if a 5V Vcc is used. It must be noted that for the negative gate voltage, there is no problem with the supply current, because no DC current will flow through this gate. The negative gate erasing method can be used in the flash memory circuit of the present invention as described above to erase a WL, a WL pair, multiple WLs, or multiple WL pairs. However, if the erasing operation with a very flexible size is to be achieved, and only a part of a WL provided by the circuit of the present invention can be eliminated, the conventional negative gate erasing method is not suitable. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs As mentioned above, a WL or WL pair of the memory array of the present invention can be divided into multiple paragraphs as shown in Figures 10A and 10B: The memory array of each paragraph on the WL pair can be selectively erased. Each paragraph can be as small as a byte. When the bias condition of the negative gate erasing method is used to erase one or more paragraphs on a WL pair, the paragraph that is not selected for erasure will be subject to gate disturbance because the same negative gate Voltage is applied to both selected and unselected paragraphs. In a long section of this paper, the Chinese National Standard (CNS) A4 specification (21〇 × 297 mm) is applied. 40 ^ 338 A7 B7 V. Description of the invention () In the erasing time, the 'high negative gate voltage will remove the floating gate Of electronics. In order to minimize the gate disturbance, the conventional source elimination method can be used to eliminate one or more paragraphs of a WL or multiple WLs in the present invention. In the conventional source elimination method, the source of the selected section is applied with a positive voltage such as 12V, and the gate of the selected section is grounded. According to the circuit of the present invention as shown in Figs. 10A and 10B, only the paragraph line of the source of the selected paragraph is applied with a high voltage 'and the remaining unselected paragraph lines are suspended. Therefore, the source disturbance and gate disturbance are all removed. Because only some of the memory cells are cleared at this time, the required source current is much smaller than the high supply current of the 64KB memory cell, as described before. However, this bias condition still has the disadvantages of thicker oxide layers and deeper junctions as previously described. In order to overcome these problems, an appropriate method with a more suitable bias condition for the erasing operation can be used to fully obtain the advantages of the flexible erasing number of word lines of the decoding circuit disclosed above. A more suitable bias condition for eliminating the previous or more paragraphs of the selected WL pair is to apply an appropriate negative voltage such as -4V to the gate line, and an appropriate positive voltage such as 7V to the source line. The yuan line is suspended. Because the coupling ratio of the control gate (word line) to the floating gate is about 50%, by adding 2V to the source voltage of the conventional negative gate elimination method, the gate voltage can be reduced by about 4V. Reduce the gate disturbance but still maintain the same electric field to erase the memory cell data. Because of the memory read operation, a voltage of 5V is usually applied to a WL. Therefore, the gate disturbance caused by the appropriate negative voltage of -4V on the unselected section during the erasing operation is no longer the gate disturbance caused by the read operation. The determination can be ignored. . This paper size applies Chinese National Standard (CNS) A4 specification (210X297mm > (Please read the precautions on the back before filling this page) Printed by W Industry Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs

408338 A7 —_ B7 V. Description of the invention () Although the source voltage has increased, the source disturbance in the unselected paragraph has not increased. Because each paragraph has its own source of decoded paragraphs, as shown in SL11 or SL12 in Figure 18, the source of paragraphs of unselected paragraphs on the same WL pair are floating. In addition, a proper positive source voltage does not require a thicker oxide layer and a large supply current for conventional source elimination methods. The breakdown voltage of the widely used current device technology is about 8V. According to the preferred bias conditions of the present invention, the appropriate positive source line voltage is still below the breakdown voltage. Therefore, there is no need to increase the oxide layer thickness or junction depth for peripheral devices. In addition, with the boost circuit on the chip, it is easy to reach + 7V source line voltage, and if 5V Vcc is used, the boost circuit only needs one stage, or if 3V Vcc is used, only two stages are required. As a result, this new bias condition provides the advantages of negligible gate interference and a source voltage that is easily boosted compared to conventional bias conditions. It is also compatible with the manufacturing technology of the current device. It is also worth mentioning that the source line voltage and gate line voltage described above are just one example. Other suitable 値 can also be used. As mentioned before, the following are the bias conditions used in the flash memory of the present invention. The bias condition of the conventional negative gate erasing method is suitable and popular for erasing memory cells on one or more WL pairs because of the advantages of lower source voltage. The bias condition of the conventional source erasing method or the appropriate method of the present invention can be used to erase one or more paragraph memory cells on one WL or multiple WL pairs. That is, in the present invention, the most appropriate bias condition is based on the number of word lines to be subjected to the erasing operation (please read the note on the back W1 · item to complete this page) · 1:% order. Ministry of Economic Affairs The paper size printed by the Intellectual Property Bureau employee consumer cooperative is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) 408S38 A7 B7 V. Description of the invention () For regulatory use. As disclosed in this specification, although the preferred mode of operation of the flash memory circuit of the present invention is to eliminate a word line pair or word line paragraph pair that simultaneously shares the same source line, the circuit also allows for a single word line Erase the memory unit. It is even possible to eliminate a single memory cell or a smaller memory cell on a single word line. However, the memory cells of adjacent unselected word line segments are affected by stress and disturbed. To overcome the shortcomings of erasing a single selected word line, the method is to remember and store the stylized data of the memory cells that may be affected by the stress on the adjacent WL unselected word line before the erasing operation is performed. After the selected WL is successfully erased and verified, the stored data of the adjacent WL before being erased is read and compared with the read data of the memory cell on the disturbed WL after being erased. If the data is not within a safe read boundary, a post-programming operation is performed to store the data. Although this method can also be applied to conventional flash memory circuits, the advantage provided by the present invention is that only the memory cells on the disturbed word line will be stored. This is because in the present invention, the memory cells on adjacent word lines can be turned off to reduce the disturbance of data when a single word line is erased. Therefore, only the disturbed memory cells must be programmed. However, traditional flash memory circuits must erase and reprogram the entire memory cell block. FIG. 13 shows a flowchart of a post-programming method of a memory cell that is disturbed by data when the memory cells of a word line pair are not simultaneously selected for erasing operation according to the present invention. It can be summarized as follows: i .. Read the data of the memory unit that will be affected by the disturbance, and the stored paper size applies the Chinese National Standard (CNS) A4 specification (2 丨 0X297 mm) (Please read the note on the back first) Please fill in this page for more details.) Binding. Order-line _ 408338 Λ7 Α7 Β7 V. Description of the invention () The body information is compared. ii. Verify the data '0' with a critical voltage of about 4V under 3V operation. If it fails, the memory cell is post-programmed to restore its critical voltage back above 4V. If the allowed erasure time has elapsed before the reprogramming is successful, the flash memory device is considered defective. iii. Verify the data '1' whose critical voltage is around IV under 3V operation. If it fails, the memory cell is post-programmed to restore its critical voltage back to IV. If the allowed erasure time has passed before the programming is successful, the flash memory device is considered defective. iv. If both the data '0' and the data '1' are successfully restored to the memory unit, the post-programming operation is completed. The above program steps can be used to overcome the data disturbance caused by the word line pair with adjacent common source lines not being cleared at the same time when most of the word line erasing operations are performed. FIG. 14 is a flowchart of a method for erasing multiple digital lines in the present invention. This operation mode is called a multiple word line mode, and the steps are as follows: a. Select the word lines for the erasing operation. b. Read the memory data from the memory cells of adjacent unselected word lines that will be disturbed by data during the erase operation, that is, the word lines selected for the erase operation share the same source Line and not selecting each word line, and then storing the data in static random access memory (SRAM) on or off the chip. (Please read the precautions on the back before filling this page) • Binding. Order printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Employee Consumer Cooperatives. This paper is printed in accordance with Chinese National Standard (CNS) A4 (210X2.97 mm) 408338 A7 " _B7 ____ 5. Description of the invention () C. Add appropriate biasing conditions to the selected word line 'to erase one or more word lines and close other unselected word lines. D. Add the erasure pulse to the The selected word line. E. Verify the memory cells on the selected word line. If all the selected word lines pass the verification, proceed to step g. F. If the allowed erasure time has not passed 'reselect step e' The word line that failed the verification is used for the next erasing operation and proceed to step c. If the permitted erasure time has passed, the erasing operation is terminated and the flash memory device is considered defective G. Perform the post-stylized operation shown in Figure 13. Note that compared to conventional techniques, there are three new points in the erasing operation of the present invention. First, in step f, the selected word that passes the verification is selected. Line will be reset to Selected, and the erase pulse will not be applied to these next erased word lines. This will greatly reduce the number of over-erased cells. In contrast, conventional flash memory will continue to erase these word lines until all are selected The word lines have been successfully erased and verified. Second, if the memory cell must be continuously erased in step f, the operation returns to step c, and the bias condition is removed based on the foregoing verification step. The threshold voltage of the memory cell is used to update. In contrast, the conventional flash memory will return to step d 'and the bias condition will not be updated. Third, steps b and g are used to The memory cell data is post-programmed. In contrast, conventional technology does not use this programmatic operation. As described above, the flash memory circuit of the present invention can also divide the memory unit on the word line into a plurality of paragraphs. .. For single-print papers and dimensions, the Chinese National Standard (CNS) M specification (21〇χ 297 mm) applies (谙 Please read the precautions on the back before filling in this page) Order · Ministry of Economic Affairs Printed by the Intellectual Property Cooperative's Consumer Cooperatives 408338 A7 B7 V. Description of the Invention () For the memory unit of one or more paragraphs on the line, the operation is similar 'except that it is adjacent to the source line shared by the selected word line. Unselected word lines will be disturbed. Memory cells on selected word lines that are not selected will also be disturbed. These must be read and stored outside of temporary storage devices such as SRAM. These The memory unit must verify and store 'if it has been disturbed during the erasing operation. Figure 15 shows the erasing operation in the second mode of the present invention, in which a plurality of word line segments are selected for the erasing operation. The erasing operation The operation mode is called multiple paragraph mode. The summary is as follows: A. Select the word line paragraph for erasing operation. B. Read the memory data from the memory cells that will be disturbed by data during the erasing operation, including memory cells other than the selected word line paragraph on the same word line, and memory cells of adjacent unselected word lines. Store this data on or off-chip static random access memory (SRAM) ^ C. Add appropriate bias conditions to the selected word line segment to erase one or more word line segments and close Other unselected word line paragraphs and other unselected word lines. D. Add the erasure pulse to the selected word line segment. E. Verify the memory cells on the selected word line paragraph. If all selected word line paragraphs pass the verification, go to step G. F. If the permitted erasure time has not yet passed, select the word line paragraph that failed the verification in step E again, use it for the next clear operation, and go to step C. If the erasing time allowed is exceeded, then the erasing operation of this paper applies the Chinese National Standard (CNS) A4 specification (2 [〇X 297 mm] (please read the note on the back before filling out this purchase ) Order. 408338 A7 _B7_ 5. The invention description () will be terminated, and the flash memory device will be considered defective. G. Perform the post-programming operation shown in Figure 13. Similar to Figure 14, in After the verification operation of step F, each selected word line segment can be stopped in erasing. It should be noted that the source line of the paragraph is provided by an appropriate positive voltage and the negative line is provided by an appropriate negative voltage as shown previously. The bias condition of the gate must be used to erase the selected word line segment of step C in the erasing operation. The source line of the paragraph of the unselected word line segment must be suspended. As mentioned earlier, this bias condition will reduce the Gate perturbation of unselected word line paragraphs. The method of the present invention shown in Figs. 14 and 15 is designed to erase the memory cells of multiple word lines and word line segments respectively. The present invention further Provide a two-step operation. And the advantages of the two methods in FIG. 15 to further enhance the erasing operation of the disclosed flash memory circuit. In conventional flash memory circuits, when memory cells of multiple word lines are selected for erasure If some memory cells take a considerable amount of time to erase, all other selected units must be continuously erased until these slower erased memory cells are successfully erased. This will not only increase Excessively erasing the number of memory cells will waste time and power. The disadvantages and problems of excessive erasing have already been mentioned previously. In addition, according to the method of the present invention in FIG. 14, it can be independently based on a word line. Stop the erasing operation to avoid this problem. However, if the slower memory cells are distributed on many different word lines, this disadvantage cannot be overcome by stopping the erasing of another word line.-To overcome this problem, Figure 10 The flow chart of 6 shows one kind of elimination— __________ This paper size is applicable to China National Standard (CNS) A4 specification (2 丨 0X297 mm) (Please read the Please fill in this page for the note items) Customs · The consumer cooperation of the Intellectual Property Bureau of the Ministry of Economic Affairs Du printed 408338 _ A7 _ _B7_ V. Description of the invention () A new method of word lines. The elimination method in Figure 16 includes multiple word lines and Multiple paragraph modes. At the beginning, the selected word line was deleted by using multiple word line modes, in which all the multiple selected word lines were deleted together, and each word line that passed the verification was independently Stopped from erasing. After most of the selected word lines have been successfully erased and verified, the erasure operation switches to multiple paragraph modes. In multiple paragraph modes, there is still an unerased success memory The word line of the cell will be detected and erased in a WL followed by WL. For each word line that needs to be further erased, the erase pulse is added to the number of cells that contain the memory cells that have not been successfully erased. Paragraphs. When each paragraph passes the verification, it can be stopped independently in the erasure. After all the selected word lines have been successfully erased and verified, the next word line containing the memory cells that have not been erased successfully will be detected and erased in multiple paragraph modes. The erasing operation of such multiple paragraph modes will be repeated until all the memory cells on the selected word line are successfully erased and verified. Almost all steps performed by the method of FIG. 14 are repeated in FIG. 16 except for step f. In step f, if the allowable time limit has not been reached, the method of FIG. 16 determines whether the erasing operation should be switched to a plurality of paragraph modes. There are several different factors that can be used to decide whether or not to switch modes, such as the number of erase pulses applied, the number of failed memory cells, or the minimum threshold voltage of the erased memory cells. The following examples illustrate the case where multiple word line erasing modes are to be switched to multiple paragraph modes. Assume that there are multiple word line memory cells selected. _ .___ 36________ This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) (Please read the precautions on the back before filling this page) Order the intellectual property of the Ministry of Economic Affairs Printed by the Bureau ’s Consumer Cooperatives 408338 A7 B7 V. Description of the invention () Elimination, where five word lines represent a part of all selected word lines. A preset condition used to change the mode can be set when the number of all word lines that fail the erasure-verification is less than five. The total number of clear pulses added to the selected word line can also be used as an additional constraint. For example, if the number of erasure pulses has exceeded a preset number, such as 100, and the total number of word lines that fail to pass the erasure-verification is less than 5, erasure in multiple segment modes is started. The maximum threshold voltage of a memory cell can also be taken as another criterion. The switching point for switching from multiple word line modes to multiple paragraph modes is' when the maximum threshold voltage of a memory cell that fails the erasure-verification is higher than a preset voltage, such as 3V, and the word that fails the erasure-verification The total number of lines is less than 5. It must be noted that the above-mentioned number of word lines and voltages 値 are merely examples and should not be used to limit the scope of the present invention. If multiple word line modes have been determined to continue, the erasing operation returns to the method of FIG. If the erasing operation is switched to a plurality of paragraph modes, the word line paragraphs of each word line are identified based on the verification result. By the method shown in Fig. 15, the identified word line segments in each word line are selected for the erasing operation. By being able to switch to multiple paragraph mode, the word line paragraph without the slower memory cells will be less disturbed by the longer clearing time. Therefore, the problem of excessive elimination is eliminated, and the power consumption thereof is greatly reduced. In summary, when the invention of this case is known to have utility and novelty, and the invention has not been seen in any publications, it shall comply with the provisions of the Patent Law. The above is only one preferred embodiment of the present invention, and the scope of implementation of the present invention cannot be limited by it. That is, Fanfan applied according to the present invention (please read the precautions on the back before filling this page). Order the paper printed by the staff of the Intellectual Property Bureau of the Ministry of Economic Affairs. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) 408338 A7. B7 V. Description of the invention () The equivalent changes and modifications made to the scope of the patent shall be within the scope of the invention patent. (谙 Please read the notes on the back before filling in this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 8 3 This paper size is applicable to China National Standard (CNS) A4 (210X297 mm)

Claims (1)

y 7 4083B8 λ August ^ correction / history ^ C8 丨 丨 I ϋ〇6. Patent application scope1. One kind of elimination and verification of one or more word lines in a flash memory circuit (please read the precautions on the back first) (Fill in this page again) The method for operating the memory of the memory unit, which includes the following steps: A. Select the word line to be deleted; B. Identify if the selected word line in step A is applied with an appropriate The memory cell that will be disturbed during the bias condition; C. read the data of the memory cell identified in step B and store the data to a temporary storage device; D. the word selected for erasure Online memory unit, set the appropriate erasing bias condition, and set the appropriate non-erasing bias condition for other word online memory units that are not selected for erasure; Ε · Add a erasing pulse to The word line selected for erasure; F. Data verification of the word line memory cells' selected for erasure; G. If the memory cells of all word lines selected for erasure have passed the data of step F Verification, then enter Step I; Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. If the preset time limit has not been exceeded, then update the selection of the word line that excludes all memory cells that have been verified by the data in step F. 'And go back to step D. Otherwise, proceed to step P; I. read new data of a first group of memory cells identified in step B, and perform data " 1 "verification on the first group of memory cells, the first group of memory cells is The data “1” is stored in the temporary storage device; History ^ C8 丨 丨 I ϋ〇6. Patent application scope1. A type of memory unit that eliminates and verifies one or more word lines in a flash memory circuit (please read the precautions on the back before filling this page) A memory operation method, which includes the following steps: A. selecting a word line to be erased; and B. identifying that if an appropriate bias condition is applied to the selected word line in step A, Perturbed memory cells; C. Read the data of the memory cell identified in step B and store the data to a temporary storage device; D. Set the appropriate memory cell on the word line memory cell selected for erasure Remove the bias condition, and For other memory cells on the word lines that are not selected for erasing, set the appropriate non-erasing bias condition; E. Add a erasure pulse to the word lines that are selected for erasing; F. For the selected To delete the word line memory unit 'for data verification; G. If the memory unit of all word lines selected for erasure has passed the data verification of step F, proceed to step I; Employee Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Print Η. If the preset time limit has not been exceeded, then update the selection of the word line, the selected word line is 'excluded' from all memory cells verified by step F and return to step D. Otherwise proceed Step P; I. Read new data of a first group of memory cells identified in step B, and perform data " 1 "verification on the first group of memory cells, the first group of memory cells having data" 1 ”'Stored in this temporary storage device;. 39 _ _-— — "-____ This paper size is suitable for financial and family transfer (CNS) (21GX297 public money) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A 8 ll D8 6. Scope of patent application J. If the verification of the information of step I "Γ is successful, proceed to step L; otherwise, execute step K; KK. If the verification of the data of step I" quote fails, and the preset After the time limit has not been exceeded, the data "1" is programmed into the memory unit of the first group and returns to step L '; otherwise, step P is performed; L. Read a second group identified by step B New data of the memory unit, and perform data " 0 " verification on the second group of memory units, the second group of 100 million units has data "0" and is stored in the temporary storage device; Μ. If step L If the verification of the data "0 " is successful, proceed to step 0, otherwise proceed to step N. If the verification of the data of step L " 0" fails, and the preset time limit has not been exceeded, then the data " 0 "is programmed into the first group of memory units and returns to step L, otherwise step P is performed; 0. Successfully exits the memory operation; P. Exits the memory operation and claims the flash memory The circuit is defective Trapped. 2. As described in item 1 of the scope of the patent application, the memory operation method of removing and verifying the memory cell of one or more word lines in a flash memory circuit, wherein the steps in the procedure can be composed of the following steps Replaced by: .Η1. If a preset time limit has been exceeded, proceed to step P; (Please read the precautions on the back before filling this page) 408338 as? 88 D8 VI. Scope of patent application (please read the precautions on the back before filling this page) H2. If the requirements of a preset condition are not met, the words of all memory units that have passed the data verification of step F Lines are excluded to update the selection of the erased word lines, and return to step D; H3. Find the word lines of the memory cells that have not passed the data verification of step F, and perform a memory paragraph for each of the found word lines Deletion operation, and the memory paragraph deletion operation includes the following steps: a. Divide the memory unit on the word line into a plurality of paragraphs; b. Select the paragraph to be deleted;-c. Select the selected paragraph in step a When an appropriate biasing condition is added, the memory unit that is disturbed by the data is identified; d. Reading the data of the memory unit identified in step c and storing the data in a temporary storage device; e. Setting The appropriate erasing bias condition is used to erase the memory cells of the selected paragraph; and the appropriate non-erasing bias condition is set to the memory cells of the unselected paragraph and the unselected word line; f Apply a erasure pulse to the paragraph selected for erasure; printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs g. Verify the data of the memory unit of the passage selected for erasure; h. If selected All the memory units of the deleted paragraph have passed the data verification of step g, then go to step j; i. If the preset time limit has not been exceeded, all the memory unit paragraphs that have passed the data verification of step g Exclude to update the selection of the erasure paragraph and return to the step --------- u____ This paper size applies to China National Standard (CNS) A4 specification (210X297 mm) 408338 bismuth C8 D8 Step e of applying for a patent, otherwise proceed to step q; (Please read the precautions on the back before filling this page) j. For the first group of memory units identified in step c, read the new data, and A set of memory cells performs data "Γ 'verification, and the first set of memory cells has data stored in the temporary storage device 値 ΜΓ; k. If the verification of the data" Γ in step j is successful, it continues. Continue to step m, otherwise go to step q; l. If the verification of the data "1" of step j fails and the preset interval limit has not been exceeded, then the data " 1 " is programmed into the memory of the first group Unit, and return to step j, otherwise proceed to step q; _Π1, read new data of a second group of memory units identified in step C, and perform data verification on the second group of memory units, the first The two sets of memory units have the data "0 " stored in the temporary storage device. Η. If the verification of the data" 0 "of step m is successful, proceed to step P, otherwise proceed to step 0; Ministry of Economic Affairs wisdom Printed by the Consumer Cooperative of the Property Bureau 〇. If the verification of the data of step m "〇" fails, and the preset time limit has not been exceeded, then the data is programmed into the first group of memory units and returned Go to step m, otherwise proceed to step q; P. Exit the memory operation successfully; d. Exit the memory operation and claim that the flash memory circuit is defective. . ---- 43 _—_ This paper size applies to China National Standard (CNS) A4 (210X297 mm) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 408338 6. Scope of patent application 3. If the scope of patent application is the second item The method for erasing and verifying a memory operation of a memory cell of one or more word lines in a flash memory circuit, wherein the appropriate bias of the memory cell selected in step e for the erased paragraph is given. The pressure condition is a bias condition of a source erasure method, and the source of the memory cell of the unselected paragraph is suspended. 4. The method of deleting and verifying the memory operation of the memory cell of one or more word lines in a flash memory circuit as described in item 2 of the scope of patent application, wherein the method selected in step e for erasing The proper bias condition of the memory cells of the paragraph is a bias condition of an appropriate method, and the source of the memory cell of the unselected paragraph is suspended. 5. —A method for deleting and verifying a memory unit of a plurality of word line segments in a flash memory circuit, the method includes the following steps: a. Selecting a segment to be deleted; b. Step When a selected paragraph in a is added with an appropriate erasing bias condition, the memory unit that is disturbed by the data is identified; c. The data of the memory unit identified in step b is read and stored in a temporary storage In the device; d. Setting the appropriate erasing bias condition for erasing the memory cell of the selected paragraph and setting the appropriate non-erasing bias condition for the unselected paragraph and the unselected word line For memory unit; e. Apply a erasing pulse to the selected paragraph for erasure; f. Perform data verification on the memory unit selected for erasure; (Please read the precautions on the back before filling (This page) This paper uses the Chinese National Standards (CNS) A4 standard (210X297 mm) 408338 a | g8S___ 6. Application scope for patents g. If all the memory units selected for the deleted paragraph have been verified by the data, Then go to step i; h. If the preset time limit has not been exceeded, exclude the paragraphs of all the memory units that have passed the data verification to update the selection of deleted paragraphs and return to step d, otherwise enter Step P; i. Read a new set of data from a first set of memory cells identified in step b, and perform data " 1 "verification on the first set of memory cells, and the first set of memory cells has storage J. If the data "1" of step i is successfully verified, proceed to step 1; otherwise, proceed to step k; k. If the data of step i " 1 " If the verification fails and the preset interval limit has not been exceeded, the data is programmed to the memory unit of the first group after 1′Γ, and returns to step i; otherwise, step p is performed; 1. Read through step b Identify New data of a second set of memory units, and performing data " 〇 " verification on the second set of memory units, the second set of memory units having data stored in the temporary storage device; m · if If the verification of the data “〇” in step 1 is successful, proceed to step 0; otherwise, proceed to step η; η. If the verification of the data of step 1 " 〇 " fails, and the preset time limit has not been exceeded, The data " 〇 " is then programmed into the memory unit of the first group, and returns to step 1, otherwise proceed to step ------ 44 --------; _ this paper size Applicable to Chinese National Standard (CNS) Α4 specification (2 丨 〇 × 297mm) I »--1 (Please read the precautions on the back before filling out this page), 1T. Line, Ministry of Economic Affairs, Intellectual Property Bureau, Employee Consumption Cooperative, printed 4083¾ A8 B8 C8 D8 VI. Patent application step P; 〇. Successfully withdraw from the memory operation; P. Withdraw from the memory operation and claim that the flash memory circuit is defective. 6. If the scope of patent application is the fifth Delete and verify a flash note A memory operation method for a memory cell of a plurality of word line paragraphs in a circuit, wherein the appropriate bias condition for a memory cell of a paragraph selected in step d for erasing is a bias of a source erasing method The source of the memory cell of the unselected paragraph is suspended under the condition of being pressed. 7. Divide and verify the memory cell of a plurality of word line segments in a flash memory circuit as described in item 5 of the scope of the patent application. The method of operating a memory in which the appropriate bias condition for the memory unit selected in step d for erasing is a bias of an appropriate method, and the source of the memory unit of the unselected paragraph Is floating. (Please read the notes on the back before filling this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs ______, -I _____—— 1 --- Order ------- line} .---- ^ Γ !, The size of this paper is applicable to China's national ladle (CNS) A4 specification (210X297)