JPH07334991A - Semiconductor non-volatile memory device - Google Patents

Abstract

(57) [Abstract] [Purpose] To realize a semiconductor non-volatile memory device capable of reducing the drain disturb and suppressing an increase in the time required for mask fabrication. [Structure] When the number of word lines for writing "1" data in the write / read circuit 6 is less than half of the total number N of word lines, data is written with the phase of the write data being in the normal state. The fact that the data was written in the normal state is recorded in the auxiliary word memory unit 12, and when the number of word lines in which “1” data should be written is N / 2 or more, the phase of the write data is inverted to write the data, The fact that it was written in the phase inversion state is recorded in the auxiliary word memory unit 12,
At the time of data reading, after reading the phase information at the time of writing recorded in the auxiliary word memory unit 12, the memory cells of the normal memory unit 11 are read,
The read data is "1" based on the read phase information.
It is determined whether it is data or "0" data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile memory, for example, a semiconductor nonvolatile memory device such as a flash EEPROM.

[0002]

2. Description of the Related Art As a non-volatile memory, a UV erasable EP capable of erasing data by irradiating UV
For ROM or write operation, channel hot electrons (CHE) are injected into the floating gate,
An electrically rewritable NOR flash EEPROM is known in which an erasing operation is performed by extracting electrons from a floating gate to a source by FN (Fowler-Nordheim) tunneling.

FIG. 11 shows a NOR type flash EEPRO.
FIG. 6 is a circuit diagram showing bias conditions for a write operation in M. In FIG. 11, WL _n-1 , WL _n , and WL _{n + 1} are word lines, CSL is a common source line, and BL _m-1 , BL _m ,
BL _{m + 1} is a bit line, MT _{(n-1, m-1) to} MT _{(n + 1, m + 1 )}
Is a memory transistor, CG is a control gate, and F
G indicates each floating gate.

At the time of erase operation in this memory array, although not shown, a selected word line, for example, WL
_n is -10 V, unselected word lines WL _n-1 , WL
_{n + 1} is 0V, common source line CSL is 6V, bit line BL
_m−1 , BL _m , and BL _{m + 1} are set to the floating state, respectively, and the electrons in the floating gate are extracted. As a result, the threshold voltage V _TH of the memory cell in the erased state becomes about 1 to 2V.

At the time of write operation, as shown in FIG. 11, the selected word line, for example, WL _n is positive 12
V, the unselected word lines WL _n−1 and WL _{n + 1} are 0 V, the common source line CSL is at the ground level (0 V), the selected bit line BL _m is 7 V, and the unselected bit line BL _m−1 , BL
_{m + 1} is set to 0 V, respectively, and CHE (channel hot electrons) is injected into the floating gate FG of the selected memory transistor MT _{(n, m)} .
As a result, the selected memory transistor MT _{(n, m)}
Threshold voltage V _TH of 5 V or more.

[0006]

However, in the memory array described above, unselected memory cells MT _{(n-1, m)} , MT connected to the selected bit line BL _m.
There is a problem that the data of _{(n + 1, m)} is destroyed by the so-called drain disturb phenomenon.

The following two are known as the drain disturb phenomenon. The first drain disturb is
This is a drain disturb phenomenon that occurs in an unselected memory cell in which "1" data (threshold voltage V _TH > 5V) is stored. The second drain disturb is "0"
This is a drain disturb phenomenon that occurs in an unselected memory cell of data (threshold voltage V _TH ≈1 to 2 V). Below, about this drain disturb phenomenon,
The configuration of FIG. 11 will be specifically described as an example.

Now, it is assumed that the thresholds of data "1" and "0" are "high (>5V)" and "low (≈1-2V)", and the memory cell MT _{( Focus on m, n)} . At this time, memory cells MT _{(n-1, m)} , M other than the memory cells MT _{( m, n)} connected to the same bit line BL _m
Assuming that the stored data of T _{(n + 1, m)} are all "1", when writing to the memory cell MT _{(n-1, m)} or MT _{(n + 1, m)} , the memory cell MT _{(m , n)} floating electrons FG accumulated in the floating gate FG of the memory cell MT _{(m, n).}
Holes are injected into G. Therefore, the memory cell M
When the stored data of T _{(m, n)} is "1", the accumulated electrons are lost and the threshold voltage V _{TH is changed} to 5 V or more, but the non-selected memory cell is selected. MT
_The stored data is lost by writing data to _{(n-1, m)} or MT _{(n + 1, m)} .

When the stored data is "0", conversely, avalanche hot holes are injected and the threshold voltage V _TH is further lowered although it is as low as 1 to 2V. Then, the threshold value may become too low to become negative, and in this case, all the memory cells MT _{(m, n)} , MT _{(n-1, m)} , connected to this bit line BL _m , MT _{(n + 1
, m)} regardless of cell selection, a current flows through the bit line BL _m during a read operation, and correct read cannot be performed.

The above drain disturb phenomenon (voltage)
Is the maximum (N− when the number of word lines is N).
1) Continue to be applied once. That is, when the stored data of cells other than the selected memory cell connected to the same bit line are all “1”, the drain disturb voltage is applied (N−1) times.

In the read-only mask ROM, when the storage data is written in the manufacturing process, the threshold value of the storage cell is set to "high" or "low" corresponding to "1" or "0" of the storage data. ". For example, if the memory cell is an N-channel MOS transistor,
Data is written by selectively ion-implanting a P-type impurity, for example, boron into the cell "1" of the stored data. However, when the data are all "1", a mask for ion implantation of all cells is prepared. This work
Normally, a computer creates data so that the opening of the ion implantation mask corresponds to the position where predetermined “1” data is written, and the mask is created based on this data. The larger the amount, the longer the processing time.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a semiconductor non-volatile memory device capable of reducing drain disturb and suppressing a long time required for mask fabrication. Especially.

[0013]

In order to achieve the above object, a semiconductor nonvolatile memory device of the present invention comprises a plurality of word lines and bit lines, and the nonvolatile semiconductor memory elements are arranged in a matrix. Of the non-volatile storage array and auxiliary storage means for storing the polarity of the stored information for each bit line of the non-volatile storage array.

In the semiconductor non-volatile memory device of the present invention, the non-volatile memory array is divided into a plurality of sub-arrays divided in the direction in which the bit lines extend, each sub-array including a sub-bit line and the sub-bit line. The auxiliary storage means has a storage means for operatively connecting the sub-bit line and the bit line, and the auxiliary storage means has a storage means for storing the polarity of stored information for each sub-bit line of the sub-array.

Further, in the semiconductor nonvolatile memory device of the present invention, the semiconductor nonvolatile memory element is electrically rewritable, and the polarity of the memory information is reversed when the memory information is written in the semiconductor nonvolatile memory element. A binary information corresponding to whether or not to be written into the auxiliary storage means, and when the storage information of the semiconductor nonvolatile storage element is read out, the storage information is inverted according to the information of the auxiliary storage means.

Further, in the semiconductor nonvolatile memory device of the present invention, the semiconductor nonvolatile memory element can write the memory information by a mask pattern in a semiconductor manufacturing process, and when the memory information is written in the semiconductor nonvolatile memory element,
Binary information depending on whether to invert the polarity of the stored information is written in the auxiliary storage means, and when the stored information of the semiconductor nonvolatile storage element is read out, the stored information is stored according to the information of the auxiliary storage means. It has a circuit for inverting.

[0017]

According to the semiconductor nonvolatile memory device of the present invention, the polarity of the stored information of the nonvolatile memory array is stored in the auxiliary memory means for each bit line of the nonvolatile memory array. Also,
When the non-volatile storage array is divided into a plurality of sub-arrays divided in the direction in which the bit lines extend, the polarity of the stored information is stored in the storage means for each sub-bit line of the sub-array.

Further, according to the semiconductor non-volatile memory device of the present invention, when the semiconductor non-volatile memory element is electrically rewritable, or when the semiconductor non-volatile memory element writes memory information by a mask pattern in a semiconductor manufacturing process. When it is possible, when the storage information is written in the semiconductor nonvolatile storage element, the binary information according to whether or not the polarity of the storage information is written is written in the auxiliary storage means.
Then, when the stored information is read from the semiconductor nonvolatile storage element, the stored information is inverted according to the information in the auxiliary storage means.

[0019]

1 is a block diagram showing a first embodiment of a NOR flash EEPROM as a semiconductor nonvolatile memory device according to the present invention. In FIG. 1, 1 is a memory array section, 2 is a row decoder, 3 is a column decoder,
4 is a memory circuit, 5 is a counter circuit, 6 is a write / read circuit, WL _{1 to} WL _N are word lines, and BL _{1 to} BL
_M indicates a bit line and CWL indicates an auxiliary word line.

The memory array section 1 is composed of a normal memory section 11 in which normal data is written and read, and an auxiliary word memory section 12 in which a phase state at the time of writing data for each bit line is recorded. .

FIG. 2 is a diagram showing a specific configuration example of the memory array section 1. The memory array unit 1, as shown in FIG. 2, N of word lines WL ₁ to WL _N, and the M bit lines BL ₁ to BL _M to the normal memory array as a regular memory unit configured It is configured by adding one auxiliary word line CWL. In FIG. 2, a single circle indicates a memory cell in a normal word line, and a double circle indicates an auxiliary word memory for storing the phase state of each word line sector.

The row decoder 2 has row addresses X _{1 to} X _1.
A word line designated by _X is selected, a signal of a level according to the operation mode is applied to the word lines WL _{1 to} WL _N , and an auxiliary word line CWL designated by an address _{XX + 1.}
A signal having a level corresponding to the operation mode based on the control of the write / read circuit 6 is applied to. Column decoder 3
Outputs a signal for selecting the bit line designated by the column addresses Y ₁ to _{Y Y} to the write / read circuit 6.

The memory circuit 4 has, for example, N × M S
It has a configuration in which RAM or DRAM is arranged in a matrix of N rows and M columns, and M of the normal memory section 11 is used at the time of writing.
Book on the bit lines BL ₁ to BL _M input data D _IN inputted correspondingly and respectively held, a predetermined clock signal CL
Depending on K, the N (corresponding to the number of word lines) held data corresponding to each bit line is sequentially output to the counter 5.

The counter circuit 5 counts only the data "1" of the N pieces of "0" and "1" data output from the memory circuit 4. Then, for example, the MSB output is connected to the write / read circuit 6. The MSB of the counter circuit 5 becomes logic "1" because the number of memory cells (corresponding to the number of word lines) in which "1" data is written among the memory cells connected to one bit line is
For example, when the number of word lines N reaches 1/2, that is, N / 2. Then, this information is held in a register (not shown) of the write / read circuit 6 and is referred to during the write operation.

When the write / read circuit 6 receives the write command WR, if the information held in the register (not shown) indicates that the output data of the MSB of the counter circuit 5 is "0", Data is written in the same phase as a normal NOR flash EEPROM, that is, in the normal rotation state, and a control signal CTL indicating that is performed.
Is sent to a row decoder control system (not shown), and "1" data indicating that the data is recorded in the normal state is written in the auxiliary word memory cell provided corresponding to the selected bit line. On the other hand, when the information held in the above-mentioned register (not shown) indicates that the output data of the MSB of the counter circuit 5 is "1", the data is written in the reverse phase and the inverted state. , A "0" data indicating that the control signal CTL indicating that is sent to a row decoder control system (not shown) and the data is inverted and recorded in the auxiliary word memory cell provided corresponding to the selected bit line. Write. When receiving the read command RD, the control signal CTL is output to a row decoder control system (not shown) to perform a read operation on the auxiliary memory cells of the auxiliary word memory unit 12 and to confirm the phase state of the write data. A read operation is performed on the designated memory cell of the normal memory section 11, and data “1” / “0” is determined based on the read phase information.

The operation principle of the write / read circuit 6 at the time of writing and reading data will be described in detail below with reference to FIGS.

In this embodiment, the concept of data phase is introduced to the memory cell for each bit line,
For example, as shown in FIG. 3, the write / read circuit 6 determines the phase for each bit line and writes data.

That is, when the phase is the normal rotation, it is in the same phase as the normal NOR flash EEPROM, and when the threshold voltage V _TH of the memory cell is 5 V or more and it is in the OFF state, the data "1", the threshold value. The data is "0" when the value voltage V _TH is 1 to 2 V and in the ON state. On the other hand, when the phase is inverted, a normal NOR flash EEPROM is used.
And the threshold voltage V _TH of the memory cell is 1 to 2
Data "1" when V is ON, threshold voltage V _TH
Is "0" when the voltage is 5 V or more and is in the off state. The phase difference of the memory cell data for each bit line is normal when the threshold voltage V _TH of the memory cell transistor in the auxiliary bit memory unit 12 is 5 V or more and is in the off state. Threshold voltage V _TH is 1 to
It is inverted when it is in the ON state at 2V.

When writing data, the drain
Set each bit so that the number of indisturbs becomes smaller.
Select the phase condition for each line and perform the write operation.
Yes. This is because the number of all word lines is N as in this embodiment.
Then, the threshold voltage V _THIs off at 5V or higher
The number of memory cells that can be used is half of the total, that is, N / 2 or less
The phase of each bit line should be determined so that
Becomes In other words, when writing data,
Floating gate by Nel Hot Electron
Reduce the number of memory cells that inject electrons into less than half of the total
do it. Therefore, the phase inversion of each bit line
Is the same phase as the normal NOR flash EEPROM.
Threshold voltage V_THIs "5" when 5V or more
Let P be the number of memory cells and N be the number of all word lines,
It is set with the relationship of. Phase inversion with P ≧ N / 2 Phase normal rotation with P <N / 2

The voltage applied to the word line SWL and the bit line SBL selected by the row decoder 2 and the write / read circuit 6 in the data write operation at this time is set as shown in FIG. That is, the selection gate line SWL is 12 regardless of the normal or inverted state.
Set to V. Then, at the time of writing in the normal rotation state, when writing "1" data, the selected bit line SBL
Is set to 7V, and when writing "0" data, the selected bit line BL is set to 0V. On the other hand, at the time of writing in the inverted state, the selected bit line BL is set to 0V when writing “1” data, and the selected bit line BL is set to 7V when writing “0” data.

By performing the write operation as described above, the number of memory cells for injecting electrons into the floating gate by CHE becomes half or less of the whole even in the worst case. That is, the number of drain disturbs at the time of writing data in the worst case can be reduced to half, and the normal NO
The maximum load is halved as compared with the R-type flash EEPROM.

In the data read operation, as described above, before the read operation for the memory cell,
After performing the read operation on the auxiliary memory cell and confirming the phase state, the normal read operation is performed as shown in FIG. 5, and the read data “1” from the memory cell is performed.
/ "0" is determined. That is, when the threshold voltage V _TH of the auxiliary memory cell is 5 V or more and no current flows in the bit line BL, it is determined to be in the normal rotation state. Then, in the subsequent read operation, when the threshold voltage V _TH of the read cell is 5 V or more and no current flows in the bit line connected to the read cell, the read data is determined to be “1”. Threshold voltage V of auxiliary memory cell
_In the read operation after _TH is 5 V or more and no current flows in the bit line BL and it is determined that the bit line BL is in the normal rotation state, the read cell is connected with the threshold voltage V _TH of 1 to 2 V. When the current flows through the bit line, the read data is determined to be "0". Further, when the threshold voltage V _TH of the auxiliary memory cell is 1 to 2 V and a current flows through the bit line BL, it is determined to be in the inverted state. Then, in the subsequent read operation, the threshold voltage V of the read cell is
_{When TH} is 5 V or more and no current flows through the bit line to which the read cell is connected, the read data is determined to be “0”. The threshold voltage V _TH of the auxiliary memory cell is 1 to
A current flows through the bit line BL at 2V, and in the read operation after it is determined that the read cell is in the inverted state, the threshold voltage V _TH of the read cell is 1 to 2V, and the current is supplied to the bit line to which the read cell is connected. When the data flow, the read data is determined to be "1".

Next, the operation of the above configuration will be described. At the time of writing, a write command WR is input to the write / read circuit 6, and M pieces of data D _IN are sequentially input to and held in the memory circuit 4. The clock signal CLK is input to the memory circuit 4, and the held data corresponding to each bit line is sequentially output to the counter circuit 5 in response to the input of the clock signal CLK. The counter circuit 5 counts the number of “1” data in the output of the memory circuit 4. As a result, the number of “1” data is 1 of the total number N of word lines.
When it is less than / 2, the MSB does not become a logical "1",
The logic “0” is input to the write / read circuit 6.
This data is held in a register (not shown).

In this case, the write / read circuit 6 determines that the write operation is in the normal state, and the normal NO operation is performed.
Predetermined data held in the memory circuit 4 is written in the same phase as in the R type, and "1" data indicating normal rotation is written in the auxiliary word memory cell. At this time, the word line WL and the auxiliary word line CWL selected by the row decoder 2 are set to 12V, and when writing "1" data by the write / read circuit 6, a predetermined bit line BL ₁ (to BL _M ) Is 7
Is set to V, also "0" predetermined bit line BL ₁ is to write data (to BL _M) is set to 0V.

The threshold voltage V _TH of the memory cell written with “1” data is held at a value of 5 V or more, and the threshold voltage V _TH of the memory cell written with “0” data is 1.
It is held at a value of ~ 2V. Similarly, the threshold voltage V _TH of the auxiliary word memory cell is held at a value of 5 V or higher.

On the other hand, as a result of counting by the counter circuit 5, when the number of "1" data is 1/2 or more of the total number N of word lines, the MSB becomes a logic "1" and is input to the write / read circuit 6. When the information is held in the register (not shown), it is determined that the write operation is in the inverted state, and the memory circuit 4 is in the opposite phase to the normal NOR type.
The predetermined data held in the memory is written, and at the same time, "0" data indicating inversion is written in the auxiliary word memory cell. At this time, the word line WL and the auxiliary word line CWL selected by the row decoder 2
Is set to 12 V and the write / read circuit 6 writes "1" data, a predetermined bit line BL
₁ (to BL _M) is set to 0V, also "0" of a given case of writing data bit lines BL _{1 (~BL M)} is 7
Set to V.

In this case, the data in which the "1" data is written is
Molycell threshold voltage V_THIs held at a value of 1-2V
And the threshold value of the memory cell in which "0" data is written
Voltage V _THIs held at a value of 5 V or higher. Also, the auxiliary work
Memory cell threshold voltage V_THHolds at a value of 1-2V
To be done.

At the time of reading, when the read command RD is input to the write / read circuit 6, the normal memory section 1
Before the read operation for the first memory cell, the read operation for the auxiliary memory cell of the auxiliary word memory unit 12 is performed, and after confirming the phase state, the normal read operation is performed, and the memory cell is read based on the read phase information. The determination of "1" / "0" of the read data from is performed. When no current flows in the bit line BL connected to the auxiliary memory cell, it is determined that the data has been written in the normal state, and data determination is performed. When sufficient current flows in the bit line BL, inversion occurs. Depending on the state, it is judged that the data has been written, and the data is judged.

Specifically, when it is determined that the data has been written in the normal state, the read data is determined to be "1" if no current flows through the bit line to which the read cell is connected, and the bit line is determined. If a sufficient amount of current flows, the read data is determined to be "0". On the other hand, when it is determined that the data has been written due to the inverted state, the read data is determined to be “1” if a sufficient current flows through the bit line to which the read cell is connected, and the current flows through the bit line. If it does not flow, the read data is determined to be "0".

As described above, according to this embodiment,
At the time of data writing, when the number of word lines for writing "1" data in the write / read circuit 6 is less than half of the total number N of word lines, the phase of the write data is kept in the normal state. Write data,
In addition, the fact that writing is performed in the normal rotation state is recorded in the auxiliary word memory unit 12 as a recording unit, and when the number of word lines for writing "1" data is N / 2 or more, the phase of the write data is set. The data is written by reversing the data, the fact that the writing is performed in the phase inversion state is recorded in the auxiliary word memory unit 12, and when the data is read,
First, after reading the phase information at the time of writing to this memory cell recorded in the auxiliary word memory unit 12,
Since the memory cell of the normal memory unit 11 is read and whether the read data is "1" data or "0" data is determined based on the read phase information, the drain disturb at the time of writing data is performed. The number of times can be greatly reduced to less than half, the drain disturb resistance can be greatly improved, and data destruction can be prevented.

FIG. 6 is a block diagram showing a main part of a second embodiment of a NOR flash EEPROM as a semiconductor nonvolatile memory device according to the present invention. The present embodiment is different from the above-described first embodiment in that the normal memory section of the memory array section 1 has one or a plurality of word lines as one group n.
Regular memory arrays 11-1 to 11-1 each including a group of word lines
1-n and each word line group 11-1 to 11-
corresponding to n in the provision of the auxiliary memory array 12a having n number of auxiliary word line CWL ₁ ~CWLn.

In such a configuration, the normal memory arrays 11-1 to 11-n are connected to the bit lines BL _{1 to} BL _M by the block selection gates 11-11 to 11-n1 provided corresponding to the normal memory arrays 11-1 to 11-n. Operatively connected. In addition, the normal memory array 11-n and the column decoder 3a,
A first column select gate 7-1 and a second column select gate 7-1 are provided between the column decoder 3a and the auxiliary memory array 12a, respectively.
Column select gate 7-2 is provided for the normal memory array 11-n, the column decoder 3a, and the column decoder 3a.
And the auxiliary memory array 12a are operatively connected.

FIG. 7 is a circuit diagram showing a configuration example of these column selection gates. This select gate is for each bit line B
L N-channel MOS transistor NT ₁ ~ to _{1 ~BL M}
It is configured to NT _M insertion connection to the gate of each N-channel MOS transistor NT ₁ ~NT _M control signals S ₁ to S
Each is connected to the _M input line.

In this configuration, each regular memory array 1
1-1~11-n positive for a predetermined supplementary memory cells connected to each corresponding auxiliary word line CWL ₁ ~CWL _n auxiliary memory array described above in (word line group) per 11-1 to 11-n The writing of the phase information of "0" or "1" indicating the inversion and the inversion is performed.

According to this embodiment, there is an advantage that the drain disturb can be reduced efficiently and accurately. In this embodiment, the regular memory arrays 11-1 to 11-n are used.
Although a configuration example in which the corresponding n auxiliary word lines CWL _{1 to} CWLn are collectively provided in the auxiliary memory array 12a has been described, the present invention is not limited to this, and each normal memory array 11-1 to 11-11, for example. Various modes are possible, such as providing the auxiliary word lines CWL _{1 to} CWLn adjacent to each other for each −n.

In each of the above embodiments, the NOR
Type flash EEPROM was explained as an example, but a normal D
It goes without saying that the present invention can be applied to an INOR type flash EEPROM, a NAND type flash EEPROM, and the like.

FIG. 8 shows a DINOR type flash EEPR.
9 is a circuit diagram showing a configuration example of the normal memory arrays 11-1 and 11-2 of FIG. 6 when the OM is applied to the present invention, and FIG.
FIG. 3 is a circuit diagram showing a configuration example of an auxiliary memory array in that case. In the figure, MT is a memory transistor, and GT is a gate transistor. In this example, the word line is divided into four lines, and two sub bit lines SBL ₁₁
And SBL ₁₂ , SBL ₂₁ and SBL ₂₂ are made to correspond to _one bit line BL ₁ and BL ₂ , respectively, so that the number of bit lines is reduced. With such a configuration, the defect density of the pattern can be reduced and the parasitic capacitance can be reduced.

FIG. 10 shows a NAND flash E
FIG. 7 is a circuit diagram showing a configuration example of the normal memory arrays 11-1 and 11-2 in FIG. 6 when the EPROM is applied to the present invention. The difference from the memory cell array of the DINOR type flash EEPROM is that there is no sub-bit line and the gates are provided on the opposite sides of the block select gates 11-11 and 11-21 of the memory array to the input lines of the select gate signals SG ₁ and SG _2. The gates of the connected N-channel MOS transistors are provided with GT ₁ and GT ₂ .

The above DINOR type flash EPROM
Also, when the NAND flash EEPROM is used, the same effect as that of the NOR flash EEPROM described above can be obtained.

In the above-described first and second embodiments, the case where the electrically rewritable semiconductor nonvolatile memory element is applied to the present invention has been described as an example. However, for example, a mask pattern is used in the semiconductor manufacturing process. It is also possible to apply a mask programmable ROM that writes stored information. In this case, if the number of cells stored as data “1” is larger than the number of cells stored as data “0” among the memory cells connected to the same bit line, the same bit is stored. For cells connected to the line, reverse the polarity of the data to create mask data,
At the time of reading, the read data is inverted and output. As a result, the amount of generated data can be reduced to a maximum of half as compared with the case where no measures are taken, and the processing time required for mask creation can be reduced. This processing time is not proportional to the amount of data, but considering that the generated data is converted to raster scan data for electron beam writing, the amount of data increases exponentially. The effect of reduction is greater than the amount of reduction.

[0051]

As described above, according to the present invention,
The number of drain disturbs at the time of data writing can be significantly reduced to less than half, the drain disturb resistance can be greatly improved, and data destruction can be prevented.
When applied to mask programmable ROM etc.,
The amount of generated data can be reduced to a maximum of half, and the processing time required for mask creation can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a semiconductor nonvolatile memory device according to the present invention.

FIG. 2 is a diagram showing a configuration example of a memory array section of FIG.

FIG. 3 is a diagram for explaining threshold voltages of a memory cell and an auxiliary memory cell at the time of phase normal rotation and reverse writing of data in the circuit of FIG.

FIG. 4 is a diagram showing a set voltage when writing data in the circuit of FIG. 1.

5 is a diagram for explaining a data determination operation during a read operation of the circuit of FIG.

FIG. 6 is a block diagram showing a main part of a second embodiment of the semiconductor nonvolatile memory device according to the present invention.

7 is a circuit diagram showing a specific configuration example of the column selection gate shown in FIG.

8 is a circuit diagram showing a configuration example of the normal memory array of FIG. 6 when the DINOR type flash EEPROM is applied to the present invention.

9 is a circuit diagram showing a configuration example of an auxiliary memory array in the case of the circuit of FIG.

10 is a circuit diagram showing a configuration example of the normal memory array of FIG. 6 when a NAND flash EEPROM is applied to the present invention.

FIG. 11 is a circuit diagram showing bias conditions during a write operation of a general NOR flash EEPROM.

[Explanation of symbols]

1 ... Memory array section 11 ... Regular memory section 11-1 to 11-n ... Regular memory array 12 ... Auxiliary memory section 12a ... Auxiliary memory array 2 ... Row decoder 3 ... Column decoder 4 ... Memory circuit 5 ... Counter circuit 6 ... Write / read circuit 7-1, 7-2 ... the column selection gate WL ₁ to WL _N ... word lines BL ₁ to BL _M ... bit lines CWL ₁ ~CWLn ... auxiliary word line

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Claims (4)

[Claims] 1. A non-volatile memory array comprising a plurality of word lines and bit lines, in which semiconductor non-volatile memory elements are arranged in a matrix, and a polarity of memory information is stored for each bit line of the non-volatile memory array. Non-volatile memory device having auxiliary storage means for performing. 2. The non-volatile storage array is divided into a plurality of sub-arrays divided in the direction in which the bit lines extend, each sub-array operating a sub-bit line and the sub-bit line and the bit line. 2. The semiconductor non-volatile memory device according to claim 1, further comprising switching means for electrically connecting the auxiliary storage means, and said auxiliary storage means has storage means for storing a polarity of stored information for each sub-bit line of the sub-array. 3. The semiconductor non-volatile memory element is electrically rewritable, and when the memory information is written in the semiconductor non-volatile memory element, the binary depending on whether to invert the polarity of the memory information or not. 3. The semiconductor non-volatile according to claim 1 or 2, further comprising a circuit that writes information in the auxiliary storage means and inverts the stored information in accordance with the information in the auxiliary storage means when the storage information in the semiconductor non-volatile storage element is read out. Sex memory device. 4. The semiconductor non-volatile memory element can write memory information by a mask pattern in a semiconductor manufacturing process, and when the memory information is written in the semiconductor non-volatile memory element, whether the polarity of the memory information is inverted or not. 2. A circuit having a circuit for writing binary information according to whether or not the auxiliary information is stored in the auxiliary storage means, and inverting the stored information according to the information in the auxiliary storage means when reading the stored information in the semiconductor nonvolatile storage element. The semiconductor nonvolatile memory device according to claim 2.