經濟部中央標準局員工消費合作社印製 407233 __ 五、發明説明（1 ) 本發明係關於個人電腦、工作站等之資訊處理裝置， 特別是關於複數之內部匯流排經由匯流排轉接器（匯流排 轉換裝置），被分級連接之資訊處理系統。 關於複數之內部匯流排經由匯流排轉接器（匯流排轉 換裝置）被分級連接之電腦系統之以往之技術，被公開揭 露於：TP — A— 5 — 233528號公報。 在以往之技術中，經由低速之I / 0模組之傳送妨礙 高速之處理器或記憶體之傳送之故，一般爲：分級連接如 處理器匯流排、系統匯流排、I / 0匯流排之樣子之獨立 匯流排以構築系統。於此，相鄰接之匯流排之間經由匯流 排轉接器（匯流排轉換器）以互相被連接。在一般之資訊 處理裝置中，於互相被連接之匯流排間，通信協定（protoc 〇1) —般不同之故，於匯流排轉換裝置內部進行通信協定 之轉換處理‘。 將處理多媒體特別是動畫影像之應用以個人電腦爲始 之資訊處理裝置實行之情形，處理資料量大之故，由於因 匯流排分級化之通信協定轉換之處理輔助時間，由輸入/ 輸出（I/O)側對於中央運算處理裝置（C PU)或主 記憶裝置之應處理資料之供給，會產生來不及之情形。另 一方面’反之，在C P U或主記亦裝置處理之資料要傳送 位於I / 0側之顯示裝置時，也會產生無法以一定之傳送 率之顯示之可能性。再者，考慮到動畫影像之壓縮、解壓 縮等之處理’由I / 〇側來之資料之供應即使來得及，可 能c P U之處理能力本身也會不足。 本紙張尺度適用中國國家標準（CNSrA4規格（210X 297公t )~^4~- (請先閱讀背面之注意事項再填寫本頁) -裝 訂. .r • IHW · 經濟部中央標隼局員工消費合作社印製 407233 μ五、發明説明f ) 本發明之目的在於提供：將處理多媒體特別是動畫影 像之應用以個人電腦之類之資訊處理裝置實行之情形，以 以往之C P U及匯流排之性能，經由c P U之負荷分散以 實現必要之處理性能之資訊處理系統。更爲特定而言，本 發明之目的在於提供：於以個人電腦之類之資訊處理裝置 處理多媒體特別是動畫影像之應用中，降低c P U之處理 負荷，可以防止起因於系統匯流排等之低速匯流排之通過 量之降低，複數之內部匯流排經由匯流排轉接器被分級連 接之低價格化資訊處理系統。 爲了達成上述目的，依循本發明之1個之形態時，其 構成係：在稱爲資訊處理系統之匯流排轉接器之匯流排轉 換裝置內部，設有可以實行運算或資訊處理之運算處理單 元，於以往系統中，將C P U、I / 0模組進行之處理， 由分級連接複數之內部匯流排之匯流排轉換裝置與資料傳 送並行地可以分擔實行。 如上述般地，運算處理單元存在於匯流排轉換裝置內 部之故，在C P U、主記憶裝置等之C P U匯流排側模組 與高速處理Μ P E G動畫影像資料之圖形裝置之系統匯流 排側模組之間，與交換運算前資料及運算結果之情形相比 ，匯流排層級傳達之傳送頻度減少，可以減少匯流排之負 荷。即，資料傳送之處理輔助時間被減少，系統之整體性 能提昇。 分級連接匯流排之匯流排轉換裝置本身也分擔處理對 象之資料之運算之故，可以防止處理集中在C P U或系統 (請先閱讀背面之注意事項再填寫本頁) 1裝· 訂· Μ- 本紙張尺度適用中國國家標準（CNS ) Λ4規枱（210Χ 297公釐）-5 - 經濟部中央標準局員工消費合作社印製 407233 ;Ί 五、發明説明p ) 匯流排側之i /〇模組（圖形裝置等），系統內之個個之 零件成本可以降低。即使使用低價格之c P U，也可以補 足系統性能。 再者，可以將C P U不在行之處理，例如位元運算等 以匯流排轉換裝置，即設於匯流排轉接器之專用硬體進行 之故’資訊處理性能也提昇。 圖面之簡單說明 圖1係依循本發明之一實施例之匯流排轉換裝置之詳 細方塊圖。 圖2係顯示依循本發明之一實施例之系統槪要之系統 構成圖。 圖3係顯示依循本發明之一實施例之資料傳送時機之 一例之時序圖。 圖4係顯示依循本發明之一實施例之資料傳送時機之 其他之例之時序圖。 圖5係顯示依循本發明之一實施例之系統槪要之代替 方案之之系統構成圖。 圖6係顯示依循實施例之系統匯流排之匯流排使用權 調停信號之連接關係之連接圖。 圖7係依循本發明之別的實施例之匯流排轉換裝置之 詳細方塊圖。 主要元件對照表 本紙張尺度適用中國國家標準（CNS ) A4規桔（210X297公t ) - 6 - {請先閱讀背面之注意事項再填寫本頁) Ϊ裂---- .- *1τ- ....... ΪΪ - 1--1 hi l·/ ' In - - —i 407233 經濟部中央標準局員工消費合作社印製 A7 B7五、發明説明f ) 1 匯流排轉換裝置 2 CPU 3 圖像處理基板 4 主記憶體 5 C P U匯流排界面部 6 匯流排通信協定轉換部 7 運算控制部 8 系統匯流排界面部 9 顯示裝置 I 0 圖像處理器 II 工件記憶體 12 顯示記憶體 10 1 C P U匯流排控制單元 102‘運算處理單元 1 0 3 運算資料寄存器 1 0 4 運算前資料用FIFO 10 5 運算後資料用F I F ◦ 106 運算模式設定寄存器 107 位址寄存器 108 傳送率控制單元 109 系統匯流排控制單元 1 1〇，1 1 1 ，1 12 雙方向輸入輸出緩衝器 113 運算模式控制單元 1 1 4，1 1 9 位址信號線 (讀先閱讀背面之注意事項再填寫本頁) -裝· 訂 本紙張尺度適用中國國家標隼（CNS ) Λ4規格（210X 297公釐） -7- 經濟部中央橾準局員工消費合作社印製 407233 a7 --------B7 五、發明説明$ ) 1 1 5 ’ 1 2 0 資料信號線 116，117，118 選擇器 1 2 1 ’ 1 2 3 控制信號線 12 2 位址/資料信號線 以下佐以圖1至圖6說明本發明之1個之實施例，佐 以圖7說明另外之實施例。 於圖1中’ 1係一般被稱爲匯流排轉接器，在本發明 被特定之匯流排轉換裝置，5爲匯流排轉換裝置1內部之 C P U匯流排界面部，6爲匯流排轉換裝置1內部之匯流 排控制轉換部’ 7爲匯流排轉換裝置1內部之運算控制部 ’ 8爲匯流排轉換裝置1內部之系統匯流排界面部， 1 0 1爲C P U匯流排界面部5內部之C P U匯流排控制 單元，1 0 2爲運算控制部7內部之運算處理單元（ ALU) ，‘10 3爲運算資料寄存器，10 4爲運算前資 料用先進先出寄存器（first-in first-out register )( FIFO) ，：L05爲運算後資料用F I F〇，1〇6爲 運算模式設定寄存器，1 0 7爲運算結果傳送目的地位址 寄存器，1 0 8爲傳送率控制單元，1 0 9爲系統匯流排 界面部8內部之系統匯流排控制單元，1 1 0、1 1 1、 1 1 2爲雙方向輸入輸出緩衝器，1 1 3爲運算模式控制 單元，1 1 4爲由匯流排控制轉換部6至運算控制部7之 資料信號線，116、117、118爲選擇器，119 爲C P U匯流排1 3參考圖2之位址信號線，1 2 ◦爲 C P U匯流排1 3之資料信號線’ 1 2 1爲C P U匯流排 本紙張尺度適用中國國家榇準（CNS ) A4規格（210X297公楚）.g. —--I------- . ·裝--^----訂-----Γ (請先閲讀背面之注意事項再填寫本頁) - 經濟部中央標準局員工消費合作社印製 A7 _____B7 五、發明説明$ ) 1 3之控制信號線’ 1 2 2爲系統匯流排1 4之參考圖2 之被多重化之位址/資料信號線’ 1 2 3爲系統匯流排 1 4之控制信號線。 於圖2中’ 2爲CPU，3爲具有系統匯流排1 4之 界面之圖像處理基板’ 4爲主記憶裝置，9爲顯示裝置， 10爲圖像處理基板3內部之圖像處理器，11爲圖像處 理基板3內部之工件用記憶體’ 1 2爲圖像處理基板3內 部之顯示記憶體。 於圖3中，3 0 1爲系統匯流排1 4之系統時鐘（ C L K )’ 3 0 2爲由匯流排轉換裝置1對於系統匯流排 仲裁器6 0 1 (參考圖6 )之系統匯流排之匯流排使用權 要求信號（BRQO) ，303爲由系統匯流排仲裁器 6 0 1對於匯流排轉換裝置1之匯流排使用權許可信號（ B A K 0 )'，3 0 4爲由圖像處理基板3對於系統匯流排 仲裁器6 0 1之系統匯流排之匯流排使用權要求信號（ B R Q 1 ) ’ 3 0 5爲由系統匯流排仲裁器6 0 1對於圖 像處理基板3之匯流排使用權許可信號（B A K 1 )， 3 ◦ 6爲被多重化之位址/資料信號線（A / D )， 3 0 7爲指定位址循環之位址選通脈衝信號（A S )， 3 ◦ 8爲讀出傳送指定信號（RD ) ，3 0 9爲寫入傳送 指定信號（W T ) ’ 3 1 〇爲報告資料之接受之資料識別 信號（DAK) ’311爲寫入傳送循環，312爲讀出 傳送循環。 於圖4中’ 4 0 1爲系統匯流排1 4之系統時鐘（ (請先閱讀背面之注意事項再填离本頁) -裝.Printed by the Employees' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 407233 __ V. Description of the Invention (1) The present invention relates to information processing devices such as personal computers, workstations, etc., especially to a plurality of internal buses via a bus adapter (bus) Conversion device), a hierarchically connected information processing system. The conventional technology of a computer system in which plural internal buses are hierarchically connected via a bus adapter (bus switching device) is publicly disclosed in: TP — A — 5 — 233528. In the past, the transmission through low-speed I / 0 modules hindered the transmission of high-speed processors or memory. Generally, it is: hierarchical connection such as processor bus, system bus, I / 0 bus Look like independent buses to build the system. Here, adjacent busbars are connected to each other via a bus adapter (busbar converter). In a general information processing device, the communication protocol (protoc 〇1) between the connected buses is generally different, and the conversion processing of the communication protocol is performed inside the bus conversion device. In the case where information processing devices that process multimedia applications, especially animation images, are started with personal computers, the amount of processing data is large. Due to the processing auxiliary time converted due to the hierarchical communication protocol of the bus, the input / output (I The supply of data to be processed by the Central Processing Unit (CPU) or the main memory device on the / O) side will be delayed. On the other hand, on the other hand, when the data processed by the CP or the master or the device is to be transmitted to the display device located on the I / 0 side, there is also a possibility that it cannot be displayed at a certain transmission rate. In addition, considering the processing of compression and decompression of animation images, even if the supply of data from the I / 〇 side is too late, the processing power of c PU may itself be insufficient. This paper size applies to Chinese national standard (CNSrA4 specification (210X 297 g t) ~ ^ 4 ~-(Please read the precautions on the back before filling out this page)-Binding. .R • IHW · Staff of the Central Bureau of Standards, Ministry of Economy Cooperative printed 407233 μ 5. Description of the invention f) The purpose of the present invention is to provide the application of processing multimedia, especially animated images with information processing devices such as personal computers, and the performance of conventional CPUs and buses. An information processing system that achieves the necessary processing performance through c PU load distribution. More specifically, the object of the present invention is to provide: in the application of information processing equipment such as a personal computer to process multimedia, especially animated images, reduce the processing load of c PU and prevent low speeds caused by system buses, etc. A low-price information processing system in which multiple internal buses are hierarchically connected via a bus adapter. In order to achieve the above purpose, when following one form of the present invention, its structure is: inside a bus conversion device called a bus adapter of an information processing system, there is an arithmetic processing unit capable of performing operations or information processing. In the conventional system, the processing performed by the CPU and the I / 0 module can be implemented in parallel by the bus conversion device that hierarchically connects a plurality of internal buses and the data transmission. As mentioned above, because the arithmetic processing unit exists inside the bus conversion device, the CPU bus side module of the CPU, the main memory device, and the system bus side module of the graphics device that processes the PEG animation image data at high speed Compared with the case of exchanging data and calculation results before the calculation, the transmission frequency of the bus level transmission is reduced, which can reduce the load of the bus. That is, the processing assistance time for data transmission is reduced, and the overall performance of the system is improved. The bus conversion device that is connected to the bus in stages is also responsible for the calculation of the processing target data, which can prevent the processing from being concentrated in the CPU or the system (please read the precautions on the back before filling this page). Paper size applies Chinese National Standard (CNS) Λ4 gauge (210 × 297 mm)-5-Printed by Staff Consumer Cooperative of Central Bureau of Standards, Ministry of Economic Affairs 407233; Ί 5. Description of invention p) I / 〇 module on the bus side ( Graphics device, etc.), the cost of each part in the system can be reduced. Even if the low-cost c P U is used, it can complement the system performance. In addition, the processing of CPUs, such as bit calculations, can be performed by a bus conversion device, that is, dedicated hardware provided at the bus adapter. The information processing performance is also improved. Brief Description of the Drawings Figure 1 is a detailed block diagram of a bus conversion device according to an embodiment of the present invention. FIG. 2 is a diagram showing a system configuration according to a system essential according to an embodiment of the present invention. FIG. 3 is a timing chart showing an example of a data transmission timing according to an embodiment of the present invention. FIG. 4 is a timing chart showing other examples of data transmission timing according to an embodiment of the present invention. Fig. 5 is a system configuration diagram showing a system alternative according to an embodiment of the present invention. FIG. 6 is a connection diagram showing a connection relationship of a mediation signal of a bus use right of a system bus according to an embodiment. FIG. 7 is a detailed block diagram of a bus switching device according to another embodiment of the present invention. Comparison table of main components The paper size is applicable to Chinese National Standard (CNS) A4 Orange (210X297g t)-6-(Please read the precautions on the back before filling this page) Cracks-.- * 1τ-. ... ΪΪ-1--1 hi l · / 'In---i 407233 Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention f) 1 Bus conversion device 2 CPU 3 Figure Image processing board 4 Main memory 5 CPU bus interface section 6 Bus protocol conversion section 7 Calculation control section 8 System bus interface section 9 Display device I 0 Image processor II Work memory 12 Display memory 10 1 CPU Bus control unit 102 'arithmetic processing unit 1 0 3 arithmetic data register 1 0 4 pre-operation data FIFO 10 5 post-operation data FIF ◦ 106 operation mode setting register 107 address register 108 transfer rate control unit 109 system bus control Unit 1 10, 1 1 1, 1 12 Bidirectional input and output buffer 113 Operation mode control unit 1 1 4, 1 1 9 Address signal line (read the precautions on the back before filling in this page) This paper size is applicable National Standard (CNS) Λ4 specification (210X 297 mm) -7- Printed by the Consumers 'Cooperative of the Central Government Bureau of the Ministry of Economic Affairs 407233 a7 -------- B7 V. Description of the invention $) 1 1 5' 1 2 0 Data signal lines 116, 117, 118 Selector 1 2 1 ′ 1 2 3 Control signal line 12 2 Address / data signal line The following describes one embodiment of the present invention with reference to FIG. 1 to FIG. 6 Fig. 7 illustrates another embodiment. In FIG. 1, 1 is generally referred to as a bus adapter. In the present invention, the bus conversion device is specified. 5 is a CPU bus interface portion inside the bus conversion device 1, and 6 is a bus conversion device 1. The internal bus control conversion section '7 is the operation control section of the bus conversion device 1' 8 is the system bus interface section of the bus conversion device 1 and 101 is the CPU bus inside the CPU bus interface section 5. Row control unit, 102 is the arithmetic processing unit (ALU) inside the arithmetic control unit 7, '10 3 is the arithmetic data register, and 10 4 is the first-in first-out register for the data before the operation (first-in first-out register) ( FIFO): L05 is FIF for data after operation, 10 is operation mode setting register, 107 is operation result transmission destination address register, 108 is transmission rate control unit, and 10 is system bus Interface bus control unit in interface unit 8, 1 0, 1 1 1, 1 1 2 are bidirectional input and output buffers, 1 1 3 is the operation mode control unit, 1 1 4 is the bus control conversion unit 6 Information to calculation control section 7 Signal line, 116, 117, 118 are selectors, 119 is the CPU bus 1 3 Refer to the address signal line of Figure 2 and 1 2 ◦ is the data signal line of the CPU bus 13 '1 2 1 is the CPU bus Paper size is applicable to China National Standard (CNS) A4 specification (210X297). G. —-- I -------. · Installation-^ ---- Order ----- Γ (Please Read the notes on the back before filling this page)-Printed by A7 _____B7, the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention $) 1 3 Control signal line '1 2 2 is the reference for the system bus 1 4 The multiplied address / data signal line '1 2 3 is the control signal line of the system bus 1 4. In FIG. 2, '2 is a CPU, 3 is an image processing substrate having an interface of a system bus 1 4' 4 is a main memory device, 9 is a display device, 10 is an image processor inside the image processing substrate 3, 11 is a work memory inside the image processing substrate 3 '1 2 is a display memory inside the image processing substrate 3. In FIG. 3, 3 0 1 is the system clock (CLK) 'of the system bus 14 and 3 2 is the system bus from the bus conversion device 1 to the system bus arbiter 6 0 1 (refer to FIG. 6). The bus use right request signal (BRQO), 303 is the system bus arbiter 6 0 1 for the bus use right permission signal (BAK 0) 'for the bus conversion device 1, and 3 0 4 is the image processing substrate 3 For the system bus arbiter 6 0 1 system bus use right request signal (BRQ 1) '3 0 5 is the system bus arbiter 6 0 1 for the image processing substrate 3 bus use right license Signal (BAK 1), 3 ◦ 6 is the multiplexed address / data signal line (A / D), 3 0 7 is the address strobe signal (AS) for the specified address cycle, 3 ◦ 8 is read The transmission designation signal (RD) is output, 3 0 9 is the write transmission designation signal (WT) '3 1 〇 is the received data identification signal (DAK) of the report data, 311 is the write transmission cycle, and 312 is the read transmission cycle . In Figure 4, ‘4 0 1 is the system clock of the system bus 14 ((Please read the precautions on the back before filling out this page)-installed.
•tT 本紙乐尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） -9 - 經濟部中央標準局員工消費合作杜印製 40^333 λ7 Β7_ _ 五、發明説明f ) C L Κ ) ，4 0 2爲由匯流排轉換裝置1對於系統匯流排 仲裁器6 0 1之系統匯流排之匯流排使用權要求信號（ B R Q 〇 ) ，4 0 3爲由系統匯流排仲裁器6 0 1對於匯 流排轉換裝置1之匯流排使用權許可信號（B A K 0 )， 4 0 4爲由圖像處理基板3對於系統匯流排仲裁器6 ◦ 1 之系統匯流排之匯流排使用權要求信號（B R Q 1 )， 4 0 5爲由系統匯流排仲裁器6 0 1對於圖像處理基板3 之匯流排使用權許可信號（BAK 1 )，4 0 6爲被多重 化之位址/資料信號線（A / D )，4 0 7爲指定位址循 環之位址選通脈衝信號（AS) ，408爲讀出傳送指定 信號（RD) ，409爲寫入傳送指定信號（WT)， 4 1 0爲報告資料之接受之資料識別信號（DAk ) ，4 11、412爲寫入傳送循環。 於圖5中，1 5係顯示匯流排轉換裝置1直結之主記 憶裝置用匯流排。 於圖6中’ 6 0 1爲調停系統匯流排之使用權之系統 匯流排仲裁器，6 0 2爲由匯流排轉換裝置1對於系統匯 流排仲裁器6 0 1之系統匯流排之匯流排使用權要求信號 (B R Q 〇 )，6 0 3爲由系統匯流排仲裁器6 〇 1對於 匯流排轉換裝置1之匯流排使用權許可信號（B A K 〇 ) ’ 6 0 4爲由圖像處理基板3對於系統匯流排仲裁器 δ 0 1之系統匯流排之匯流排使用權要求信號（b r q工 )，6 0 5爲由系統匯流排仲裁器6 〇 1對於圖像處理基 板3之匯流排使用權許可信號（β a Κ 1 )。 本紙張尺度適财國®家料（CNS ) A视格（21GX 297公楚)~「1〇 J - ；---^----- 裝----K--訂----f/l.k (請先閱讀背面之注意事項再填寫本頁) . . 經濟部中央標準局員工消費合作社印製 40^^33 ____._Β7_ _ 五、發明説明^ ) 接著，說明一實施例之系統裝置之動作。首先，考慮 位於系統匯流排上之圖像處理基板3進行之處理之一部份 於匯流排轉換裝置1分擔之情形。 參考圖1〜2之方塊圖，圖像處理基板3係將運算前 之資料經由系統匯流排1 4以寫入匯流排轉接器1內之運 算控制部之寄存器1 0 3。將與運算前資料相同地，於運 算後應被傳送之位址寫入運算結果傳送目的地位址寄存器 1 07。運算前資料經由運算前資料用F I F0，被傳送 於運算單元1 0 2。於運算單元1 0 2中，資料遵循被設 定於運算模式控制單元113內部之運算模式設定寄存器 1 0 6之內容，被實行運算處理。依據運算單元1 0 2被 實行之運算在經由掌管泛用之運算之C P U，藉由專用之 硬體實行，可以高速進行之情形，本發明之資訊處理系統 之效果變得稂顯著。例如，資料之壓縮/解壓縮等之運算 即可以適用。 被設定於此運算模式設定寄存器1 0 6之運算模式與 由圖像處理基板3對匯流排轉換裝置1之運算前資料及運 算結果之傳送目的地位址一齊地經由圖像處理基板3被傳 送。 於此，在運算資料寄存器1 0 3被寫入：識別與運算 前資料一齊地被寫入運算結果傳送目的地位址寄存器 1 ◦ 7之位址用之位址識別資訊，以及識別運算模式用之 運算模式識別資訊。 運算模式控制單元113內部之寄存器經由CPU2 本紙浪尺度適用中國國家標準（CNS ) A4規格（210X297公釐〉-11 _ ，裝 一 訂-----Γ - -* (請先閱讀背面之注意事項再填寫本頁) - . 經濟部中央標準局員工消費合作社印製 40^33 Λ7 Β7 _ 五、發明説明θ ) 或圖像處理基板3內部之圖像處理器1 0被設定。經由運 算單元1 0 2被施以運算處理之資料與位址識別資訊及運 算模式識別資訊一齊地被保持於運算後資料用先進先出寄 存器（F I F 0 ) 1 〇 5，經由系統匯流排1 4被傳送於 圖像處理基板側。於此處，運算模式控制單元1 1 3參考 被保持於F I F0 1之上述位址識別資訊，對於在運算結 果傳送目的地位址寄存器1 〇 7被指定之位址，傳送被保 持於F I F 0 1 〇 5之運算後資料地控制之。代替此，經 由在運算結果傳送目的地位址寄存器1 0 7附加增量機能 ’也可以依序傳送於圖像處理基板3之工件記憶體11。 於此，處理之資料爲動畫影像之壓縮，解壓縮等之情形， 圖像之幀率（frame rate )保持一定之故，送出系統匯流排 上之傳送之優先順序之操作成爲必要。掌管此者爲傳送率 控制單元1 ‘0 8，在要求傳送率高之情形，由C P U側來 之處理器I/O (PIO)之傳送要求優先，可以將運算 資料傳送於系統匯流排上。此控制也使用運算模式設定寄 存器106以設定之。 圖4係顯示此時之資料傳送時機之時序圖。 參考圖6，在系統匯流排上傳送資料之情形，匯流排 上之各模組對於調停系統匯流排之使用權之系統匯流排仲 裁器6 0 1 ，主張系統匯流排之匯流排使用權要求信號。 而且，由系統匯流排仲裁器6 0 1只有接受匯流排使用權 許可信號之模組可以使用系統匯流排。於此，參考圖4， 最初之寫入傳送411係：圖像處理基板3將運算前之資 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公粲). 12_~~~ ^:'裝--r---^—訂------/'M (請先閲讀背面之注意事項再填寫本頁) - . 經濟部中央標準局員工消費合作社印製 407233 Λ7 Β7 五Λ發明説明彳0 ) 料·寫入運算資料寄存器1 ο 3之寫入傳送循環，第2個寫 入傳送4 1 2係：被實施運算，被存於運算後資料用 F I F 〇 1 〇 5之資料被傳送於圖像處理基板側之寫入傳 送循環。 於此處，說明了匯流排轉換裝置1自動地將運算後之 資料對於圖像處理基板3傳送之實施形態例，在處理速度 不高之情形，代替方案爲：圖像處理基板3對 F I FO 1 〇 5發出讀出要求，以讀出運算結果也可以。 在該情形，讀出運算資料寄存器1 0 3之情形，控制被存 於運算後資料用F I F Ο 1 〇 5之資料被依序地讀出。 其時之資料傳送時機之時序圖被顯示於圖3。 於此，最初之傳送3 1 1係：圖像處理基板3將運算 前之資料寫入運算資料寄存器1 0 3之寫入傳送循環，第 2個之傳送‘3 1 2係：被實施運算處理，將被存於運算後 資料用F I FO 1 0 5之資料由圖像處理基板3讀出之讀 出傳送循環。 .接著，使用圖7說明本發明之別的實施形態例。與上 述一實施例之不同點爲：運算資料寄存器1 〇 3之輸入非 由系統匯流排被傳送，而係由匯流排控制轉換部6對運算 控制部7之資料信號線1 1 5。 在此實施例中’由c P U或主記憶體裝置一邊對圖像 處理基板3之工件記憶體1 1傳送資料’與此並行對於該 資料進行運算，可以使得C P U 2進行處理之一部份由匯 流排轉換裝置1分擔。 本紙張尺度適用中國國家標準（（^5)六4規格（210乂 297公楚）.13- -.1I.----、裝-- (請先閱讀背面之注意事項再填寫本頁)• tT paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X 297 mm) -9-Consumption cooperation by employees of the Central Standards Bureau of the Ministry of Economic Affairs 40 ^ 333 λ7 Β7_ _ 5. Description of the invention f) CL Κ), 4 0 2 is the system bus arbiter 6 0 1 system bus arbiter request signal (BRQ 〇) by the bus conversion device 1, 4 0 3 is the system bus arbiter 6 0 1 for the bus The bus use right permission signal (BAK 0) of the bus conversion device 1, 4 0 4 is the bus use right request signal (BRQ 1) of the system bus from the image processing substrate 3 to the system bus arbiter 6 ◦ 1 , 4 0 5 is the system bus arbiter 6 0 1 for the bus processing right permission signal (BAK 1) of the image processing substrate 3, and 4 0 6 is the multiplexed address / data signal line (A / D ), 4 0 7 is the address strobe signal (AS) of the designated address cycle, 408 is the read transfer designation signal (RD), 409 is the write transfer designation signal (WT), and 4 1 0 is the report data. The received data identification signal (DAk), 4 11 and 412 are write transmission cycles. In FIG. 5, 15 indicates a bus for the main memory device directly connected to the bus conversion device 1. In FIG. 6, '6 0 1 is a system bus arbiter that mediates the right to use the system bus, and 60 2 is used by the bus conversion device 1 for the system bus of the system bus arbiter 6 0 1 The claim signal (BRQ 〇), 6 0 3 is the system bus arbiter 6 0 1 for the bus use right permission signal (BAK 0) for the bus conversion device 1 and 6 0 4 is the image processing substrate 3 for the System bus arbiter δ 0 1 system bus use right request signal (brq workers), 6 0 5 is the system bus arbiter 6 〇1 for the image processing substrate 3 bus use right permission signal (Β a κ 1). The paper size is suitable for the wealthy country® household materials (CNS) A view grid (21GX 297 male Chu) ~ "1〇J-; --- ^ ----- installed ---- K--order ---- f / lk (Please read the notes on the back before filling this page).. Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 40 ^^ 33 ____._ Β7_ _ V. Description of the Invention ^) Next, the system of an embodiment will be described Operation of the device. First, consider a case where a part of the processing performed by the image processing substrate 3 located on the system bus is shared with the bus conversion device 1. Referring to the block diagram of FIGS. 1 and 2, the image processing substrate 3 is Write the data before the calculation to the register 1 0 of the calculation control section in the bus adapter 1 through the system bus 1 4. Write the address that should be transmitted after the calculation in the same way as the data before the calculation The calculation result is transmitted to the destination address register 1 07. The data before the operation is transmitted to the operation unit 1 0 through the data before the operation using FI F0. In the operation unit 1 0 2, the data follows the data set in the operation mode control unit 113. The contents of the operation mode setting register 1 0 6 are subjected to operation processing. According to the operation unit 1 0 2 The operations performed are performed by the CPU in charge of general-purpose operations and can be performed at high speed by dedicated hardware. The effect of the information processing system of the present invention becomes remarkable. For example, data compression / decompression Such calculations can be applied. The calculation mode set in this calculation mode setting register 106 and the transfer destination address of the data before calculation and the calculation result of the bus conversion device 1 by the image processing substrate 3 pass through the figure together. The image processing substrate 3 is transferred. Here, the calculation data register 103 is written: the identification and the data before the calculation are written together with the calculation result transfer destination address register 1 ◦ 7 address identification information for the address And the operation mode identification information used to identify the operation mode. The registers inside the operation mode control unit 113 are adapted to the Chinese National Standard (CNS) A4 specification (210X297 mm> -11 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ one _ _ _ _ _ _ _ _ _ _ one _ _ _ _ _ _ one _ -Γ--* (Please read the notes on the back before filling this page)-. Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 40 ^ 33 Λ7 Β7 _ Explanation θ) or the image processor 10 in the image processing substrate 3 is set. The data subjected to the arithmetic processing through the arithmetic unit 10 and 2 is held in the arithmetic together with the address identification information and arithmetic mode identification information. The first-in-first-out register (FIF 0) 1 05 for the last data is transferred to the image processing substrate side via the system bus 14. Here, the reference of the operation mode control unit 1 1 3 is held in FI F0 1 above. The address identification information controls the transfer of the data designated by the operation result transfer destination address register 1 07, and the data held after the operation in FIF 0 1 05. Instead of this, it is also possible to sequentially transfer to the work memory 11 of the image processing substrate 3 by adding the incremental function to the destination address register 107 of the operation result. Here, when the processed data is the compression and decompression of the animation image, the frame rate of the image is kept constant, so it is necessary to send the priority order of transmission on the system bus. In charge of this is the transmission rate control unit 1 ‘0 8. In the case of a high transmission rate, the transmission request from the processor I / O (PIO) from the CPU side has priority, and the operation data can be transmitted to the system bus. This control is also set using the operation mode setting register 106. FIG. 4 is a timing chart showing the timing of data transmission at this time. Referring to FIG. 6, in the case of transmitting data on the system bus, the system bus arbiter 6 0 1 of each module on the bus to mediate the use right of the system bus claims the system bus use right request signal . In addition, the system bus arbiter 601 can use the system bus only for the modules that accept the bus use permission signal. Here, referring to FIG. 4, the initial write transmission 411 series: the image processing substrate 3 applies the Chinese paper standard (CNS) A4 specification (210X297 cm) to the capital paper size before calculation. 12_ ~~~ ^: '装--r --- ^ — Order ------ / 'M (Please read the notes on the back before filling this page)-. Printed by the Staff Consumer Cooperative of the Central Bureau of Standards, Ministry of Economic Affairs 407233 Λ7 Β7 Five Λ Description of Invention彳 0) The data transfer cycle of data and write operation data register 1 ο 3, the second write transmission 4 1 2 series: the operation is performed, and the data stored in the operation data FIF 〇1 〇5 is transmitted A write transfer cycle on the image processing substrate side. Here, an example of an embodiment in which the bus conversion device 1 automatically transmits the calculated data to the image processing substrate 3 is described. In the case where the processing speed is not high, the alternative is: the image processing substrate 3 pairs FI FO 1 05 issued a read request to read the operation result. In this case, in the case where the operation data register 103 is read out, the data stored in the control-use data F I F 0 105 are sequentially read out. The timing chart of the data transmission timing at that time is shown in FIG. 3. Here, the initial transmission 3 1 1 series: the image processing substrate 3 writes the data before the operation to the operation data register 1 0 3 in the write transmission cycle, and the second transmission '3 1 2 series: the operation processing is performed The read-out transfer cycle in which the data stored in the post-operation data FI FO 105 is read out by the image processing substrate 3. Next, another embodiment of the present invention will be described with reference to FIG. 7. The difference from the above embodiment is that the input of the calculation data register 103 is not transmitted by the system bus, but is the data signal line 1 15 of the bus control conversion section 6 to the operation control section 7. In this embodiment, “the CPU or the main memory device transmits data to the workpiece memory 1 1 of the image processing substrate 3” while performing operations on the data in parallel, so that part of the processing by the CPU 2 can be performed by It is shared by the bus switching device 1. This paper size applies to the Chinese national standard ((^ 5) six 4 specifications (210 乂 297 cm). 13- -.1I .----, installed-(Please read the precautions on the back before filling this page)
、1T 407233 Λ7 B7 五、發明説明纟1 ) 於此，由CPU2來之傳送係指P I 0存取，由主記 憶體來之傳送爲直接記憶體存取（DMA )。本實施例之 傳送目的地指定方法有以下2種之故，使用p I 〇型之存 取例說明之。 其中一項之傳送目的地指定方法（1)爲CPU2係 p I 0寫入之要領，寫入運算前之資料之方法。c PU不 管指定位址，P I〇寫入資料被寫入運算資料寄存器 1 ◦ 3。被寫入運算資料寄存器1 〇 3之運算前資料經由 運算前資料用F I FO 1 0 4被傳送於運算單元1 〇 2。 通過運算單元1 〇 2之際被實行之運算內容被設定於 運算模式控制單元113內部之運算模式設定寄存器 1 ◦ 6。被實施運算處理之資料被存入運算後資料用 F Ϊ FO 1 〇 5，經由系統匯流排被傳送於圖像處理基板 側。該情形之傳送目的地位址爲C P U 2在P I 0寫入循 環指定之位址。是否使用此傳送匯流排，也以運算模式控 制單元1 1 3內部之運算模式設定寄存器1 〇 6之値設定 之。 另一個之傳送目的地指定方法（2 )爲C PU 2於 P I 〇寫入循環中，指定運算資料寄存器1 〇 3之位址， 寫入運算前之資料之方法。被寫入運算資料寄存器1 〇 3 之運算前資料經由運算前F I FO 1 〇 4被傳送於運算單 元1 0 2。通過運算單元1 〇 2之際被實施之運算內容被 設定於運算模式控制單元113內部之運算模式設定寄存 器1 0 6。被實施運算處理之資料被存入運算後資料用 本紙張尺度適用中國國家標準（€奶）六4規格（2丨0>< 297公楚） (請先閲诮背面之注意事項再填寫本頁) ,-° 經濟部中央標準局員工消費合作社印聚 -14- 經濟部中央標準局員工消費合作社印製 407^33 ^___ 五、發明説明（l2 ) F I F 〇 1 〇 5，經由系統匯流排被傳送於圖像處理基板 側。該情形之傳送目的地位址可以設定於運算模式控制單 元1 1 3內部之運算結果傳送目的地位址寄存器1 〇 7。 又’經由載運算結果傳送目的地位址寄存器1 〇 7附加增 量機能，可以對於圖像處理基板3之工件記憶體1 1依序 傳送。 於上述之哪一種之傳送目的地指定方法中，運算前資 料與位址識別子及運算模式識別子一齊地被寫入運算資料 寄存器1 0 3、運算前資料用F I FO 1 〇 4、運算後資 料用FIFO105，經由運算模式控制單元113，因 應運算前資料之運算模式與運算後之運算結果傳送目的地 位址，運算前資料被加以運算，被傳送於運算結果傳送目 的地位址。 於此說明了 P I 0寫入之情形，在向C PU2方向之 匯流排設置一連串之運算資料寄存器、運算前資料用 F I F 0、運算後資料用F I F ◦，P I 〇讀出之情形也 可以同樣地控制。 又，上述之傳送目的地指定方法（1 ) 、（ 2 )在 DMA型之傳送也同樣可以應用。 具體之運算內容不限於單純之理論、數學運算，也想 像在壓縮圖像之解壓縮等必要之賀夫曼編碼電路等。因此 ，在本發明中，爲了將彙總資料在運算活用之故，具備運 算前資料用F I F Ο 1 0 4、運算後資料用 F I F Ο 1 0 5。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐)~:15_ ' — (請先閱讀背面之注意事項再填商本頁) 、裝. -β ♦ 407233 Λ7 Λ7 ---s_ 五、發明説明<3 ) 在此處顯示之實施例之系統構成中，如圖2所示之主 記憶體裝置雖被連接於c P U匯流排，但是如圖5所示般 $ ’主記憶體裝置直結於匯流排轉換裝置之構成也無礙。 如以上說明過的，依據本發明，運算處理單元存在於 匯流排轉換裝置內部之故，與在c P U匯流排側（C P U '主記憶體裝置等）與系統匯流排側（圖像等之I / 0模 組）之間，一邊進行資料傳送，一邊分擔處理之情形相比 ’可以降低匯流排層間傳遞之資料傳送量。即，資料傳送 之處理輔助時間或匯流排之負荷被降低，系統之整體性能 提昇。又，CPU不在行之處理（位元運算等）以專用硬 體進行之故，資訊處理性能也提昇。再者，匯流排轉換裝 置本身也分擔運算之故，可以防止在C P U或系統匯流排 側知I / 〇模組（圖像等）處理集中，也可以降低系統使 用之個個零#之成本。 ^—mi ^^^1 t^i^— —^n ml nn ^^^1 一 J I 、1 (請先閱讀背面之注意事項再填寫本頁) - 經濟部中央標準局員工消費合作社印裝 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐）_ -1T 407233 Λ7 B7 V. Description of the Invention 纟 1) Here, the transfer from CPU2 refers to P 0 access, and the transfer from the main memory is direct memory access (DMA). The transmission destination designation method of this embodiment has the following two reasons, which will be explained using p I 0 type storage examples. The transfer destination designation method (1) for one item is the method for CPU2 to write p I 0 and write the data before calculation. c PU Regardless of the specified address, P I0 write data is written to the operation data register 1 ◦ 3. The pre-operation data written in the operation data register 1 03 is transmitted to the operation unit 1 2 through the pre-operation data F I FO 1 0 4. The contents of the calculation performed when the calculation unit 1 02 is passed are set in the operation mode setting register 1 ◦ 6 in the operation mode control unit 113. The data subjected to the arithmetic processing is stored in the post-operation data F Ϊ FO 105, and is transmitted to the image processing substrate side via the system bus. The transfer destination address in this case is the address specified by C P U 2 in the P I 0 write cycle. Whether or not to use this transmission bus is also set by the operation mode setting register 1 of the operation mode control unit 1 1 3. Another transfer destination designation method (2) is a method in which the CPU 2 designates the address of the operation data register 103 in the write cycle of P I 0 and writes the data before the operation. The pre-operation data written in the operation data register 1 03 is transferred to the operation unit 102 through the pre-operation F I FO 1 04. The contents of the calculations performed on the occasion of the calculation unit 1 02 are set in the operation mode setting register 106 in the operation mode control unit 113. The data processed by the calculation is stored in the data after the calculation. The paper size applies to the Chinese National Standard (€ milk) 6 4 specifications (2 丨 0 > < 297 Gongchu) (Please read the precautions on the back before filling in this Page),-° Printed by the Consumers 'Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs -14- Printed by the Consumers' Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 407 ^ 33 ^ ___ V. Description of the Invention (l2) FIF 〇 〇 05 It is transferred on the image processing substrate side. In this case, the transfer destination address can be set in the calculation mode control unit 1 1 3 and the internal calculation result transfer destination address register 107 is set. In addition, by adding an operation result to the destination address register 107, an additional increment function can be sequentially transferred to the work memory 11 of the image processing substrate 3. In which of the above-mentioned transmission destination designation methods, the pre-operation data is written into the operation data register 1 0 together with the address identifier and the operation mode identifier 3. The pre-operation data is FI FO 1 〇4 and the post-operation data is used The FIFO 105 transmits the destination address according to the operation mode of the data before the operation and the operation result after the operation via the operation mode control unit 113. The data before the operation is calculated and transmitted to the operation result transmission destination address. The following describes the situation of writing PI 0. A series of arithmetic data registers, FIF 0 for pre-operation data, and FIF for post-operation data are set in the bus to C PU2. The same can be said for PI 0 reading. control. The above-mentioned transfer destination designation methods (1) and (2) can also be applied to DMA-type transfers. The specific calculation content is not limited to simple theory and mathematical operations, but also imagines the necessary Huffman coding circuits, such as decompression of compressed images. Therefore, in the present invention, in order to utilize the aggregated data in calculations, F I F Ο 1 0 4 for pre-operation data and F I F 〇 1 0 5 for post-operation data are provided. This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) ~: 15_ '— (Please read the precautions on the back before filling in the supplier's page), installation. -Β 407233 Λ7 Λ7 --- s_ 5 2. Description of the invention <3) In the system configuration of the embodiment shown here, although the main memory device shown in FIG. 2 is connected to the cPU bus, as shown in FIG. 5 The structure of the device directly connected to the busbar conversion device does not matter. As explained above, according to the present invention, because the arithmetic processing unit exists inside the bus conversion device, it is on the c PU bus side (CPU 'main memory device, etc.) and the system bus side (images, etc.) / 0 module), it can reduce the amount of data transferred between the bus layers compared to the case where the data is transmitted and the processing is shared. That is, the processing auxiliary time of data transmission or the load of the bus is reduced, and the overall performance of the system is improved. In addition, because the CPU does not perform processing (bit operations, etc.) using dedicated hardware, the information processing performance is also improved. In addition, the bus conversion device itself also shares the calculations, which can prevent I / O modules (images, etc.) from being processed centrally in the CPU or system bus, and can also reduce the cost of each zero # used by the system. ^ —Mi ^^^ 1 t ^ i ^ — — ^ n ml nn ^^^ 1 One JI, 1 (Please read the precautions on the back before filling out this page)-Printed copy of the staff consumer cooperative of the Central Standards Bureau of the Ministry of Economic Affairs Paper size applies to China National Standard (CNS) A4 (210X297 mm) _-