JPH0512219A - Process transferring system - Google Patents

Abstract

PURPOSE:To reduce overhead at the time of transferring a process for which a slave processor is made to execute. CONSTITUTION:A master processor 101 generates the process for which the slave processor 105A is made to execute, and the process ID is written into the FIFO 107A of the salve 105A. When a condition that FIFO 107A is not in idle and the slave does not use a bus is realized, an ID output circuit 111A outputs the processor ID of the slave 105A to the bus by the output of an AND gate 109A, and it is written into FIFO 117 by a latch strobe from an OR gate 113. Then, it is noticed to the master 101 that FIFO 117 is not in idle. The master 101 reads the processor ID from FIFO and reads the process ID from corresponding FIFO 107A so as to transfer the code of the corresponding code, the data and control information to the slave 105A.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a process transfer system when a master processor transfers a process to a slave processor for execution.

[0002]

2. Description of the Related Art An information processing system in which one or more slave processors are connected to a master processor and the master processor allocates processes to these slave processors and executes them has been known for a long time. A schematic block diagram showing an example of the hardware configuration of such a system is shown in FIG.

In FIG. 3, a master processor 301 is connected to a status register 303 and a plurality of slave processors A, B, C and D via a bus 305. These slave processors A to D have signal lines 307A, B, C and D, respectively.
, Via a signal to the bit position assigned to the corresponding slave processor in the status register 303. Status register 30
3 is mapped to an appropriate address in the memory space of the master processor 301 or the input / output register space, and the master processor 301 reads the status register 303 by a memory read instruction or an input / output instruction to the slave processors A to D. It is possible to know whether or not the transfer is currently possible. Process transfer is also performed via the bus 305. Since these slave processors appear to the master processor 301 as input / output devices, this transfer can be realized in various forms that are possible when transferring data to the input / output devices. The transfer of a process is, specifically, to give a code of a program to be executed, data to be given to this program, and various information for control to a slave processor. If the slave processor has the program code,
Information identifying the code to be executed may be given instead of the code itself.

In some of these systems,
The master processor creates a process, transfers it to the slave processor's memory, and causes the slave processor to execute the process. In such a conventional system, the master processor that spawned the process sees the status signal from the slave processor to load it. As a result of confirmation, if the process can be transferred, it transfers it.If it cannot transfer, it continues polling the status signal until the slave processor can transfer it, and when the transfer becomes possible, the transfer starts. To do.

In another conventional system, a process to be loaded and executed in a slave processor is put in a software queue, and when the status signal of the slave processor becomes transferable, the process is taken out of the queue and Transfer to slave processor.

However, in the prior art described at the outset, it takes a long time to poll the slave processor, and the master processor is largely disabled due to the process transfer. Also, the second conventional technique has a problem that the load on the master processor is increased due to the overhead associated with operating the queue by software.

[0007]

SUMMARY OF THE INVENTION It is an object of the present invention to solve the above-mentioned problems of the prior art and to provide a process transfer system in which the overhead required for the slave processor to share the load is reduced.

[0008]

SUMMARY OF THE INVENTION According to one embodiment of the invention, a master processor provides a process transfer request to a slave processor. The slave processor stores the received transfer request in the storage means, and when the master processor is ready to accept the transfer of the process, it issues a signal notifying the master processor. The master processor can in response transfer the corresponding process to its slave processor.

This storage means may be a queue for storing the given transfer requests in order, or it may store the transfer requests with priorities and store the one with the highest priority among those currently stored. It may be a storage means for outputting.

The state in which the transfer of the process can be accepted means that the slave processor does not use its local memory in the next memory cycle, so that this memory cycle is used to make the slave processor local memory of the slave processor. It may be in a transferable state in units of memory cycles, that is, transfer to the memory is possible. Alternatively, the slave processor may be in a transferable state in process units in which the next process can be transferred to the local memory at once because the process being executed by the slave processor has ended.

[0011]

1 is a block diagram of a parallel information processing system according to an embodiment of the present invention. The master processor 101 is connected to the slave processors 105A, 105B, ...
.., FIFO 107A, 107B, ... (Since there may be three or more slave processors etc., write "..." in the sense that the number is not limited; (Similar) data input, and FIFO
It is connected to the data output of 117. Also FIFO 117
A status output that is TRUE when data is in is connected to the master processor 101 via signal line 119.

Each slave processor 105A, 105B, ...
Is the local memory allocated to you (not shown)
The status output which becomes TRUE when the is not accessed is given to one input of the AND gates 109A, 109B, .... The FIFOs 107A, 107B, ... Corresponding to the slave processors 105A, 105B, ... A have status output that becomes TRUE when they hold data.
It is applied to the other input of the ND gates 109A, 109B, ... Further, the data outputs of the FIFOs 107A, 107B, ... Are connected to the common bus 103 so that they can be read by the master processor 101. AND gates 109A, 109B, ...
.. is the ID that outputs the ID of the corresponding slave processor when TRUE is given from the AND gate
It is given to the output circuits 111A, 111B, .... The outputs of the AND gates 109A, 109B, ... Are also given to the OR gate 113. The output of the OR gate 113 is given to the latch signal input of the FIFO 117. This allows the AND gate
When any of the outputs of 109A, 109B, ... Becomes TRUE, the slave processor ID which is the output of the ID output circuit 111A, 111B corresponding to the AND gate outputting TRUE is input to the FIFO 117.

The operation of the parallel information processing system configured as described above will be described below. When the system performs a specific process, the master processor 101 divides this process into a number of processes and divides them into the common bus 10
Slave processors 105A, 105B, ...
.. is transferred as data to and executed.

Processes dynamically created by the master processor 101 are slave processors 105A, 105B, as data.
.. must be transferred to the local memory. If the corresponding slave processor is still executing the previous process when attempting this transfer, the actual transfer needs to wait until the end of this process.

In order to realize the processing waiting operation, the master processor 101 generates a process to be executed by the slave processor, and the FIFO 10 of the slave processor 105A, 105B, ...
Write in 7A, 107B, ... The status output of the FIFO 107A, 107B, ... In which the process ID is written in this way becomes TRUE.

For example, it is assumed that the process ID is written in the FIFO 107A in order to cause the slave processor 105A to execute the next process. In this case, the FIFO
107A status output becomes TRUE and AND gate
Applied to one of the inputs to 109A. After that, when the process running on slave processor 105A ends,
Slave processor 105A stops and the status output provided to AND gate 107A becomes TRUE. As a result, the output of the AND gate 107A becomes TRUE, so that I
The processor ID of the slave processor 105A from the D output circuit 111A is transferred to the FIFO by the output of the OR gate 113.
Entered in 117 and stored.

The state that something is stored in the FIFO 117 and can be transferred to the slave processor storing the process ID is transmitted to the master processor 101 by the signal line 119. Master processor
After creating the process, 101 monitors signal line 119 to see if any of the slave processors are ready to transfer. When the master processor 101 detects that a slave processor is ready for transfer,
The first processor ID is read from FO117, and the FIFO corresponding to the corresponding slave processor, here F
The process ID is read from the beginning of the IFO 107A. The process corresponding to this process ID is the slave processor 10
Transfer to 5A local memory (not shown) to activate slave processor 105A. After that, the master processor 101 checks whether there is a process that has not been created yet, and creates it if any. Next, the state of the signal line 119 is monitored again. This process creation / monitor / transfer operation is repeated until all the necessary processes have been created and the FIFO 117 has been emptied. The signal line 119 may be monitored by a program of the master processor 101, or an interrupt may be generated depending on the level of the signal line 119.

In the configuration shown in FIG. 1, when a plurality of slave processors 105A, 105B, ... Can simultaneously receive process transfers, the processor IDs collide on the bus 115 and the writing to the FIFO 117 is normal. Not done to. This is because the hardware for coping with such a case is omitted in order to make the embodiment of FIG. 1 easy to see, and in practice, it can be easily avoided by adopting a well-known arbitration method here. It's just a problem.

Needless to say, the generation of the above-mentioned process transfer request may be asynchronous with the actual process transfer processing. This is why the means for storing the process transfer request is not a simple register but a FIFO or the like. Further, the means for storing the ID of the slave processor which has become able to accept the process transfer request is the FIFO, and the fact that the transfer is possible does not occur when there are plural slave processors. This is because it is asynchronous with the process transfer.

The operation described with reference to FIG. 1 is shown in the flowchart of FIG.

The above-described embodiments are merely examples for explaining the present invention, and there is no intention to limit the present invention thereto.
The present invention can be variously modified other than this embodiment.

For example, in FIG. 1, a process transfer request to a slave processor (specifically, a process ID)
Are stored in the FIFOs 107A, 107B, ... In the order of request generation, and therefore the transfer is also in the order of request generation when viewed for each slave processor. On the other hand, the transfer can be performed in the order of process priority. To this end, the master processor 101 adds the process priority to the process ID and adds the slave processors 105A, 105
Send it to B ... In addition, FIFO107A, 107
Instead of B, ..., A plurality of process IDs and priority pairs are stored, and a storage means that can be called a “sorting register” is used so that the process IDs are read in descending order of priority. Since it is easy to actually create the “sorting register”, its circuit configuration and the like are omitted.

Further, in FIG. 1, when the process in the slave processor is finished, the next process can be transferred. However, the slave processor uses its local memory even while the process is being executed. It is possible to transfer a process from the master processor to the slave processor with no timing.

To do this, each slave processor 105A, 105B, ... Has AND gates 109A, 109B ,.
-The status signal given to is used as a signal indicating that the slave processor does not use the bus in the next memory cycle. Further, a channel for DMA transfer is prepared for each slave processor, and a circuit is configured so that local memory access by the slave processor is prohibited during DMA transfer. Under such a configuration, AND gate 109A,
The outputs of 109B, ... May be used as signals indicating that DMA transfer is possible in the next memory cycle.

[0025]

As described above in detail, according to the present invention, when the master processor transfers a process to the slave processor, the function of monitoring the state of the process or managing the queue of the transfer waiting process is hard. Software, the master processor is relieved of such monitoring / management overhead and improves overall system throughput.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating an embodiment of the present invention.

FIG. 2 is a flowchart illustrating an embodiment of the present invention.

FIG. 3 is a schematic block diagram showing an example of a hardware configuration of a system according to a conventional technique.

[Explanation of symbols]

101: Master processor 103: Common bus 105A, 105B: Slave processor 107A, 107B: FIFO 109A, 109B: AND gate 111A, 111B: ID output circuit 113: OR gate 115: Bus 117: FIFO 119: Signal line

Claims (4)

[Claims] 1. A master processor, a slave processor that executes a process transferred from the master processor, and storage means that is provided in the slave processor and stores a process transfer request sent from the master processor. When the slave processor is ready to accept a process transfer, the slave processor requests the master processor to transfer a process based on a process transfer request stored in the storage means. Process transfer method characterized by. 2. The process transfer system according to claim 1, wherein said storage means is a queue for storing process transfer requests in a given order. 3. The storage means stores a process transfer request with priority given from the master processor, and outputs the highest priority one of the stored process transfer requests. The described process transfer method. 4. The process transfer request is information for identifying a process to be transferred.
Alternatively, the process transfer method described in 3.