A7 B7 35 14twf.doc/008 五、發明説明（ί ) 本發明是有關於一種半導體積體電路元件的製造方 法’且特別是有關於一種結合記憶胞陣列與邏輯電路陣列 於單一晶片的積體電路元件。 —般而言，現在的積體電路，不管是邏輯（logic)產品 或是記憶體(memory)，都需要上百個以上的製程步驟，耗 時約1至2個月，或是更長的時間才得以完成。通常是以 該產品的製程所需經過的微影(photolithography)次數，或 光罩(reticle)數目，來評斷該製程及產品的複雜性。 嵌入式動態隨機存取記憶體（embedded DRAM)是一 種將記憶胞陣列與邏輯電路陣列結合於單一晶片上的積體 電路元件。此種嵌入式動態隨機存取記憶體可以高速存取 大量的資料，對積體電路的應用有很大的助益，其可應用 於處理大量資料的邏輯電路上，例如爲圖形處理器。一個 完成的嵌入式動態隨機存取記憶體包含邏輯電路、轉移場 效電晶體（transfer field effect transistor，transfer FET.) 以及與轉移場效電晶體耦合的電容器。其中，轉移場效電 晶體係作爲電容器之下電極與位元線選擇性耦接的開關， 因此可自電容器讀取資料或將資料存入於電容器。 第1A圖至第1D圖繪示習知一種嵌入式動態隨機存取 記憶體的製造流程剖面圖。請參照第1A圖，繪示一種嵌 入式動態隨機存取記憶體的積體電路元件在製程期間之剖 面圖。如圖示形成動態隨機存取記憶體（DRAM)區100， 和形成邏輯電路區1〇2之一部份的邏輯電晶體。嵌入式動 ，態隨機存取記憶體與邏輯電路係形成於基底104之上，例 如基底爲P型的矽基底1〇4 ’而元件之隔離區例如以區域 本紙張尺度適用中國國家標準（CNS ) A4規格（2丨〇X 297公釐） --------------t;------tT------ΐ (請先閲讀背面之¾意事項#填寫本頁) 經濟部中央標準局員工消費合作社印製 A7 B7 3514twf,doc/008 五、發明説明（）） 氧化法（LOCOS)形成場氧化層106，用以隔離元件。 (請先閱讀背面之注意事項再填寫本頁) 閘極結構108與110的形成方法，先以熱氧化法在邏 輯電路區與記憶體區的基底1〇1上形成一層氧化層，然後， 再以化學氣相沈積法（chemical, vapor deposition;CVD)依序 於氧化層上形成摻雜的多晶矽(polysilicon)層、矽化鎢（WSix) 層與氮化矽（Si3N4)層。接著，再進行圖案的定義，以形成 閘極氧化層(gate oxide) 112與114、多晶砂層116與118、 氮化鈦金屬矽化物層120與122 ,以及氮化矽閘極頂蓋層 121與1%。然後，以閘極頂蓋層124與126爲罩幕，對 整個晶片進行淡離子的植入，形成淡離子摻雜區128與 130。此區植入的離子濃度不高，主要是用來作爲防止短 通道效應（short channel effect)發生的輕接雜汲極（lightly doped drains ;LDD)之用。 接著，請參照第IB圖，以CVD的方式於DRAM區與 邏輯電路區沈積一 Si02層，用來做爲閘極間隙壁(spacer) 之用。接下來，將LDD植入後的晶片以900°C〜1000°C左 右的高溫，進行高溫回火（annealing)，以使摻雜離子經由 熱擴散而活化，形成摻雜均勻分佈的區域128a與130a。 ； 經濟部中央標準局員工消費合作社印製 然後，利用非等向性蝕刻方式蝕刻8丨02層，而在閘極結構 108與110的側壁分別形成間隙壁132與134,再於DRAM 區100與邏輯電路區102的基底104上覆蓋一層絕緣層136 與138。接著，以一光阻140覆蓋於DRAM區100的基底 104上，移除邏輯電路區102的絕緣層138後，進行邏輯 電路區102源極與汲極的重摻雜(heavy doping)步驟。 其後，請參照第1C圖，移除邏輯電路區102的絕緣 1 本紙張尺度適用中國國家標準（CNS ) A1規格（2丨〇><297公釐） 經濟部中央標準局員工消費合作社印製 3514twf.doc/008 五、發明説明（彡) 一—~ 一 層138後，對基底1〇4進行高濃度且深度(depth)較深的離 子植入，於邏輯電路區102形成濃離子摻雜區142，此植 入將作爲源極與汲極的主體之用。接著，以自動對準砂化 物的方法在源極/汲極區142形成金屬矽化物。首先，在 基底104上先形成一金屬層144 ,其材質例如鈦，形成的 方法例如爲物理氣相沈積法。 然後，請參照第1D圖，將基底1〇4快速升溫至約 700°C〜800°C左右’進行初次回火，以使源極/汲極區ι42 之矽表面上的金屬層144矽化爲金屬矽化物146。接著， 將基底104置於例如過氧化氫(h2〇2)與氫氧化銨(NH4OH) 的水溶液中’進行蝕刻，以去除未反應的鈦金屬，並再進 行第二次的回火，以降低源極/汲極上金屬矽化物146的 阻値。 .習知的嵌入式動態存取記憶體的製造方法中，以自動 對準矽化物的方法在源極/汲極區142形成金屬矽化物， '其主要目的是爲了降低DRAM區100和邏輯電路場效電 晶體108、110之源極/汲極區142的接觸阻値（contact resistance)，增加導電性。然而，DRAM區1〇〇採用自動 對準矽化物的方式，易造成源極/汲極區128a的淺接面 (shallow junction)變淺，而導致與源極/汲極區128a耦接 的電容器嚴重的漏電現象，因此dram區無須採用自動 對準矽化物的方式來降低源極/汲極區128a之接觸阻値。 由於DRAM區不進行自動對準矽化物的反應，於是可將 間隙壁的形成和重離子摻雜步驟予以簡化。 因此本發明的主要目的之一就是在DRAM區無須形 ^-- (請先閲讀背面之注意事項再填寫本頁) -钉 -線 _ 本紙張尺及適用中國國家標準（CNS > A4規格（210X297公釐） A7 B7 3 5 14 twf. doc/008 五、發明説明（P) 成金屬矽化物的情況下’簡化重離子摻雜步驟，同時加以 簡化DRAM區形成閘極間隙壁的步驟，使製程進行時間 縮短。 本發明的另一目的就是在避免DRAM區因使用電漿 (plasma)進行間隙壁蝕刻時，對元件造成的損害。 根據本發明之上述目的，提出一種半導體積體電路元 件的製造方法，其簡述如下：在定義完整個閘極後，接著 進行LDD的離子植入步驟。爲形成閘極間隙壁之si〇2層 沈積在DRAM區與邏輯電路區表面，此時，dram區以 一光阻作爲罩幕覆蓋於其上後，再以非等向性的蝕刻方式 (anisotropic etch) ’對晶體進行所謂的間隙壁蝕刻步驟。 如此，DRAM區便不形成間隙壁，亦不會因進行間隙壁的 蝕刻製程所使用的電漿而受損，而且也同時簡化了習知 DRAM區的部份製程。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： 圖式之簡單說明： 第1A圖至第1D圖繪示習知一種嵌入式動態隨機存取 記憶體的製程流程剖面圖；以及 第2A圖至第2D圖，繪示依照本發明較佳實施例，一 種嵌入式動態隨機存取記憶體的製造流程剖面圖。 圖式之標記說明： 100 5 200 動態隨機存取記憶體區 尽紙張尺度適用中國國家標準.（CNS ) A4規格（210X297公釐 —.1111 n 11 I I — 訂 ~~ I—# (請先聞讀背面之注-意事項再填寫本頁) 經濟部中央襟準局員工消費合作社印製 35ΐ4^ί^〇ς/008 Α7 Β7 五、發明説明（t) 102 104 106 108 112 116 120 202 204 206 110 114 118 122 邏輯電路區 基底 隔離區 208 ， 210 212 ， 214 216 ， 218 220 ， 222 閛極結構 閛極氧化層 多晶矽層 氮化鈦金屬砂化物層 閘極頂蓋層 128 ， 128a ， 130 ， 130a ， 228 ， 228a ， 230 ， 230a 淡離子摻雜區 132，134，234 間隙壁 138，232絕緣層 光罩 242 N+濃離子摻雜區 244 金屬層 246 金屬矽化物 124 ， 126 ， 224 ， 226 N· 136 140 142 144 146 --------—ιί------tr------%» (請先Η讀背面之注意事項再填寫本頁) 經濟部中央標準局負工消費合作社印製 第2A圖至第2D圖，繪示依照本發明較隹實施例一種 嵌入式動態隨機存取記憶體的製造流程剖面圖。 請參照第2A圖，繪示一種嵌入式動態隨機存取記憶 體的積體電路元件在製程期間之剖面圖。在圖式200欲形 成 DRAM區，而在圖式202則欲形成一邏輯電路區 嵌入式動態隨機存取記憶體區200與邏輯電路區202形成 於基底204之上，而元件之隔離區206例如以區域氧化法 本紙張尺度適用中國囤家標準（CNS ) A4規格（210X 297公釐） A7 B7 3 5 14twf.doc/008 五、發明説明（i) (LOCOS)形成場氧化區，以隔離元件；或以淺溝渠隔離 法（STI)形成溝渠之後，再以化學氣相沈積的方法，將 氧化物塡入溝渠的方式形成。 閘極結構208與210的形成方法，例如以熱氧化法在 DRAM區200和邏輯電路區202的基底204上形成一層氧 化層，然後，再以CVD法依序於氧化層上形成摻雜的多 晶矽層、矽化鎢層與氮化矽層。接著，再進行圖案的定義， 以形成閘極氧化層212與214、多晶矽層216與218、氮 化鈦金屬矽化物層220與222，以及氮化矽閘極頂蓋層224 與226。然後，以閘極頂蓋層224與226爲罩幕，對整個 晶片進行淡離子的植入，形成淡離子摻雜區228與230。 此植入的離子濃度不高，主要是用來作爲防止短通道效應 發生的輕摻雜汲極之用。 接著，請參照第2B圖，例如以CVD的方式於DRAM 區200與邏輯電路區202沈積一絕緣層，用來做爲閘極間 隙壁之用，絕緣層例如爲8丨02層，。接下來，將LDD N-植入後的晶片以900°C〜1000°C左右的高溫，進行高溫回 火’以使摻雜離子經由熱擴散而活化，形成摻雜均勻分佈 的區域228a與230a。然後，別於習知之作法，在對絕緣 層進行間隙壁的蝕刻製程前，DRAM區200的絕緣層232 以一光罩240覆蓋於其上，則乾蝕刻法只對邏輯電路區202 的Si02層進行，故邏輯電路區202閘極結構210的側壁形 成間隙壁234，暴露出LDD區230a，而DRAM區200由 於有光罩240的覆蓋，因此絕緣層232仍完整覆蓋在基底 2〇4上。接下來則進行邏輯電路區2〇2源極與汲極的重摻 本紙張尺度適用中國國家檩準（CNS ) A4規格（210X297公釐） ) . I I r: I n ^ — i I I 絲 (請先閱讀背面之洼意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 經濟部中央標準局員工消費合作社印裂 A7 3514twf.doc/008 B7 五、發明説明（〇 ) 雜(heavy doping)步驟。 其後，請參照第2C圖，對基底204進行高濃度且深 度較深的離子植入，形成濃離子摻雜區242，此植入將作 爲源極與汲極的主體之用。接著，移除覆蓋於DRAM區200 之光罩240。在習知步驟中，此時需沈積一絕緣層以作爲 進行自動對準矽化物反應之罩幕，但本發明中由於DRAM 區200不形成間隙壁，因此絕緣層232仍完整覆蓋在基底 204之上，因此在光阻240移除後，可直接以所沈積的Si02 層232作爲進行自動對準矽化物反應之罩幕。因此接下來 便在邏輯電路區202的源極/汲極區242進行自動對準矽 化物的反應。首先，在基底204上先形成一層金屬層244， 其材質包括鈦，形成的方法例如爲物理氣相沈積法。 然後，請參照第2D圖，將元件快速升溫至約 700°C〜800°C左右，進行初次回火，以使源極/汲極區242 之矽表面上的金屬層244矽化爲金屬矽化物246。接著， 將基底204置於例如過氧化氫(H202)與氫氧化銨(NH4OH) 的水溶液中，進行蝕刻，以去除未反應的鈦金屬，並再進 行第二次的回火，以降低源極/汲極242上金屬矽化物246 的阻値。由於DRAM區200不進行濃離子的摻雜和自動 對準矽化物的反應，因此本發明直接省略了此二步驟所需 开多成的間隙壁和沈積一絕緣層步驟，簡化了嵌入式動態隨 機存取記憶體之製程。 綜上所述，本發明的優點在於： L本發明之嵌入式動態隨機存取記憶體的製程中，形 成自動對準矽化物程序，由於DRAM區不形成間隙壁， 本紙張尺度適用中國國家標準（CNS ) Α4^_ ( 21〇χ297公餐） ----------贫：------訂------線Ν (請先閲讀背面之注意事項再填寫本頁) A7 B7 35 14twf.doc/〇〇8 五、發明説明（？） 因此於光罩移除後’直接以原欲形成間隙壁的絕緣層作爲 DRAM區之罩幕層，而使自動對準矽化物反應在邏輯電路 區進行，因此可簡化習知製程。 2.因DRAM區之閘極與氧化層具有光罩覆蓋，故間 隙壁的蝕刻製程只在邏輯電路區進行，因此蝕刻間隙壁時 所甩的電漿不會損及DRAM區的記憶胞。 3·由於DRAM區不需進行自動對準矽化物和濃離子 摻雜的程序，因此可簡化DRAM'區形成間隙壁的步驟， 使嵌入式動態隨機存取記憶體的製造方法更爲簡單。. 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 當視後附之申請專利範圍所界定者爲準。 ----------繫-------,ρ—^-----銷 (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作杜印製 本紙張尺度適用中國國家標準（CNS ) Α4^格（2丨0X297公釐）A7 B7 35 14twf.doc / 008 V. Description of the invention (ί) The present invention relates to a method for manufacturing a semiconductor integrated circuit element ', and in particular to a integrated product combining a memory cell array and a logic circuit array on a single chip Circuit components. -In general, today's integrated circuits, whether they are logic products or memories, require hundreds of process steps, which take about 1 to 2 months, or longer. Time can be done. The complexity of the process and product is usually judged by the number of photolithography or number of reticles that the product needs to go through. Embedded dynamic random access memory (embedded DRAM) is a type of integrated circuit element that combines a memory cell array and a logic circuit array on a single chip. This type of embedded dynamic random access memory can access a large amount of data at high speed, which is very helpful for the application of integrated circuits. It can be applied to logic circuits that process large amounts of data, such as graphics processors. A completed embedded dynamic random access memory includes a logic circuit, a transfer field effect transistor (transfer FET), and a capacitor coupled to the transfer field effect transistor. Among them, the transfer field effect transistor system serves as a switch that selectively couples the electrode below the capacitor to the bit line, so data can be read from the capacitor or stored in the capacitor. FIG. 1A to FIG. 1D are cross-sectional views showing a conventional manufacturing process of an embedded dynamic random access memory. Referring to FIG. 1A, a cross-sectional view of an integrated circuit element of an embedded dynamic random access memory during a manufacturing process is shown. As shown, a dynamic random access memory (DRAM) area 100 is formed, and a logic transistor forming a part of the logic circuit area 102 is formed. Embedded dynamic, state random access memory and logic circuits are formed on the substrate 104. For example, the substrate is a P-type silicon substrate 104 ', and the isolation area of the component is, for example, a Chinese paper (CNS) ) A4 specification (2 丨 〇X 297 mm) -------------- t; ------ tT ------ ΐ (Please read the intention on the back first Matters # Fill in this page) Printed by the Consumers' Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs A7 B7 3514twf, doc / 008 V. Description of the Invention ()) The oxidation method (LOCOS) forms a field oxide layer 106 to isolate components. (Please read the precautions on the back before filling this page.) To form the gate structures 108 and 110, first form an oxide layer on the substrate 101 of the logic circuit area and the memory area by thermal oxidation, and then, A chemical vapor deposition (CVD) method is used to sequentially form a doped polysilicon layer, a tungsten silicide (WSix) layer, and a silicon nitride (Si3N4) layer on the oxide layer. Then, the pattern definition is performed to form gate oxides 112 and 114, polycrystalline sand layers 116 and 118, titanium nitride metal silicide layers 120 and 122, and silicon nitride gate capping layers 121 and 1%. Then, using the gate capping layers 124 and 126 as a mask, light ion implantation is performed on the entire wafer to form light ion doped regions 128 and 130. The implanted ion concentration in this region is not high, and it is mainly used as lightly doped drains (LDD) to prevent the occurrence of short channel effects. Next, referring to FIG. IB, a SiO2 layer is deposited on the DRAM area and the logic circuit area by CVD, which is used as a gate spacer. Next, the wafer after the LDD implantation is subjected to high-temperature annealing at a high temperature of about 900 ° C to 1000 ° C, so that the dopant ions are activated by thermal diffusion to form uniformly doped regions 128a and 130a. Printed by the Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs, and then anisotropically etch 8 to 02 layers, and the spacers 132 and 134 are formed on the sidewalls of the gate structures 108 and 110, respectively, and then in the DRAM area 100 and The substrate 104 of the logic circuit region 102 is covered with an insulating layer 136 and 138. Next, a photoresist 140 is used to cover the substrate 104 of the DRAM area 100. After the insulating layer 138 of the logic circuit area 102 is removed, a heavy doping step is performed on the source and drain of the logic circuit area 102. After that, please refer to Figure 1C to remove the insulation of the logic circuit area 102. This paper size is applicable to the Chinese National Standard (CNS) A1 specification (2 丨 〇 > < 297 mm) Employees' Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs Printed 3514twf.doc / 008 V. Description of the invention (彡) I. After one layer of 138, the substrate 104 is subjected to high-concentration and deep-depth ion implantation to form a concentrated ion dopant in the logic circuit region 102. Miscellaneous region 142, this implant will be used as the source and sink body. Next, a metal silicide is formed in the source / drain region 142 by automatically aligning the sand. First, a metal layer 144 is formed on the substrate 104, and a material of the metal layer 144 is, for example, titanium. Then, referring to FIG. 1D, the substrate 104 is rapidly heated to about 700 ° C to 800 ° C for initial tempering, so that the metal layer 144 on the silicon surface of the source / drain region ι42 is silicided into Metal silicide 146. Next, the substrate 104 is etched in an aqueous solution of, for example, hydrogen peroxide (h2O2) and ammonium hydroxide (NH4OH) to remove unreacted titanium metal, and a second tempering is performed to reduce Resistance of metal silicide 146 on source / drain. In the conventional manufacturing method of embedded dynamic access memory, a metal silicide is formed in the source / drain region 142 by automatically aligning the silicide. Its main purpose is to reduce the DRAM area 100 and the logic circuit. The contact resistance of the source / drain regions 142 of the field effect transistors 108 and 110 increases the conductivity. However, the DRAM area 100 is automatically aligned with silicide, which tends to cause the shallow junction of the source / drain region 128a to become shallower, resulting in a capacitor coupled to the source / drain region 128a. Severe leakage phenomenon, so there is no need to automatically align the silicide in the dram region to reduce the contact resistance of the source / drain region 128a. Since the DRAM region does not carry out the auto-alignment silicide reaction, the steps of forming the spacer and the heavy ion doping can be simplified. Therefore, one of the main purposes of the present invention is not to be shaped in the DRAM area. ^-(Please read the precautions on the back before filling this page) -Nail-Thread_ This paper ruler and the applicable Chinese national standard (CNS > A4 specifications ( 210X297 mm) A7 B7 3 5 14 twf. Doc / 008 V. Description of the invention (P) In the case of forming a metal silicide, 'simplify the heavy ion doping step, and at the same time, simplify the step of forming the gate gap wall of the DRAM region, so that The process progress time is shortened. Another object of the present invention is to avoid the damage to the elements caused by the plasma wall etching using the plasma for the DRAM area. According to the above object of the present invention, a semiconductor integrated circuit element is proposed. The manufacturing method is briefly described as follows: After the entire gate is defined, the ion implantation step of LDD is performed. In order to form a gate gap wall, a SiO2 layer is deposited on the surface of the DRAM area and the logic circuit area. After the area is covered with a photoresist as a mask, the so-called spacer etching step is performed on the crystal by anisotropic etch. In this way, the DRAM area does not form a spacer. It will not be damaged by the plasma used in the etching process of the spacer, and it also simplifies part of the process of the conventional DRAM area. In order to make the above and other objects, features, and advantages of the present invention more Obviously easy to understand. The following is a detailed description of a preferred embodiment and the accompanying drawings. The following is a brief description of the drawings: Figures 1A to 1D show an embedded dynamic random access memory. And FIG. 2A to FIG. 2D are cross-sectional views of a manufacturing process of an embedded dynamic random access memory according to a preferred embodiment of the present invention. Marking description of the drawing: 100 5 200 The paper size of the dynamic random access memory area applies the Chinese national standard. (CNS) A4 specification (210X297 mm—.1111 n 11 II—Order ~~ I— # (Please read the notes on the back-please note before filling in (This page) Printed by the Consumer Cooperative of the Central Commission of the Ministry of Economic Affairs 35ΐ4 ^ ί ^ 〇ς / 008 Α7 Β7 V. Description of the invention (t) 102 104 106 108 112 116 120 202 204 206 110 114 118 122 Logic circuit area base isolation Zones 208, 210, 212 214 216, 218 220, 222 Pt structure Pt oxide layer Polycrystalline silicon layer Titanium nitride metal sanding layer Gate capping layer 128, 128a, 130, 130a, 228, 228a, 230, 230a Light ion doped regions 132, 134 , 234 spacer 138, 232 insulating layer mask 242 N + concentrated ion doped region 244 metal layer 246 metal silicide 124, 126, 224, 226 N · 136 140 142 144 146 --------— ----- tr ------% »(Please read the notes on the back before filling out this page) The Central Standards Bureau of the Ministry of Economic Affairs has printed Figures 2A to 2D. A cross-sectional view of a manufacturing process of an embedded dynamic random access memory according to a comparative embodiment of the present invention. Referring to FIG. 2A, a cross-sectional view of an integrated circuit element of an embedded dynamic random access memory during a manufacturing process is shown. In the diagram 200, a DRAM area is to be formed, and in the diagram 202, a logic circuit area is to be formed. The embedded dynamic random access memory area 200 and the logic circuit area 202 are formed on the substrate 204. The isolation area 206 of the device is According to the regional oxidation method, the paper scale is applicable to the Chinese standard (CNS) A4 specification (210X 297 mm) A7 B7 3 5 14twf.doc / 008 V. Description of the invention (i) (LOCOS) Form a field oxidation area to isolate the element Or after the trench is formed by the shallow trench isolation method (STI), and then formed by chemical vapor deposition into the trench. The gate structures 208 and 210 are formed by, for example, forming an oxide layer on the substrate 204 of the DRAM region 200 and the logic circuit region 202 by a thermal oxidation method, and then sequentially forming a doped polycrystalline silicon on the oxide layer by a CVD method. Layer, tungsten silicide layer and silicon nitride layer. Next, pattern definition is performed to form gate oxide layers 212 and 214, polycrystalline silicon layers 216 and 218, titanium nitride metal silicide layers 220 and 222, and silicon nitride gate cap layers 224 and 226. Then, using the gate capping layers 224 and 226 as a mask, light ion implantation is performed on the entire wafer to form light ion doped regions 228 and 230. The implanted ion concentration is not high, and it is mainly used as a lightly doped drain to prevent short channel effects. Next, please refer to FIG. 2B. For example, an CVD method is used to deposit an insulating layer on the DRAM area 200 and the logic circuit area 202 for use as a gate gap wall. The insulating layer is, for example, a 8/02 layer. Next, the LDD N-implanted wafer is tempered at a high temperature of about 900 ° C to 1000 ° C to activate doped ions through thermal diffusion to form uniformly doped regions 228a and 230a. . Then, unlike the conventional method, before performing the spacer etching process on the insulating layer, the insulating layer 232 of the DRAM region 200 is covered with a photomask 240, and the dry etching method only applies to the Si02 layer of the logic circuit region 202. As a result, the sidewalls of the gate structure 210 of the logic circuit region 202 form a gap 234, exposing the LDD region 230a, and the DRAM region 200 is covered by the photomask 240, so the insulating layer 232 is still completely covered on the substrate 204. Next, the source and drain electrodes of the logic circuit area are re-doped. The paper size is in accordance with the Chinese National Standard (CNS) A4 (210X297 mm). II r: I n ^ — i II wire (please (Read the ins and outs on the back before filling in this page) Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs A7 3514twf.doc / 008 B7 V. Explanation of the invention )step. Thereafter, referring to FIG. 2C, a high-concentration and deep-deep ion implantation is performed on the substrate 204 to form a concentrated ion-doped region 242. This implantation will be used as the source and drain body. Then, the mask 240 covering the DRAM area 200 is removed. In the conventional step, an insulating layer needs to be deposited at this time as a mask for performing the auto-aligned silicide reaction. However, in the present invention, since the DRAM region 200 does not form a gap wall, the insulating layer 232 still completely covers the substrate 204. Therefore, after the photoresist 240 is removed, the deposited SiO 2 layer 232 can be directly used as a mask for performing the auto-alignment silicide reaction. Therefore, the source / drain region 242 of the logic circuit region 202 is automatically reacted with the silicide. First, a metal layer 244 is formed on the substrate 204, and the material includes titanium. The method for forming the metal layer 244 is, for example, a physical vapor deposition method. Then, referring to Figure 2D, rapidly heat the device to about 700 ° C ~ 800 ° C, and perform the first tempering to silicify the metal layer 244 on the silicon surface of the source / drain region 242 into a metal silicide. 246. Next, the substrate 204 is placed in an aqueous solution of, for example, hydrogen peroxide (H202) and ammonium hydroxide (NH4OH), and is etched to remove unreacted titanium metal, and then tempered a second time to reduce the source electrode. Resistance of metal silicide 246 on drain / 242. Since the DRAM region 200 does not perform the doping of concentrated ions and the reaction of automatically aligning the silicide, the present invention directly omits the steps of the spacer and the deposition of an insulating layer required for these two steps, which simplifies the embedded dynamic randomization. Process of accessing memory. In summary, the advantages of the present invention are as follows: In the process of the embedded dynamic random access memory of the present invention, an automatic alignment silicide process is formed. Since the DRAM area does not form a gap wall, this paper size applies to Chinese national standards (CNS) Α4 ^ _ (21〇χ297 public meal) ---------- Poor: -------- Order ------ Line N (Please read the notes on the back before filling (This page) A7 B7 35 14twf.doc / 〇〇8 V. Description of the invention (?) Therefore, after the photomask is removed, the insulation layer that is intended to form the barrier wall is directly used as the cover layer of the DRAM area, so that the automatic alignment is performed. Quasi-silicide reactions occur in the logic circuit area, which simplifies the conventional process. 2. Because the gate and oxide layer of the DRAM area are covered with a photomask, the etching process of the gap wall is performed only in the logic circuit area. Therefore, the plasma thrown during the etching of the gap wall will not damage the memory cells in the DRAM area. 3. Since the DRAM area does not need to perform the process of automatically aligning silicide and dopant ion doping, the steps of forming a gap wall in the DRAM 'area can be simplified, and the manufacturing method of the embedded dynamic random access memory is simpler. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present invention. The warranty of the present invention shall be determined by the scope of the appended patent application. ---------- Department -------, ρ — ^ ----- pin (please read the precautions on the back before filling this page) The printed paper size is applicable to the Chinese National Standard (CNS) Α4 ^ grid (2 丨 0X297 mm)