經濟部中央標準局員工消費合作社印製 31C463 A7 1 4 3 5 t w f / M u I cl e r H u / 0 0 2 B? 五、發明説明（I ) 本發明是有關於半導體隔離製程中之淺接面_離_ 槽製程，且特別是有關於在上述製程中改痗淺接_隔離溝 槽邊角過尖之方法。 積體電路其積集度越來越高，在先進的V L SI製程上， 可以在1〜2cm2面積的矽表面上形成數量多達數十萬個 MOS電晶體，爲使電晶體與電晶間的操作不致受到對方的 干擾，必須設法將每個電晶體間相隔離，以避免產生短路， 此製程稱爲隔離製程》 習知一種隔離製程的方法是在半導體基底上，依序形 成一墊氧化層及一氮化矽層，然後以微影製程及蝕刻技術 在預定形成淺隔離溝槽處定義出一窗口。接著，再以氮化 矽層爲罩幕，蝕刻裸露出基底表面之窗口到基底下，形成 一隔離用的淺溝槽。其製程於第1A圖〜1C圖詳細說明之。 請先參照第1A圖，提供一半導體基底丨(），先形成一 墊氧化層例如是二氧化矽層12於半導體基底上，再形成一 絕緣層例如是氮化砂層14於：::氧化砂層h 然後，以微影 製程及蝕刻程序在預定形成淺接面隔離溝槽處，定義出一 裸露出基底表面之開口 15。 其次，請參照第1B圖，以氮化矽層14爲蝕刻罩幕， 蝕刻開口 1 5裸露之基底表面到基底内，形成一淺接面隔離 用溝槽15’。 最後，請參照第1C圖，依序去除氮化矽層14及墊氧 化層12，完成·淺接面隔離用溝槽之製造。 其中，因淺接面隔雛用溝槽之邊緣角落非常尖峭，在 本紙張疋度適用中國國家梯準（CNS ) A4规格（210X297公釐> 83. 3. !0,0〇〇 ------.---衣— (請先聞讀背面之注意事項再填寫本頁) 訂 經濟部中央標準局貝工消费合作社印聚 3IG463 I 435twf/Mulder Hu/〇〇2 五、發明说明（二） 溝塡絕緣物質如二氧化矽到溝槽16内以形成-一溝塡有絕 緣物質之淺接面隔離溝槽21時，造成如第2圖所標號19 之構造，相較於其他平坦的地方，在角落的絕緣層會有偏 薄之現象，此轉折區偏薄之情形，在半導體運作時會造成 二次導通現象（double hump)，產生寄生電場。 有鑒於此，本發明提出--種淺接面隔離溝槽製程，以 改善淺接面隔離溝槽邊緣角落過尖之問題，其步驟包括： 提供一半導體基底；依序形成一墊氧化層及一絕緣層於該 基底上；以光學微影程序及蝕刻技術定義該墊氧化層及該 絕緣層，並形成至少一裸露出該半導體基底表面之開口； 形成一蝕刻緩衝層於該絕緣層上及該開口側壁及其裸露 的基底表面；回蝕刻該蝕刻緩衝層，形成一側壁間隔層於 該開口之該墊氧化層及該絕緣層側壁；以該絕緣層爲蝕刻 罩幕，蝕刻該開口裸露之基底表面，並沿該側壁間隔層之 外側蝕刻，形成一具圖滑邊角之淺接面隔離溝槽，該側壁 間隔層並在蝕刻過程中逐漸被去除；以及依序去除該絕緣 層及該墊氧化層，完成具圓滑邊角之淺接面隔離溝槽製 造。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： 圖式之簡單說明： 第1A〜1C圖是習知一種淺接面隔離溝槽之剖面製造 流程圖。 4 (請先閱讀背面之注意事項再填寫本頁) 袈. 訂 本紙張尺度適用中國國家標率（CNS > A4规格（210X297公釐） 83. 3.10,000 310463 I 43 5twf/Muldcr Hu/002 經濟部中夬標率局貝工消费合作社印製 五、發明説明（2 ) 第2圖是將如第1C圖所示構造溝塡絕緣物後之淺接面 隔離溝槽。 第3A〜3F圖是根據本發明之淺接面隔離溝槽剖面製 造流程圖。 第4圖是將如第3F圖所不:構造溝塡絕緣物後之淺接面 隔離溝槽。 實施例： 首先，請先參照第3A圖，提供一如第1A圖所示之結 構，其包括有一半導體基底10，一墊氧化層12，一絕緣 層例如是氮化矽層14，然後，以微影製程及蝕刻程序在預 定形成淺接面隔離溝槽處，定義出一裸露出基底表面之開 □ 15。 其次，請參照第3B圖，形成一蝕刻緩衝層16於絕緣 層14上及開口 15之側壁及其底部之基底表面；其中，触 刻緩衝層例如是以低壓化學氣相沈積法（LPCVD)沈積的複 晶矽層，其厚度約介於300〜500A » 然後，請參照第3C圖，回蝕刻緩衝層16，並在開口 15之墊氧化層/氮化矽層側壁形成一複晶矽側壁間隔層 16,。 接著，請參照第3D圖，以氮化矽層14爲罩幕，逐漸 蝕刻到裸露之基底表面，形成-淺接面溝槽Π ;其中複晶 矽側壁間隔層16’並被逐漸蝕刻掉，形成如圖所示殘餘的 複晶矽側壁間隔層16’’。 然後，請參照第3E圖，繼續蝕刻該裸露之基底表面’ (請先閱讀背面之注意事項再填寫本K ) 装. 訂31C463 A7 1 4 3 5 twf / M u I cl er H u / 0 0 2 B printed by the Employee Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. Fifth, the description of the invention (I) The surface_off_groove process, and in particular, there is a method for improving the shallow connection_isolating trench corners in the above process. The integration of integrated circuits is getting higher and higher. In the advanced VL SI process, up to hundreds of thousands of MOS transistors can be formed on the silicon surface with an area of 1 ~ 2cm2. The operation of the device will not be interfered by the other party. You must try to isolate each transistor to avoid short circuit. This process is called an isolation process. A conventional method of isolation process is to form a pad oxidation on the semiconductor substrate in sequence Layer and a silicon nitride layer, then a window is defined at the place where the shallow isolation trench is to be formed by the lithography process and etching technology. Then, using the silicon nitride layer as a mask, the window that exposes the surface of the substrate is etched under the substrate to form a shallow trench for isolation. The manufacturing process is described in detail in Figures 1A to 1C. Please first refer to FIG. 1A to provide a semiconductor substrate (), first form a pad oxide layer such as silicon dioxide layer 12 on the semiconductor substrate, and then form an insulating layer such as nitride sand layer 14 in ::: oxide sand layer h Then, using the lithography process and etching process to define a shallow junction isolation trench, define an opening 15 that exposes the surface of the substrate. Next, referring to FIG. 1B, using the silicon nitride layer 14 as an etching mask, the exposed substrate surface of the opening 15 is etched into the substrate to form a shallow junction isolation trench 15 '. Finally, referring to FIG. 1C, the silicon nitride layer 14 and the pad oxide layer 12 are sequentially removed to complete the fabrication of trenches for shallow junction isolation. Among them, because the edges and corners of the trenches for shallow joints are very sharp, the Chinese paper standard (CNS) A4 specification (210X297mm> 83. 3. 0,0〇〇- -----.--- Clothing— (please read the precautions on the back before filling in this page) Order the 3IG463 I 435twf / Mulder Hu / 〇〇2 of the Beigong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy V. Inventions Description (2) When a trench insulating material such as silicon dioxide is formed into the trench 16 to form a trench 21 with a shallow junction of insulating material to isolate the trench 21, a structure as reference number 19 in FIG. 2 is created, as compared to In other flat areas, the insulating layer at the corners will be thin, and the thinning of the transition area will cause double humps and parasitic electric fields during semiconductor operation. In view of this, the present invention Proposed-a kind of shallow junction isolation trench process to improve the problem of shallow junction isolation trench edge corners, the steps include: providing a semiconductor substrate; sequentially forming a pad oxide layer and an insulating layer on the substrate On; define the pad oxide layer and the optical lithography process and etching technology An insulating layer, and forming at least one opening exposing the surface of the semiconductor substrate; forming an etch buffer layer on the insulating layer and the opening sidewall and the exposed substrate surface; etching back the etch buffer layer to form a sidewall spacer layer The pad oxide layer of the opening and the side wall of the insulating layer; using the insulating layer as an etching mask, the exposed substrate surface of the opening is etched and etched along the outer side of the side wall spacer layer to form a shallow connection with a sliding edge Surface isolation trench, the sidewall spacer layer is gradually removed during the etching process; and the insulating layer and the pad oxide layer are sequentially removed to complete the fabrication of shallow junction isolation trenches with rounded corners. The above and other purposes, features, and advantages can be more clearly understood. The following is a preferred embodiment, and the drawings are described in detail as follows: A brief description of the drawings: Figures 1A ~ 1C are conventional A cross-section manufacturing flow chart of a shallow junction isolation trench. 4 (please read the precautions on the back before filling in this page) 袈. The size of the revised paper is applicable to China ’s national standard rate (CNS > A4 specification) (210X297mm) 83. 3.10,000 310463 I 43 5twf / Muldcr Hu / 002 Printed by the Beigong Consumer Cooperative of the Ministry of Economic Affairs of China. 5. Description of the invention (2) Figure 2 will be constructed as shown in Figure 1C Shallow junction isolation trenches after trench insulation. Figures 3A ~ 3F are flow charts for the fabrication of shallow junction isolation trench sections according to the present invention. Figure 4 is the construction of trench insulation as shown in Figure 3F. Isolation trenches after the shallow junction. Embodiments: First, please refer to FIG. 3A to provide a structure as shown in FIG. 1A, which includes a semiconductor substrate 10, a pad oxide layer 12, an insulating layer such as It is the silicon nitride layer 14, and then, a lithography process and an etching process are used to define a shallow junction isolation trench where an opening 15 is defined to expose the surface of the substrate. Next, please refer to FIG. 3B, an etching buffer layer 16 is formed on the insulating layer 14 and the sidewalls of the opening 15 and the base surface of the bottom; wherein, the touch buffer layer is deposited by low pressure chemical vapor deposition (LPCVD), for example The thickness of the polycrystalline silicon layer is about 300 ~ 500A »Then, referring to FIG. 3C, the buffer layer 16 is etched back, and a polycrystalline silicon sidewall spacer is formed on the sidewall of the pad oxide layer / silicon nitride layer of the opening 15 Floor 16 ,. Next, referring to FIG. 3D, using the silicon nitride layer 14 as a mask, gradually etch to the bare substrate surface to form a shallow junction trench II; wherein the polysilicon sidewall spacer 16 'is gradually etched away, A residual polysilicon sidewall spacer 16 '' as shown is formed. Then, please refer to Figure 3E, continue to etch the exposed substrate surface ’(please read the precautions on the back before filling in this K).
J 表紙張尺度適用中國國家樣率（CNS ) A4規格（210X297公釐） 83. 3. ! 〇,〇〇〇 A? f/Mulder Hu-O02 五、發明説明（f ) 形成· •淺接_隔離用溝槽丨7'，而側壁蝕刻緩衝層_已在 蝕刻過程中被去除· 然後，請參照第3F圖，依序去除氮化矽層14及墊氧 化層12，完成淺接面隔離用溝槽17’。 最後，請參照第4圖，在該半導體基底10表面形成另 一絕緣層例如是二氧化矽層2 0，並溝塡淺接面隔離用溝槽 17’，形成--溝塡有絕緣物質之淺接面隔離用溝槽22。 因本發明在蝕刻過程中更利用一側壁蝕刻緩衝層’可 使蝕刻時沿側壁之外型而蝕刻裸露之基底表面，形成· -11 滑的邊緣角落，不會造成後續絕緣層形成於其上時因其邊 緣角落過尖峭而有二次導通的情形，且此蝕刻緩衝層亦可 在蝕刻過程中逐漸被去除，不必再另次蝕刻去除，故其在 製程上亦極爲便利。 雖然本發明已以--較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 (請先閱讀背面之注意事項再填寫未頁) 、訂 經濟部中央標隼局員工消費合作社印繁 6 本紙張尺度適用中國國家標準（CNS ) A4規格（2丨〇Χ297公f )J sheet paper scale is applicable to China National Sample Rate (CNS) A4 specification (210X297 mm) 83. 3.! 〇, 〇〇〇A? F / Mulder Hu-O02 V. Description of invention (f) Formation · Shallow connection _ Isolation trench 丨 7 ', and the side wall etch buffer layer_ has been removed during the etching process. Then, referring to FIG. 3F, the silicon nitride layer 14 and the pad oxide layer 12 are sequentially removed to complete the shallow junction isolation Groove 17 '. Finally, referring to FIG. 4, another insulating layer, such as a silicon dioxide layer 20, is formed on the surface of the semiconductor substrate 10, and a trench 17 'for trench shallow junction isolation is formed to form a trench with an insulating substance Trench 22 for shallow junction isolation. Because the invention uses a side wall etching buffer layer during the etching process, the exposed substrate surface can be etched along the side wall profile during etching, forming a -11 slippery edge corner, which will not cause a subsequent insulating layer to be formed thereon When the edges and corners are too sharp, there is a secondary conduction, and the etching buffer layer can also be gradually removed during the etching process, and it is not necessary to etch and remove it again, so it is also very convenient in the manufacturing process. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Anyone who is familiar with this skill can make various changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be subject to the scope defined in the attached patent application. (Please read the precautions on the back and then fill in the unpaged pages). Order The printed and printed version of the Employee Consumer Cooperative of the Central Standard Falcon Bureau of the Ministry of Economic Affairs 6 This paper standard is applicable to the Chinese National Standard (CNS) A4 (2 丨 〇297297f)