TW202450417A - Semiconductor structure and method of manufacturing semiconductor structure - Google Patents

Abstract

A method of manufacturing a semiconductor structure includes a number of operations. A bottom electrode metal layer is formed over the substrate. The bottom electrode metal layer is etched to form a pillar bottom electrode over the substrate. A dielectric layer is formed over the pillar bottom electrode. A top electrode is formed over the dielectric layer. The pillar bottom electrode, the dielectric layer and the top electrode form a first capacitor.

Description

Semiconductor structure and method for manufacturing semiconductor structure

The present disclosure relates to semiconductor structures and methods of manufacturing semiconductor structures.

Capacitors can be used in a variety of semiconductor devices with different structures. For example, capacitors can be used in memory devices, such as dynamic random access memory devices. However, as the size of semiconductor devices shrinks, the key size of the capacitors used shrinks. When the height of the capacitor is increased, the capacitor is prone to tipping over, resulting in unexpected short circuits.

Therefore, how to provide a semiconductor structure and a corresponding manufacturing method that can make the formed capacitor have sufficient structural stability and avoid unexpected short circuits is one of the problems that technicians in the relevant field want to solve.

One aspect of the present disclosure relates to a method of manufacturing a semiconductor structure.

According to one or more embodiments of the present disclosure, a method for manufacturing a semiconductor structure includes multiple processes. A lower electrode metal layer is formed on a substrate. The lower electrode metal layer is etched to form a solid pillar lower electrode on the substrate. A dielectric layer is formed on the solid pillar lower electrode. An upper electrode is formed on the dielectric layer, wherein the solid pillar lower electrode, the dielectric layer and the upper electrode form a first capacitor.

In one or more embodiments of the present disclosure, etching the lower electrode metal layer further includes forming a mask aligned with the conductive pad on the lower electrode metal layer.

In some embodiments, the material of the bottom electrode metal layer is different from the material of the conductive pad.

In one or more embodiments of the present disclosure, the bottom surface of the solid column lower electrode has a first width, and the top surface of the solid column lower electrode relative to the bottom has a second width, and the second width is smaller than the first width.

In one or more embodiments of the present disclosure, the method for manufacturing a semiconductor structure further includes a plurality of processes. A second capacitor is formed. An intermediate dielectric layer is formed between the first capacitor and the second capacitor, wherein the intermediate dielectric layer has a trapezoidal cross-section between the first capacitor and the second capacitor, and a bottom side of the trapezoid that is flush with the bottom surface of the first capacitor is larger than a top side of the trapezoid that is opposite to the bottom side.

In some embodiments, the method of manufacturing a semiconductor structure further includes performing a planarization process so that a top surface of the first capacitor, a top surface of the second capacitor, and a top surface of the intermediate dielectric layer are coplanar.

One aspect of the present disclosure relates to a semiconductor structure.

According to one or more embodiments of the present disclosure, a semiconductor structure includes a substrate and a first capacitor located on the substrate. The first capacitor includes a solid pillar lower electrode, a dielectric layer, and an upper electrode. The solid pillar lower electrode is located on a conductive pad. The bottom surface of the solid pillar lower electrode on the conductive pad has a first width. The top surface of the solid pillar lower electrode relative to the bottom surface has a second width. The first width is greater than the second width. The dielectric layer is located on the solid pillar lower electrode. The upper electrode is located on the dielectric layer.

In one or more embodiments of the present disclosure, a total width of a first width of a bottom surface of the solid pillar lower electrode and a thickness of the dielectric layer is greater than a third width of the conductive pad.

In one or more embodiments of the present disclosure, the material of the solid post bottom electrode is different from the material of the conductive pad.

In one or more embodiments of the present disclosure, the semiconductor structure further includes a second capacitor and an intermediate dielectric layer. The second capacitor is located on the substrate. The intermediate dielectric layer surrounds the first capacitor and the second capacitor. The intermediate dielectric layer has a trapezoidal cross-section between the first capacitor and the second capacitor. The bottom side of the trapezoid aligned with the bottom surface of the first capacitor is larger than the top side of the trapezoid opposite to the bottom side.

In summary, the lower electrode of the capacitor is formed by first forming a lower electrode metal layer and etching it, and the dielectric layer and the upper electrode of the capacitor are filled in after the lower electrode metal layer is etched, so that a capacitor with a narrow upper part and a wide lower part can be formed, thereby increasing the structural stability of the capacitor and preventing the capacitor from tipping over and causing an unexpected short circuit.

The above description is only used to explain the problem to be solved by the present disclosure, the technical means for solving the problem, and the effects produced, etc. The specific details of the present disclosure will be introduced in detail in the following implementation method and related drawings.

The following is a detailed description with reference to the embodiments and the attached drawings, but the embodiments provided are not intended to limit the scope of the disclosure, and the description of the structure operation is not intended to limit the order of its execution. Any device with equal functions produced by the re-combination of components is within the scope of the disclosure. In addition, the drawings are for the purpose of description only and are not drawn according to the original size. For ease of understanding, the same or similar components in the following description will be indicated by the same symbols.

In addition, the terms used throughout the specification and the patent application generally have the ordinary meaning of each term used in this field, in the context of this disclosure, and in the specific context, unless otherwise specified. Certain terms used to describe the present disclosure will be discussed below or elsewhere in this specification to provide additional guidance to those skilled in the art in describing the present disclosure.

In this document, the terms “first”, “second”, etc. are only used to distinguish elements or operating methods with the same technical terminology, and are not intended to indicate an order or to limit the present disclosure.

In addition, the terms "include", "including", "provide" and similar terms are open-ended limitations in this document, meaning including but not limited to.

Furthermore, in this document, unless the context specifically limits the articles, "a", "an" and "the" may refer to one or more. It will be further understood that "include", "comprises", "have" and similar terms used in this document specify the features, regions, integers, steps, operations, elements and/or components described therein, but do not exclude the described or additional one or more other features, regions, integers, steps, operations, elements, components, and/or groups thereof.

Capacitors can be used in a variety of different semiconductor devices. For example, capacitors can be used in semiconductor memory devices, and capacitors can be connected to transistors to form memory cells to store information. However, as the size of components in semiconductor devices decreases, the key size of the capacitors formed will also decrease. Capacitors with reduced sizes will easily fall over, causing multiple adjacent capacitors to unexpectedly contact each other and cause short circuits. In one or more embodiments of the present disclosure, a capacitor with a shape that is wider at the bottom and narrower at the top can be formed, so that the bottom of the capacitor has a larger width than the top of the capacitor, making the structure of the capacitor stable and not easily collapsed, thereby improving the electrical properties of the overall structure.

Please refer to Figures 1 to 7. Figures 1 to 7 are schematic cross-sectional views of multiple processes of a method for manufacturing a semiconductor structure 100 according to one or more embodiments disclosed herein.

Please refer to FIG. 1 first. In the intermediate process shown in FIG. 1, a substrate 101 is provided. By way of example but not limitation. In some embodiments, the substrate 101 may include a semiconductor substrate, such as a silicon substrate. For the purpose of convenience of explanation, the substrate 101 shown in FIG. 1 collectively summarizes the semiconductor substrate and one or more semiconductor layers formed on the semiconductor substrate. In the embodiment shown in FIG. 1, the one or more semiconductor layers formed on the semiconductor substrate include a dielectric layer 105. In some embodiments, the material of the dielectric layer 105 may include a semiconductor oxide, such as silicon oxide.

In FIG. 1 , the dielectric layer 105 includes a top surface 105T. The top surface 105T extends in a direction x. In one or more embodiments of the present disclosure, as shown in FIG. 1 , the substrate 101 includes one or more conductive pads 110. The one or more conductive pads 110 are disposed on the top surface 105T of the dielectric layer 105. In this embodiment, as shown in FIG. 1 , a plurality of conductive pads 110 are embedded into the dielectric layer 105 from the top surface 105T of the dielectric layer 105. In some embodiments, the conductive pads 110 may be disposed on the top surface 105T of the dielectric layer 105 and protrude from the top surface 105T.

In one or more embodiments of the present disclosure, the conductive pad 110 may include a conductive material. For example but not limitation, in some embodiments, the conductive pad 110 may include tungsten metal.

In one or more embodiments of the present disclosure, the plurality of conductive pads 110 may be configured to connect to one or more semiconductor elements in the substrate 101. For example but not limitation, in one or more embodiments of the present disclosure, the plurality of conductive pads 110 may be configured to connect to one or more transistors in the semiconductor substrate, respectively, to be subsequently connected to a capacitor to form a memory cell for storing information. For the purpose of convenience of explanation, one or more semiconductor elements are not shown in the figure.

Please refer to Figure 2 and Figure 8. Figure 8 is a flow chart of a method 200 for manufacturing a semiconductor structure 100 according to one or more embodiments of the present disclosure.

In process 201 of method 200, a lower electrode metal layer 115 is formed on substrate 101. As shown in FIG. 2, in process 201, the lower electrode metal layer 115 is formed to cover the top surface 105T of the dielectric layer 105 and one or more conductive pads 110 exposed from the top surface 105T of the dielectric layer 105. In some embodiments, the lower electrode metal layer 115 can be formed on the top surface 105T of the dielectric layer 105 by a deposition process.

In one or more embodiments of the present disclosure, the lower electrode metal layer 115 is a conductive material, and the lower electrode metal layer 115 may include a composite conductive material. For example but not limited thereto. In one or more embodiments of the present disclosure, the lower electrode metal layer 115 may include titanium nitride (TiN) or titanium silicon nitride (TiSiN). The material of the lower electrode metal layer 115 may be the same as or different from the material of the conductive pad 110. In the embodiment where the material of the lower electrode metal layer 115 is different from the material of the conductive pad 110, the lower electrode metal layer 115 and the conductive pad 110 can have a large etching selectivity by selecting the materials of the conductive pad 110 and the lower electrode metal layer 115 and designing the etchant. Please refer to the following description for details.

Following process 201, in process 202, the lower electrode metal layer 115 is etched to form a plurality of lower electrode plates 130 on a plurality of conductive pads 110 of the substrate 101. Please refer to FIG. 3 and FIG. 4 in sequence. In one or more embodiments of the present disclosure, the lower electrode metal layer 115 can be etched by forming a mask 120.

Please refer to the intermediate process shown in FIG. 3. As shown in FIG. 3, a mask 120 is formed on the lower electrode metal layer 115. The mask 120 is patterned to retain a portion aligned with the plurality of conductive pads 110. In some embodiments, by way of example but not limitation, the mask 120 is a photoresist layer. In the embodiment shown in FIG. 3, the width of each portion of the plurality of masks 120 aligned with the plurality of conductive pads 110 in the direction x is less than the width W1 of the conductive pads 110 in the direction x.

Please refer to FIG. 4. In the middle process shown in FIG. 4, a selective etching process EP is performed through a patterned mask 120 to form a plurality of solid lower pillar electrode plates 130 aligned with a plurality of conductive pads 110. In the embodiment shown in FIG. 4, the selective etching process EP etches the lower electrode metal layer 115 from top to bottom along the direction y. Since the etching intensity decreases from top to bottom, the plurality of solid lower pillar electrode plates 130 formed have a shape of being narrow at the top and wide at the bottom. In other words, as shown in FIG. 4, in the direction y, the solid lower pillar electrode plate 130 has a top surface 130T and a bottom surface 130B opposite to each other. The bottom surface 130B of the solid lower column electrode plate 130 has a width W2 in the direction x. The top surface 130T of the solid lower column electrode plate 130 has a width W3 in the direction x. The width W3 of the top surface 130T of the solid lower column electrode plate 130 is smaller than the width W2 of the bottom surface 130B of the solid lower column electrode plate 130.

As shown in FIG. 4 , the width W3 of the top surface of the lower electrode plate 130 and the patterned portion of the mask 120 have the same width W3 in the direction x.

In the embodiment shown in FIG. 4 , the width W2 of the bottom surface 130B of the solid lower column electrode plate 130 is substantially equal to the width W1 of the conductive pad 110. In one or more embodiments of the present disclosure, the width W2 of the bottom surface 130B of the solid lower column electrode plate 130 is less than or equal to the width W1 of the conductive pad 110 to avoid unintended contact between adjacent solid lower column electrode plates 130. In some embodiments, the solid lower column electrode plate 130 may be larger than the conductive pad 110, but appropriate gaps must still be reserved between multiple solid lower column electrode plates 130 to avoid unintended contact between subsequently formed structures.

As shown in FIG. 4 , in this embodiment, the bottom surface 130B of the solid lower column electrode plate 130 directly contacts the conductive pad 110. In one or more embodiments of the present disclosure, the bottom surface 130B of the solid lower column electrode plate 130 may completely or incompletely cover the top surface of the conductive pad 110. In the embodiment where the solid lower column electrode plate 130 does not completely cover the top surface of the conductive pad 110, the width W2 of the bottom surface of the solid lower column electrode plate 130 corresponding to the direction x is smaller than the width W1 of the conductive pad 110. Since the solid lower electrode plate 130 is formed by performing a selective etching process EP, when the formed solid lower electrode plate 130 is designed to not completely cover the top surface of the conductive pad 110, the conductive pad 110 will be exposed at the side of the bottom surface 130B of the solid lower electrode plate 130, resulting in the selective etching process EP also being able to etch the conductive pad 110. In one or more embodiments of the present disclosure, the conductive pad 110 and the solid lower pillar electrode plate 130 can be made of different materials, and the selective etching process EP can be selected to use an etchant with a high etching selectivity ratio between the material of the solid lower pillar electrode plate 130 and the material of the conductive pad 110. This can reduce the etching amount of the conductive pad 110 by the etching process EP as much as possible when etching the lower electrode metal layer 115 to form the solid lower pillar electrode plate 130, thereby avoiding damage to the conductive pad 110.

Please refer to FIG. 8 . Following process 202 , in process 203 , a dielectric layer 140 is formed on the lower electrode plate 130 .

Please refer to the schematic diagram of the intermediate process cross section shown in Figure 5. The dielectric layer 140 is formed on the side wall 130SW between the opposite bottom surface 130B and the top surface 130T connected to the lower electrode plate 130. The dielectric layer 140 laterally surrounds the solid pillar lower electrode plate 130. The patterned mask 120 is removed. In one or more embodiments of the present disclosure, the dielectric layer 140 is a high-k dielectric material. By way of example but not limitation, in some embodiments, the high-k dielectric layer 140 may include a metal oxide or a metal nitride, such as silicon dioxide, silicon nitride and/or barium dioxide.

In some embodiments, the dielectric layer 140 may be formed on the solid pillar lower electrode plate 130 by a deposition process. For example but not limited thereto, in one or more embodiments of the present disclosure, after the solid pillar lower electrode plate 130 is formed in process 202, in process 203, the dielectric layer 140 may be conformally deposited on the solid pillar lower electrode plate 130 and the exposed top surface 105T of the dielectric layer 105, so that the top surface 130T and the sidewall 130SW of the solid pillar lower electrode plate 130 and the top surface 105T of the dielectric layer 105 are covered by the dielectric layer 140. In some embodiments, in the embodiment where the width of the bottom surface 130B of the solid pillar lower electrode plate 130 is smaller than the width W1 of the conductive pad 110, the conductive pad 110 exposed on the top surface 105T is also covered by the dielectric layer 140. After the dielectric layer 140 is conformally formed to cover the solid pillar lower electrode plate 130 and the dielectric layer 105, the dielectric layer 140 can be etched (e.g., anisotropic etching in which the etching speed in the vertical direction is greater than the etching speed in the horizontal direction) so that the dielectric layer 140 is only retained on the sidewall 130SW of the solid pillar lower electrode plate 130, as shown in FIG. 5 .

In some implementations, after the dielectric layer 140 is conformally deposited on the solid pillar lower electrode plate 130 and the dielectric layer 105, the dielectric layer 140 may not be etched first, as shown in FIG. 9 . Please refer to the subsequent description for details.

Please refer to FIG. 8. In process 204, an upper electrode plate 150 is formed on the dielectric layer 140 to form a plurality of columnar capacitors C1, C2 and C3.

In the schematic diagram of the intermediate process cross section shown in FIG. 6 , the upper electrode plate 150 is formed on the dielectric layer 140, and the upper electrode plate 150 surrounds the dielectric layer 140 and the solid pillar lower electrode plate 130. In one or more embodiments of the present disclosure, the material of the upper electrode plate 150 may include the same or different conductive material as the lower electrode plate 130. In some embodiments, the material of the upper electrode plate 150 may include the same or different conductive material as the conductive pad 110. In some embodiments of the present disclosure, by way of example but not limitation, the material of the upper electrode plate 150 may include titanium nitride or titanium silicon nitride.

In one or more embodiments of the present disclosure, by way of example but not limitation, the upper electrode plate 150 may be formed on the dielectric layer 140 by a deposition process. By way of example but not limitation, after the dielectric layer 140 is formed on the sidewall 130SW of the solid pillar lower electrode plate 130 in process 203, in process 204, an upper electrode metal layer for forming the upper electrode plate 150 may be conformally deposited to cover the top surface 105T of the dielectric layer 105, the dielectric layer 140, and the top surface 130T of the solid pillar lower electrode plate 130. Subsequently, the upper electrode metal layer may be etched (eg, anisotropic etching in which the etching speed in the vertical direction is greater than the etching speed in the horizontal direction) so that the upper electrode metal layer is only retained on the inclined dielectric layer 140 and serves as an upper electrode plate 150 as shown in FIG. 6 .

In this way, a set of solid columnar lower electrode plates 130, dielectric layer 140 surrounding solid columnar lower electrode plates 130, and upper electrode plate 150 can form a columnar capacitor. In the embodiment shown in FIG. 6, columnar capacitors C1, C2, and C3 are formed on the top surface 105T of dielectric layer 105, and columnar capacitors C1, C2, and C3 are arranged along direction x on the top surface 105T. For one of the columnar capacitors C1, C2, and C3, the solid columnar lower electrode plate 130 can be used as the lower electrode of the capacitor, the upper electrode plate 150 can be used as the upper electrode of the capacitor, and the dielectric layer 140 is disposed between the lower electrode and the upper electrode to separate the upper electrode and the lower electrode. In this way, the upper electrode and the lower electrode can store charge as a capacitor. The high dielectric constant dielectric layer 140 can increase the capacitance value of the columnar capacitors C1, C2, and C3.

Please refer to FIG. 5 and FIG. 6 at the same time. In FIG. 6, the bottom surfaces of the solid pillar lower electrode plate 130, the dielectric layer 140 and the upper electrode plate 150 are coplanar on the top surface 105T of the dielectric layer 105. In FIG. 5, after the dielectric layer 140 is formed on the solid pillar lower electrode plate 130, the thickness of the dielectric layer 140 and the width W2 of the bottom surface 130B of the solid pillar lower electrode plate 130 in the direction x have a total width W4, and the total width W4 of the thickness of the dielectric layer 140 and the width W4 of the bottom surface 130B of the solid pillar lower electrode plate 130 in the direction x is greater than the width W1 of the conductive pad 110. In one or more embodiments of the present disclosure, the combined width W4 of the dielectric layer 140 and the bottom surface 130B of the solid pillar lower electrode plate 130 in the direction x is greater than or equal to the width W1 of the conductive pad 110, so that the bottom surface of the upper electrode plate 150 in FIG. 6 can exceed the top surface of the conductive pad 110, thereby preventing the upper electrode plate 150 and the solid pillar lower electrode plate 130 from contacting the conductive pad 110 at the same time.

As shown in FIG. 6 , in one or more embodiments of the present disclosure, the bottom surface of each columnar capacitor C1, columnar capacitor C2, and columnar capacitor C3 has a width W5 in direction x, and the width W2 is greater than the width W1 of the conductive pad 110. The top of each columnar capacitor C1, columnar capacitor C2, and columnar capacitor C3 has a width W6 in direction x, and the width W6 is less than the width W5, so that each columnar capacitor C1, columnar capacitor C2, and columnar capacitor C3 has a shape that is narrow at the top and wide at the bottom. The shape that is narrow at the top and wide at the bottom can increase the structural strength of the columnar capacitors C1, columnar capacitors C2, and columnar capacitors C3. When the columnar capacitors C1, C2, and C3 are formed in a semiconductor device with a critical small size, the narrow-at-top-and-wide-at-bottom shape can ensure that the columnar capacitors C1, C2, and C3 have sufficient structural strength to prevent the columnar capacitors C1, C2, and C3 from unexpectedly tipping over and short-circuiting with adjacent columnar capacitors.

Please refer to FIG. 7 and FIG. 8. As shown in the schematic cross-sectional view of the intermediate process shown in FIG. 7, in process 205 of method 200, an intermediate dielectric layer 160 is formed between a plurality of columnar capacitors C1, C2, and C3. The intermediate dielectric layer 160 fills the gaps between the columnar capacitors C1, C2, and C3, thereby substantially laterally surrounding the columnar capacitors C1, C2, and C3.

In one or more embodiments of the present disclosure, the columnar capacitors C1, C2, and C3 are all narrow at the top and wide at the bottom in the direction y, so that the shape of the intermediate dielectric layer 160 between the columnar capacitors C1, C2, and C3 is a trapezoid in the cross section shown in FIG. 7. As shown in FIG. 7, the intermediate dielectric layer 160 between the columnar capacitors C2 and C3 is a trapezoid and has a bottom side with a width of W7 and a top side with a width of W8. The bottom side with a width of W7 is flush with the bottom surfaces of the columnar capacitors C1, C2, and C3. The top of width W8 is flush with the tops of columnar capacitors C1, C2, and C3, and the top of width W8 is relative to the bottom of width W7 in direction y, and width W7 is smaller than width W8. In other words, in the cross section shown in FIG. 7, the intermediate dielectric layer 160 between the two most adjacent columnar capacitors (e.g., columnar capacitors C2 and C3) is a trapezoid that is wide at the top and narrow at the bottom. Width W7 also corresponds to the spacing between adjacent columnar capacitors (e.g., columnar capacitors C2 and C3). In some embodiments, columnar capacitors C1, C2, and C3 are arranged at equal spacing from each other.

In one or more embodiments of the present disclosure, the formed columnar capacitors C1, C2, and C3 can be connected to semiconductor devices in the substrate 101 through corresponding conductive pads 110. For example, the conductive pads 110 can be connected to transistors located in the substrate 101, respectively, and multiple transistors and multiple columnar capacitors C1, C2, and C3 can form multiple 1-transistor-1-capacitor (1T1C) memory cells for DRAM devices.

In one or more embodiments of the present disclosure, in order to avoid unexpected parasitic capacitance effects, the intermediate dielectric layer 160 may be formed of a dielectric material with a low dielectric constant. In other words, in some embodiments of the present disclosure, the dielectric constant of the intermediate dielectric layer 160 may be less than the dielectric constant of the dielectric layer 140. By way of example but not limitation, in one or more embodiments of the present disclosure, the intermediate dielectric layer 160 may include polysilicon. In one or more embodiments of the present disclosure, the intermediate dielectric layer 160 may be formed on the top surface 105T of the dielectric layer 105, the columnar capacitor C1, the columnar capacitor C2, and the columnar capacitor C3 by a deposition process.

In some embodiments of the present disclosure, after the formation of the interlayer dielectric layer 160, a further polishing or planarization process (such as but not limited to a chemical planarization process) may be performed to make the top surfaces of the solid pillar lower electrode plate 130, the dielectric layer 140, the upper electrode plate 150, and the interlayer dielectric layer 160 coplanar. In other words, after performing a further polishing or planarization process, the top surfaces of the interlayer dielectric layer 160, the columnar capacitors C1, C2, and C3 are coplanar with each other.

Please refer to Fig. 9. Fig. 9 is a schematic cross-sectional view of a semiconductor structure 100' according to one or more embodiments of the present disclosure.

The semiconductor structure 100' of FIG. 9 is different from the semiconductor structure 100 of FIG. 7 in that the semiconductor structure 100' further includes a dielectric layer 141 extending along the direction x on the top surface 105T of the dielectric layer 105. In the cross section shown in FIG. 9, the dielectric layers 140 and 141 of the semiconductor structure 100' form a U-shape between adjacent ones of the columnar capacitors C1', C2', and C3'. The dielectric layer 141 and the dielectric layer 140 can be considered to be the same dielectric layer. In other words, the dielectric layer 141 and the dielectric layer 140 can be conformally formed on the solid pillar lower electrode plate 130 and the top surface 105T of the dielectric layer 105 in the same semiconductor deposition process. For the purpose of convenience of explanation, they are marked as different blocks, but this should not excessively limit the present disclosure.

The semiconductor structure 100' can be formed by the method 200 shown in FIG8. Similar to the process 203 of forming the semiconductor structure 100, please refer to FIG9, for the semiconductor structure 100', a high dielectric constant dielectric layer is conformally deposited on the top surface 130T and the sidewall 130SW of the solid pillar lower electrode plate 130 and the top surface 105T of the dielectric layer 105, but no further etching is performed. Subsequently, an upper electrode metal layer used as an upper electrode plate 150 is formed on the dielectric layer that conformally covers the solid pillar lower electrode plate 130 and the high dielectric constant, and the upper electrode metal layer is etched into an upper electrode plate 150 that only surrounds one of the plurality of solid pillar lower electrode plates 130 corresponding to different solid pillar lower electrode plates 130. After the upper electrode plate 150 is formed, an intermediate dielectric layer 160 is formed on the high dielectric constant dielectric layer and fills the gap between the upper electrode plates 150. Subsequently, a polishing process or a planarization process is performed to form an exposed top surface 130T of the solid pillar lower electrode plate 130. The high-k dielectric layer on the exposed top surface 130T of the solid pillar lower electrode plate 130 is removed during a polishing process or a planarization process.

As a result, as shown in FIG. 9 , the high-k dielectric layer is only retained in the dielectric layer 140 on the sidewall 130SW of the solid pillar lower electrode plate 130 and the dielectric layer 141 extending along the direction x on the dielectric layer 105. The solid pillar lower electrode plate 130 and the upper electrode plate 150 are separated by the dielectric layer 140. Multiple sets of solid pillar lower electrode plates 130, the dielectric layer 140 surrounding the solid pillar lower electrode plate 130, and the upper electrode plate 150 surrounding the dielectric layer 140 form a pillar capacitor C1′, a pillar capacitor C2′, and a pillar capacitor C3′. The dielectric layers 140 of different columnar capacitors C1′, C2′, and C3′ are connected to each other through a dielectric layer 141 extending along the direction x on the dielectric layer 105. In other words, the columnar capacitors C1′, C2′, and C3′ can be considered to share the same dielectric layer 140 and dielectric layer 141. In the cross section shown in FIG. 9, the dielectric layer 140 and dielectric layer 141 between the two most adjacent solid column bottom electrode plates 130 in the direction x are connected to each other to form a U shape.

As shown in FIG. 9 , the conductive pad 110 has a width W1 in the direction x, and the bottom surface 130B of the solid lower column electrode plate 130 has a width W2 in the direction x. In the embodiment shown in FIG. 9 , the width W1 of the conductive pad 110 is equal to the width W2 of the solid lower column electrode plate 130. In one or more embodiments of the present disclosure, the width W2 of the solid lower column electrode plate 130 is less than or equal to the width W1 of the conductive pad 110. In the embodiment where the width W2 of the solid column lower electrode plate 130 is smaller than the width W1 of the conductive pad 110, since the dielectric layer 141 extends between two adjacent solid column lower electrode plates 130, it is possible to ensure that the solid column lower electrode plate 130 serving as the lower electrode and the upper electrode plate 150 serving as the upper electrode are separated from each other to form a columnar capacitor.

In the embodiment shown in FIG. 9 , since the solid column lower electrode plate 130 has a shape that is narrow at the top and wide at the bottom in the direction y, it can have a certain degree of structure. Since the dielectric layer 141 can cover the conductive pad 110 that the solid column lower electrode plate 130 fails to cover, the width W2 of the bottom surface 130B of the solid column lower electrode plate 130 can be reduced, which is beneficial to reducing the key size of the overall structure.

In summary, in one or more embodiments of the present disclosure, the lower electrode plate of the capacitor can be formed by first forming the lower electrode metal layer and etching it, and the dielectric layer and the upper electrode plate of the capacitor are filled in after the lower electrode metal layer is etched, so that a capacitor with a narrow upper and wide lower shape can be formed. The capacitor shape with a narrow upper and wide lower shape can increase the structural stability of the capacitor and avoid the problem of the capacitor tipping over.

Although the present disclosure has been disclosed in the above implementation form, it is not intended to limit the present disclosure. Any person with ordinary knowledge in the field can make various changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be defined by the scope of the attached patent application.

It is obvious to those skilled in the art that various modifications and variations can be made to the structure of the embodiments of the present disclosure without departing from the scope or spirit of the present disclosure. In view of the foregoing, the present disclosure is intended to cover modifications and variations of the present invention as long as they fall within the scope of the attached protection.

100,100’: semiconductor structure 101: substrate 105: dielectric layer 105T: top surface 110: conductive pad 115: lower electrode metal layer 120: mask 130: lower electrode plate 130B: bottom surface 130T: top surface 130SW: sidewall 140: dielectric layer 141: dielectric layer 150: upper electrode plate 160: intermediate dielectric layer 200: method 201~205: process C1,C2,C3: capacitor C1’,C2’,C3’: capacitor EP: etching process W1,W2,W3,W4,W5,W6,W7,W8: width x,y: direction

The advantages and figures of the present disclosure should be better understood by referring to the following embodiments and the accompanying drawings. The description of these drawings is only an enumerated embodiment, and therefore should not be considered to limit the individual embodiments or the scope of the invention patent application. Figures 1 to 7 are schematic diagrams of multiple intermediate cross-sections of multiple processes of a method for manufacturing a semiconductor structure according to one or more embodiments of the present disclosure; Figure 8 is a flow chart of a method for manufacturing a semiconductor structure according to one or more embodiments of the present disclosure; and Figure 9 is a schematic cross-sectional diagram of a semiconductor structure according to one or more embodiments of the present disclosure.

Domestic storage information (please note in the order of storage institution, date, and number) None Foreign storage information (please note in the order of storage country, institution, date, and number) None

100:Semiconductor structure

101: Substrate

105: Substrate

105T: Top

110: Conductive pad

130: Lower electrode plate

140: Dielectric layer

150: Upper electrode plate

160: Intermediate dielectric layer

C1,C2,C3:Capacitors

W7,W8: Width

x,y: direction

Claims (10)

A method for manufacturing a semiconductor structure, comprising: forming a lower electrode metal layer on a substrate; etching the lower electrode metal layer to form a solid pillar lower electrode on the substrate; forming a dielectric layer on the solid pillar lower electrode; and forming an upper electrode on the dielectric layer, wherein the solid pillar lower electrode, the dielectric layer and the upper electrode form a first capacitor. The method as described in claim 1, wherein etching the lower electrode metal layer further includes forming a mask on the lower electrode metal layer aligned with a conductive pad of the substrate. The method as described in claim 2, wherein the material of the lower electrode metal layer is different from the material of the conductive pad. A method as described in claim 1, wherein a bottom surface of the solid column lower electrode has a first width, and a top surface of the solid column lower electrode opposite to the bottom surface has a second width, and the second width is smaller than the first width. The method as described in claim 1 further includes: forming a second capacitor; and forming an intermediate dielectric layer between the first capacitor and the second capacitor, wherein the intermediate dielectric layer has a trapezoidal shape in a cross section between the first capacitor and the second capacitor, and a bottom side of the trapezoid aligned with a bottom surface of the first capacitor is larger than a top side of the trapezoid opposite to the bottom side. The method as described in claim 5 further includes: Performing a planarization process so that a top surface of the first capacitor, a top surface of the second capacitor and a top surface of the intermediate dielectric layer are coplanar. A semiconductor structure comprises: A substrate comprising a conductive pad; and A first capacitor located on the conductive pad of the substrate, wherein the first capacitor comprises: A solid column lower electrode located on the conductive pad, wherein a bottom surface of the solid column lower electrode on the conductive pad has a first width, and a top surface of the solid column lower electrode opposite to the bottom surface has a second width, and the first width is greater than the second width; A dielectric layer located on the solid column lower electrode; and An upper electrode located on the dielectric layer. A semiconductor structure as described in claim 7, wherein a combined width of the first width of the bottom surface of the solid pillar lower electrode and a thickness of the dielectric layer is greater than a third width of the conductive pad. A semiconductor structure as described in claim 7, wherein a material of the electrode under the solid pillar is different from a material of the conductive pad. The semiconductor structure as described in claim 7 further comprises: a second capacitor located on the substrate; and an intermediate dielectric layer surrounding the first capacitor and the second capacitor, wherein the intermediate dielectric layer has a trapezoidal shape in a cross section between the first capacitor and the second capacitor, and a bottom side of the trapezoid aligned with a bottom surface of the first capacitor is larger than a top side of the trapezoid opposite to the bottom side.

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