TW202449881A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

A semiconductor device includes a contact layer, a first supporting layer, a plurality of bottom electrode layers, a second supporting layer, a third supporting layer, and a fourth supporting layer. The first supporting layer is on the contact layer. Each of the bottom electrode layers includes a first portion and a second portion. The second portion is on the first portion and is narrower than the first portion. The second supporting layer is in contact with the first portion of each of the bottom electrode layers. The third supporting layer is over the second supporting layer and in contact with the first portion of each of the bottom electrode layers. The fourth supporting layer is over the third supporting layer and in contact with the second portion of each of the bottom electrode layers. The top of the first portion of each of the bottom electrode layers is higher than the third supporting layer.

Description

Semiconductor device and method for manufacturing the same

Some embodiments of the present disclosure relate to semiconductor devices and methods of making the same.

Capacitor structures are often used in memory structures. When the memory structure is operating, the surface of the electrode layer of the capacitor structure will distribute charges, so the shape and contour of the electrode layer of the capacitor structure can determine the amount of charge distributed on the surface of the electrode layer of the capacitor structure. When the shape of the electrode layer of the capacitor structure is more complete, the amount of charge distributed on the surface of the electrode layer of the capacitor structure increases, so a higher capacitance can also be obtained.

Some embodiments of the present disclosure provide a semiconductor device, including a contact layer, a first supporting layer, a plurality of lower electrode layers, a second supporting layer, a third supporting layer, and a fourth supporting layer. The contact layer includes a contact plug. The first supporting layer is on the contact layer. The lower electrode layer is on the first supporting layer, wherein any of the lower electrode layers includes a first portion and a second portion, wherein the second portion is on the first portion and is narrower than the first portion. The second supporting layer contacts the first portion of any of the lower electrode layers. The third supporting layer is on the second supporting layer and contacts the first portion of any of the lower electrode layers. The fourth supporting layer is on the third supporting layer and contacts the second portion of any one of the lower electrode layers, wherein the top of the first portion of any one of the lower electrode layers is higher than the third supporting layer.

In some embodiments, a top of the first portion of any one of the lower electrode layers is flush with a bottom of the fourth supporting layer.

In some embodiments, a top portion of the first portion of any one of the lower electrode layers is lower than the fourth supporting layer.

In some embodiments, the lower electrode layer is directly above the contact plug of the contact layer.

In some embodiments, the top portions of the lower electrode layer are flush with the top portion of the fourth supporting layer.

Some embodiments of the present disclosure provide a method for manufacturing a semiconductor device, including providing a contact layer, wherein the contact layer includes a plurality of contact plugs, forming a multi-layer structure on the contact layer, the multi-layer structure including a first supporting layer, a first sacrificial material layer, a second supporting layer, a second sacrificial material layer, a third supporting layer, a third sacrificial material layer and a fourth supporting layer stacked from bottom to top, forming a plurality of first trenches in the multi-layer structure, wherein a plurality of bottoms of the first trenches expose the contact layer, and the first trenches are connected to the multi-layer structure. A lower electrode material layer is formed in the groove, a hard mask layer is formed on the lower electrode material layer, the hard mask layer is used as an etching mask, a second trench is formed in the multi-layer structure, the lower electrode material layer is partially etched, and the bottom of the second trench is higher than the third supporting layer, the third sacrificial material layer is removed, the hard mask layer and the lower electrode material layer are used as etching masks, the third supporting layer is etched back, the second sacrificial material layer is removed, the hard mask layer and the lower electrode material layer are used as etching masks, the second supporting layer is etched back, and the first sacrificial material layer is removed.

In some embodiments, the thickness of the hard mask layer is 3 to 12 times the thickness of the third support layer.

In some embodiments, the bottom of the second trench is lower than the bottom of the fourth supporting layer.

In some embodiments, when the second trench is formed, the second trench is wider than any of the first trenches.

In some embodiments, the hard mask layer is completely removed when etching back the second support layer.

In some embodiments of the present disclosure, the lower electrode layer of the capacitor structure may be less etched. As a result, the capacitor structure of the present disclosure may accommodate more charges and thus may include more capacitance.

The following will disclose multiple embodiments of the present disclosure with drawings. For the purpose of clarity, many practical details will be described together in the following description. However, it should be understood that these practical details should not be used to limit the present disclosure. In other words, in some embodiments of the present disclosure, these practical details are not necessary. In addition, in order to simplify the drawings, some commonly used structures and components will be depicted in the drawings in a simple schematic manner.

In some embodiments of the present disclosure, the lower electrode layer of the capacitor structure may be less etched. As a result, the capacitor structure of the present disclosure may accommodate more charges and thus may include more capacitance.

FIG. 1 to FIG. 13A are cross-sectional views of the manufacturing process of the semiconductor device 100 according to some embodiments of the present disclosure. Referring to FIG. 1, a contact layer 110 is provided, wherein the contact layer 110 includes a plurality of contact plugs 112 and a dielectric layer 114. The contact plugs 112 are arranged in the dielectric layer 114. The contact plugs 112 are made of a conductor, and the dielectric layer 114 is made of a dielectric. In some embodiments, the contact plugs 112 are made of a metal, such as tungsten, and the dielectric layer 114 is made of a nitride. The contact layer 110 may include an array region R1 and a peripheral region R2, and the contact plugs 112 are only arranged in the array region R1 of the contact layer 110.

2 , a multi-layer structure 120 is formed on the contact layer 110 , and the multi-layer structure 120 includes a first supporting layer 122 , a first sacrificial material layer 124 , a second supporting layer 126 , a second sacrificial material layer 128 , a third supporting layer 132 , a third sacrificial material layer 134 and a fourth supporting layer 136 stacked from bottom to top. Specifically, the first supporting layer 122, the second supporting layer 126, the third supporting layer 132 and the fourth supporting layer 136 are used as supporting materials for the lower electrode layer to be formed later, and the first supporting layer 122, the second supporting layer 126, the third supporting layer 132 and the fourth supporting layer 136 are formed of nitride. The first sacrificial material layer 124, the second sacrificial material layer 128 and the third sacrificial material layer 134 are formed of oxide. In some embodiments, the second sacrificial material layer 128 and the third sacrificial material layer 134 are formed of tetraethoxysilane (TEOS), and the first sacrificial material layer 124 is formed of borophosphosilicate glass (BPSG).

Referring to FIG. 3 , a plurality of first trenches T1 are formed in the multi-layer structure 120, wherein the bottom of the first trenches T1 exposes the contact layer 110. Specifically, a hard mask layer may be formed on the multi-layer structure 120, and then the hard mask layer may be patterned using a photolithography process, and then the multi-layer structure 120 may be etched using the hard mask layer as a mask to form the first trenches T1 in the multi-layer structure 120. After the first trenches T1 are formed, the hard mask layer may be removed. The bottom of the first trench T1 is located directly above the contact plug 112 of the contact layer 110.

Referring to FIG. 4 , a lower electrode material layer 142 is formed on the multi-layer structure 120 and in the first trench T1. The lower electrode material layer 142 may completely cover the multi-layer structure 120 and fill the first trench T1. Specifically, the lower electrode material layer 142 may be formed by any suitable method, such as physical vapor deposition, chemical vapor deposition, atomic layer deposition, or the like. Since the lower electrode material layer 142 is filled in the first trench T1, a portion of the lower electrode material layer 142 is also located directly above the contact plug 112 of the contact layer 110. In some embodiments, the lower electrode material layer 142 is titanium silicon nitride (TiSiN), but the material of the lower electrode material layer 142 is not limited thereto.

Referring to FIG. 5 , a hard mask layer 150 is formed on the lower electrode material layer 142. The hard mask layer 150 can completely cover the lower electrode material layer 142. The thickness W1 of the hard mask layer 150 is 3 to 12 times the thickness W2 of the third supporting layer 132. When the hard mask layer 150 is within the disclosed range, the same hard mask layer 150 can be used in subsequent processes to pattern multiple supporting layers (e.g., the second supporting layer 126, the third supporting layer 132, and the fourth supporting layer 136). In this way, the number of photolithography processes in forming the semiconductor device 100 can be reduced, thereby reducing the process cost.

Referring to FIG. 6 , a photoresist layer PR is formed on the hard mask layer 150. Specifically, a photoresist material layer may be formed on the hard mask layer 150, and then the photoresist material layer may be exposed and developed to form the photoresist layer PR on the hard mask layer 150. The photoresist layer PR has an opening O1, and the width of the opening O1 is wider than the patterned fourth supporting layer 136 below. That is, the opening O1 of the photoresist layer PR partially overlaps with the lower electrode material layer 142 in the first trench T1.

Referring to FIG. 7 , the hard mask layer 150 is used as an etching mask to form a second trench T2 in the multi-layer structure 120 to partially etch the lower electrode material layer 142, and the bottom of the second trench T2 is higher than the third supporting layer 132. In some embodiments, the bottom of the second trench T2 is lower than the bottom of the fourth supporting layer 136. Specifically, the photoresist layer PR can be used as a mask to pattern the hard mask layer 150 to form an opening in the hard mask layer 150. Then, the hard mask layer 150 is used as an etching mask to form a second trench T2 in the multi-layer structure 120, and the second trench T2 corresponds to the opening O1 (see FIG. 6 ). Since the opening O1 of the photoresist layer PR partially overlaps with the lower electrode material layer 142 in the first trench T1, a portion of the lower electrode material layer 142 in the first trench T1 is also etched when the second trench T2 is formed. Therefore, in the subsequent process, the wet etchant used to remove the sacrificial material layer can flow between the lower electrode material layers 142 more easily. If the lower electrode material layer 142 in the first trench T1 is not etched when the second trench T2 is formed, it may be impossible to confirm whether the uppermost lower electrode material layer 142 (the lower electrode material layer 142 directly below the opening O1 in FIG. 6 ) is etched, making it difficult for the wet etchant to flow in. In some embodiments, the second trench T2 is wider than any of the first trenches T1. Since the bottom of the second trench T2 is higher than the third supporting layer 132, the lower electrode material layer 142 is not lost much. In the finally formed semiconductor device 100, the lower electrode layer formed by the lower electrode material layer 142 has a sufficient volume to accommodate more charges, so that the semiconductor device 100 has more capacitance. Since the thickness W1 of the hard mask layer 150 (see FIG. 5 ) is 3 to 12 times the thickness W2 of the third support layer 132 (see FIG. 5 ), the hard mask layer 150 can be used to pattern the lower electrode material layer 142 of the capacitor structure and pattern the lower electrode material layer 142 into a desired shape. Then, the hard mask layer is used to etch back other material layers. This can reduce the loss of the lower electrode layer during patterning to increase the capacitance content of the lower electrode layer.

Referring to FIG. 8 , the third sacrificial material layer 134 is removed. Specifically, a wet etching process or an isotropic etching process can be used to completely remove the third sacrificial material layer 134. In some embodiments, dilute hydrofluoric acid can be used to remove the third sacrificial material layer 134, but it is not limited thereto. Since the hard mask layer 150, the fourth support layer 136, and the third support layer 132 have sufficient etching resistance to this wet etching process, the hard mask layer 150, the fourth support layer 136, and the third support layer 132 will not be removed. The third supporting layer 132 may serve as an etching stop layer. After the third sacrificial material layer 134 is removed, the third supporting layer 132 is exposed.

Referring to FIG. 9 , the third supporting layer 132 is etched back using the hard mask layer 150 and the lower electrode material layer 142 as etching masks. Specifically, the third supporting layer 132 can be etched back using an anisotropic etching process such as a dry etching process. When etching back the third supporting layer 132, the third supporting layer 132 exposed by the second trench T2 will be etched, while the third supporting layer 132 directly below the hard mask layer 150 remains in place. When etching back the third supporting layer 132, since the hard mask layer 150 and the third supporting layer 132 are made of the same or similar material, the hard mask layer 150 will also be partially removed. However, the thickness of the hard mask layer 150 is as disclosed above, so even if it is partially etched, the hard mask layer 150 can still have a certain thickness and serve as a mask in subsequent processes. In addition, since the lower electrode material layer 142 and the third supporting layer 132 are made of different materials, the lower electrode material layer 142 can also serve as a mask layer for etching back the third supporting layer 132.

Referring to FIG. 10 , the second sacrificial material layer 128 is removed. Specifically, a wet etching process or an isotropic etching process can be used to completely remove the second sacrificial material layer 128. In some embodiments, dilute hydrofluoric acid can be used to remove the second sacrificial material layer 128, but it is not limited thereto. Since the hard mask layer 150, the fourth support layer 136, the third support layer 132, and the second support layer 126 have sufficient etching resistance to this wet etching process, the hard mask layer 150, the fourth support layer 136, the third support layer 132, and the second support layer 126 will not be removed. The second supporting layer 126 may serve as an etching stop layer. After the second sacrificial material layer 128 is removed, the second supporting layer 126 is exposed.

Referring to FIG. 11 , the second supporting layer 126 is etched back using the hard mask layer 150 (see FIG. 10 ) and the lower electrode material layer 142 as etching masks. Specifically, the second supporting layer 126 can be etched back using an anisotropic etching process such as a dry etching process. When etching back the second supporting layer 126, the second supporting layer 126 exposed by the second trench T2 will be etched, while the second supporting layer 126 directly below the hard mask layer 150 remains in place. When etching back the second supporting layer 126, since the hard mask layer 150 and the second supporting layer 126 are made of the same or similar material, the hard mask layer 150 will also be completely removed. In addition, since the lower electrode material layer 142 and the second supporting layer 126 are made of different materials, the lower electrode material layer 142 can also be used as a material layer for etching back the second supporting layer 126. After etching back the second supporting layer 126, the lower electrode material layer 142 on the fourth supporting layer 136 can be removed to expose the fourth supporting layer 136. In this way, the lower electrode material layer 142 is etched into the lower electrode layer 140, and the top of the lower electrode layer 140 is connected by the fourth supporting layer 136.

Referring to FIG. 12 , the first sacrificial material layer 124 is removed. Specifically, a wet etching process or an isotropic etching process can be used to completely remove the first sacrificial material layer 124. In some embodiments, dilute hydrofluoric acid can be used to remove the first sacrificial material layer 124, but it is not limited thereto. Since the fourth supporting layer 136, the third supporting layer 132, the second supporting layer 126 and the first supporting layer 122 have sufficient etching resistance to this wet etching process, the fourth supporting layer 136, the third supporting layer 132, the second supporting layer 126 and the first supporting layer 122 will not be removed. The first support layer 122 may serve as an etch stop layer. After the first sacrificial material layer 124 is removed, the first support layer 122 is exposed.

Referring to FIG. 13A and FIG. 13B , FIG. 13B is an enlarged view of region M of FIG. 13A , an insulating layer 160, an upper electrode layer 170, and a conductive layer 180 are sequentially formed on the lower electrode layer 140, the first supporting layer 122, the second supporting layer 126, the third supporting layer 132, and the fourth supporting layer 136. The insulating layer 160 may cover the lower electrode layer 140, the first supporting layer 122, the second supporting layer 126, the third supporting layer 132, and the fourth supporting layer 136. The upper electrode layer 170 covers the insulating layer 160, and the conductive layer 180 covers the upper electrode layer 170. In this way, the insulating layer 160, the upper electrode layer 170 and the conductive layer 180 can fill the gaps between the lower electrode layer 140, the first supporting layer 122, the second supporting layer 126, the third supporting layer 132 and the fourth supporting layer 136 to form the semiconductor device 100, and the semiconductor device 100 is a capacitor structure. In some embodiments, the insulating layer 160 is a high dielectric constant material layer, such as zirconium oxide ( _ZrOx ), the upper electrode layer 170 is titanium nitride (TiN), and the conductive layer 180 is polysilicon, but the materials of the insulating layer 160, the upper electrode layer 170 and the conductive layer 180 are not limited thereto. In addition, although only the conductive layer 180 is shown here to cover the upper electrode layer 170, more layers may cover the upper electrode layer 170 and the conductive layer 180.

Specifically, the semiconductor device 100 may include a contact layer 110, a first supporting layer 122, a plurality of lower electrode layers 140, a second supporting layer 126, a third supporting layer 132, and a fourth supporting layer 136. The contact layer 110 includes a contact plug 112. The first supporting layer 122 is on the contact layer 110. The lower electrode layer 140 is on the first supporting layer 122, and the lower electrode layer 140 is directly above the contact plug 112 of the contact layer 110. Any of the lower electrode layers 140 includes a first portion 144 and a second portion 146, and the second portion 146 is on the first portion 144 and narrower than the first portion 144. The second supporting layer 126 is between two adjacent ones of the lower electrode layers 140, and the second supporting layer 126 contacts a first portion 144 of any one of the lower electrode layers 140. The third supporting layer 132 is on the second supporting layer 126 and contacts a first portion 144 of any one of the lower electrode layers 140. The third supporting layer 132 is between two adjacent ones of the lower electrode layers 140. The fourth supporting layer 136 is on the third supporting layer 132 and contacts a second portion 146 of any one of the lower electrode layers 140. The fourth supporting layer 136 is between two adjacent lower electrode layers 140 , and the top of the lower electrode layer 140 is flush with the top of the fourth supporting layer 136 .

The top of the first portion 144 of any one of the lower electrode layers 140 is higher than the third supporting layer 132. In some embodiments, the top of the first portion 144 of any one of the lower electrode layers 140 is lower than the fourth supporting layer 136. Since a small portion of the lower electrode layer 140 is lost when the lower electrode layer 140 is formed, the lower electrode layer 140 can accommodate more charges, so that the capacitance contained in the lower electrode layer 140 increases.

FIG. 14 shows a cross-sectional view of the semiconductor device 100 according to some other embodiments. In FIG. 14 , the top of the first portion 144 of any one of the lower electrode layers 140 is flush with the bottom of the fourth supporting layer 136. Other relevant details are the same as those in FIG. 13A and are not described again.

Although some embodiments of the present disclosure only show that the semiconductor device 100 has the first supporting layer 122, the second supporting layer 126, the third supporting layer 132, and the fourth supporting layer 136, the semiconductor device 100 may also have more supporting layers, which may be located below the third supporting layer 132. Specifically, a thicker hard mask layer 150 may be formed during the process of FIG. 5, and then the semiconductor device 100 may be formed using FIG. 6 and subsequent processes, or after the hard mask layer 150 is removed, multiple supporting layers may be etched back and forth using the lower electrode material layer 142 as an etching mask. In this way, the hard mask layer can have sufficient thickness and strength to etch back and forth multiple supporting layers to form a semiconductor device 100 with more supporting layers.

In summary, in some embodiments of the present disclosure, a hard mask layer can be formed on the fourth supporting layer used to form the capacitor structure, and the thickness of the hard mask layer is 3 to 12 times that of the third supporting layer. Therefore, the same hard mask layer can be used to pattern the lower electrode layer of the capacitor structure, etch back the third supporting layer and the second supporting layer, and reduce the photolithography process in the process of manufacturing the capacitor structure, thereby reducing the alignment problem caused by different photolithography processes. Since the capacitor structure formed in some embodiments of the present disclosure does not have alignment problems, the hard mask layer can be used to pattern the lower electrode layer first, and then the hard mask layer can be used to etch back the third support layer. In this way, the loss of the lower electrode layer during patterning can be reduced to increase the charge capacity of the lower electrode layer to increase the capacitance content.

Although the present disclosure has been disclosed in the above implementation form, it is not intended to limit the present disclosure. Anyone skilled in the art can make various changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the definition of the attached patent application scope.

100: semiconductor device 110: contact layer 112: contact plug 114: dielectric layer 120: multi-layer structure 122: first support layer 124: first sacrificial material layer 126: second support layer 128: second sacrificial material layer 132: third support layer 134: third sacrificial material layer 136: fourth support layer 140: lower electrode layer 142: lower electrode material layer 144: first part 146: second part 150: hard mask layer 160: insulating layer 170: upper electrode layer 180: conductor layer O1: opening M: region PR: photoresist layer R1: array region R2: peripheral region T1: first trench T2: second trench W1: thickness W2: thickness

FIG. 1 to FIG. 13A are cross-sectional views of the manufacturing process of the semiconductor device of some embodiments of the present disclosure. FIG. 13B is an enlarged view of the area M of FIG. 13A. FIG. 14 is a cross-sectional view of the semiconductor device of other embodiments of the present disclosure.

Domestic storage information (please note in the order of storage institution, date, and number) None Foreign storage information (please note in the order of storage country, institution, date, and number) None

100:Semiconductor devices

110: Contact layer

112: Contact embolism

114: Dielectric layer

122: The first support layer

126: The second support layer

132: The third support layer

136: The fourth supporting layer

140: Lower electrode layer

144: Part 1

146: Part 2

180: Conductor layer

M: Region

R1: Array area

R2: Peripheral area

Claims (10)

A semiconductor device comprises: a contact layer, wherein the contact layer comprises a plurality of contact plugs; a first supporting layer, on the contact layer; a plurality of lower electrode layers, on the first supporting layer, wherein any one of the lower electrode layers comprises a first portion and a second portion, the second portion being on the first portion and narrower than the first portion; a second supporting layer, contacting the first portion of any one of the lower electrode layers; a third supporting layer, on the second supporting layer and contacting the first portion of any one of the lower electrode layers; A fourth supporting layer is on the third supporting layer and contacts the second portion of any one of the lower electrode layers, wherein a top portion of the first portion of any one of the lower electrode layers is higher than the third supporting layer. A semiconductor device as described in claim 1, wherein the top of the first portion of any one of the lower electrode layers is flush with a bottom of the fourth supporting layer. A semiconductor device as described in claim 1, wherein the top of the first portion of any one of the lower electrode layers is lower than the fourth supporting layer. A semiconductor device as described in claim 1, wherein the lower electrode layers are directly above the contact plugs of the contact layer. A semiconductor device as described in claim 1, wherein a plurality of tops of the lower electrode layers are flush with a top of the fourth supporting layer. A method for manufacturing a semiconductor device, comprising: Providing a contact layer, wherein the contact layer comprises a plurality of contact plugs; Forming a multi-layer structure on the contact layer, wherein the multi-layer structure comprises a first supporting layer, a first sacrificial material layer, a second supporting layer, a second sacrificial material layer, a third supporting layer, a third sacrificial material layer and a fourth supporting layer stacked from bottom to top; Forming a plurality of first trenches in the multi-layer structure, wherein a plurality of bottoms of the first trenches expose the contact layer; Forming a lower electrode material layer on the multi-layer structure and in the first trenches; Forming a hard mask layer on the lower electrode material layer; Using the hard mask layer as an etching mask, forming a second trench in the multi-layer structure to partially etch the lower electrode material layer, and a bottom of the second trench is higher than the third supporting layer; Removing the third sacrificial material layer; Using the hard mask layer and the lower electrode material layer as etching masks, etching back the third supporting layer; Removing the second sacrificial material layer; Using the hard mask layer and the lower electrode material layer as etching masks, etching back the second supporting layer; and Removing the first sacrificial material layer. The method of claim 6, wherein a thickness of the hard mask layer is 3 to 12 times a thickness of the third supporting layer. The method of claim 6, wherein the bottom of the second trench is lower than a bottom of the fourth supporting layer. The method of claim 6, wherein when forming the second trench, the second trench is wider than any of the first trenches. The method of claim 6, wherein the hard mask layer is completely removed when etching back the second support layer.

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