TW202443933A - Light-emitting device - Google Patents

Abstract

A light-emitting device includes a support substrate, a semiconductor-stack structure, an insulting layer, a first electrode and a second electrode. The semiconductor-stack structure and the second electrode are disposed on two opposite sides of the support substrate. The semiconductor-stack structure includes a first semiconductor layer, a second semiconductor layer on the first semiconductor layer, and an active region between the first semiconductor layer and the second semiconductor layer. The insulating layer is on the second semiconductor layer, and includes one or more first openings disposed on the second semiconductor layer along a first direction in a cross-sectional view. The first electrode is on the one or more first openings and electrically connected to the second semiconductor layer through the one or more first openings. The first electrode includes a frame portion. The frame portion includes one or more notches.

Description

Light emitting element

The present application relates to a light-emitting element, and more particularly to a semiconductor light-emitting element and a method for manufacturing the same.

Light-Emitting Diode (LED) is a solid-state semiconductor light-emitting element. Its advantages are low power consumption, low heat generation, long service life, shock resistance, small size, fast response speed and good photoelectric properties, such as stable luminous wavelength. Light-emitting diodes are widely used in household appliances, equipment indicator lights, and optoelectronic products. How to come up with a new semiconductor light-emitting element that can effectively improve the product yield of semiconductor light-emitting elements is one of the key research and development issues for researchers.

According to one embodiment of the present application, the light-emitting element includes a supporting substrate, a semiconductor stack, an insulating layer, a first electrode and a second electrode. The supporting substrate has a first side and a second side opposite to the first side. The semiconductor stack is located on the first side, the semiconductor stack includes a first semiconductor layer, a second semiconductor layer is located on the first semiconductor layer, and an active region is located between the first semiconductor layer and the second semiconductor layer. The insulating layer is located on the second semiconductor layer. In a cross-sectional view, the insulating layer includes one or more first openings arranged on the second semiconductor layer along a first direction. The first electrode is located on one or more first openings and electrically connected to the second semiconductor layer through the one or more first openings. The second electrode is located on the second side. The first electrode includes an outer frame portion, and the outer frame portion includes one or more notches.

In order to better understand the above and other aspects of this application, the following is a detailed description of the embodiments with the accompanying drawings as follows:

The ordinal numbers used in this application, such as "first", "second", "third", etc., are used to modify the elements. They themselves do not imply or represent any previous ordinal number of the element, nor do they represent the order of one element to another element, or the order of the manufacturing method. The use of these ordinal numbers is only used to make the elements with the same name clearly distinguishable. In addition, the following embodiments will be accompanied by drawings, and the size ratios in the drawings are not drawn in proportion to the actual product. In the drawings, the shape or thickness of the elements may be enlarged or reduced. It should be noted that the elements not shown in the drawings or described in the instructions may be in a form known to those skilled in the art in this technical field. In addition, some elements and/or symbols may be omitted in some drawings. In the drawings, similar symbols are used to indicate similar elements. The following content and the attached drawings are provided for illustration only and are not intended to be limiting. It is contemplated that elements and features of one embodiment can be advantageously incorporated into another embodiment without further elaboration. In addition, other layers/structures or steps may be incorporated in the following embodiments. For example, the description of "forming a second layer/structure on a first layer/structure" may include embodiments in which the first layer/structure directly contacts the second layer/structure, or embodiments in which the first layer/structure indirectly contacts the second layer/structure, i.e., other layers/structures are present between the first layer/structure and the second layer/structure. In addition, the spatial relative relationship between the first layer/structure and the second layer/structure may change according to the operation or use of the device. The first layer/structure itself is not limited to a single layer or a single structure. The first layer may include multiple sublayers, and the first structure may include multiple substructures.

In addition, for the spatially related descriptive terms mentioned in this application, such as "under", "low", "down", "above", "upper", "top", "bottom" and similar terms, for the convenience of description, their usage is to describe the relative relationship between one element or feature and another element or feature in the drawings. In addition to the orientation shown in the drawings, these spatially related terms are also used to describe the possible orientations of the light-emitting element during use and operation. As the orientation of the semiconductor element is different (rotated 90 degrees or other orientations), the spatially related descriptions used to describe its orientation should also be interpreted in a similar manner.

In this application, if there is no special explanation, the general formula AlGaN series represents Al _a Ga _(1-a) N, where 0≤a≤1; the general formula InGaN series represents In _b Ga _(1–b) N, where 0≤b≤1; the general formula AlInGaN series represents Al _c In _d Ga _(1-cd) N, where 0≤c≤1, 0≤d≤1. Adjusting the content of the elements can achieve different purposes, such as but not limited to adjusting the energy level or adjusting the main emission wavelength of the light-emitting element.

The composition and doping of each layer included in the light-emitting element disclosed in this application can be analyzed by any suitable method, such as secondary ion mass spectrometer (SIMS).

The thickness of each layer included in the light-emitting element disclosed in this application can be analyzed by any suitable method, such as transmission electron microscopy (TEM) or scanning electron microscope (SEM), so as to match the depth position of each layer on the SIMS spectrum, for example.

Please refer to Figures 1A-1E at the same time. Figure 1A is a top view schematic diagram of a light-emitting element 1 according to an embodiment of the present application. Figure 1B is a cross-sectional schematic diagram of the light-emitting element 1 along the section line B-B’ shown in Figure 1A. Figure 1C is a cross-sectional schematic diagram of the light-emitting element 1 along the section line C-C’ shown in Figure 1A. Figure 1D is an enlarged schematic diagram of the light-emitting element 1 shown in area D shown in Figure 1A. Figure 1E is an enlarged schematic diagram of the insulating layer 18 shown in area D shown in Figure 1A. As shown in Figure 1B, the light-emitting element 1 may include a second electrode 11, a supporting substrate 12, a semiconductor stack 17, an insulating layer 18 and a first electrode 19. The supporting substrate 12 has a first side 121 and a second side 122 opposite to the first side 121. The first side 121 and the second side 122 may refer to positions of the supporting substrate 12 in two opposite directions. In one embodiment, the supporting substrate 12 includes a top surface and a bottom surface. The first side 121 and the second side 122 may refer to the top surface and the bottom surface of the supporting substrate 12. The semiconductor stack 17, the insulating layer 18 and the first electrode 19 are located on the first side 121 of the supporting substrate 12. That is, the semiconductor stack 17, the insulating layer 18 and the first electrode 19 are located on the top surface of the supporting substrate 12. The second electrode 11 is located at the second side 122 of the supporting substrate 12. In other words, the second electrode 11 is located below the bottom surface of the supporting substrate 12. In one embodiment, the semiconductor stack 17 may include a first semiconductor layer 171, a second semiconductor layer 172 located on the first semiconductor layer 171, and an active region 173 formed between the first semiconductor layer 171 and the second semiconductor layer 172. The first semiconductor layer 171, the active region 173, and the second semiconductor layer 172 may be stacked in sequence on the first side 121 of the supporting substrate 12 along a direction perpendicular to the bottom surface to the top surface of the supporting substrate 12 (e.g., a third direction Z). The first electrode 19 is located on the second semiconductor layer 172 and electrically connected to the second semiconductor layer 172 .

Referring to FIG. 1A , the first electrode 19 may include an outer frame portion 190. In one embodiment, the outer frame portion 190 is the outermost portion of the first electrode 19 close to the periphery of the light-emitting element 1. The outer frame portion 190 includes a plurality of conductive portions. In one embodiment, the number of conductive portions may be determined corresponding to the number of sides of the semiconductor stack 17, but is not limited thereto. In one embodiment, the conductive portions may not correspond to the number of sides of the semiconductor stack 17. For example, the semiconductor stack 17 may be a polygon, and the outer frame portion 190 may be another polygon different from the polygon of the semiconductor stack 17. In another embodiment, the outer frame portion 190 may have a circular conductive portion that cannot be distinguished by segments. In this embodiment, the outer frame 190 has a plurality of conductive portions corresponding to the number of sides of the semiconductor stack 17. The semiconductor stack 17 has four sides, and the outer frame 190 has four conductive portions close to the four sides of the semiconductor stack 17. In one embodiment, the outer frame 190 may include a first conductive portion 190a1, a second conductive portion 190a2 opposite to the first conductive portion 190a1, a third conductive portion 190a3 connecting the first conductive portion 190a1 and the second conductive portion 190a2, and a fourth conductive portion 190a4 opposite to the third conductive portion 190a3. In the second direction Y perpendicular to the first direction X, the first conductive portion 190a1 may have the same or different width as the second conductive portion 190a2. In the present embodiment, the first conductive portion 190a1 and the second conductive portion 190a2 have the same width. In the first direction X, the third conductive portion 190a3 may have the same or different width as the fourth conductive portion 190a4. In the present embodiment, the third conductive portion 190a3 and the fourth conductive portion 190a4 have the same width.

Referring to FIG. 1A , the first electrode 19 may further include one or more extensions surrounded by the outer frame 190. In this embodiment, the first electrode 19 includes a first extension 191 and a second extension 192. The first extension 191 and the second extension 192 are surrounded by the outer frame 190 and extend in the second direction Y, respectively. The first extension 191 includes a first end 191b1 and a second end 191b2, and the second extension 192 includes a first end 192b1 and a second end 192b2. Either the first end 191b1 and the second end 191b2 of the first extension portion 191, or either the first end 192b1 and the second end 192b2 of the second extension portion 192 may be connected to the outer frame portion 190, and the other of the first end 191b1 and the second end 191b2 of the first extension portion 191, or the other of the first end 192b1 and the second end 192b2 of the second extension portion 192 may be connected to or not connected to the outer frame portion 190. In one embodiment, the first end 191b1 of the first extension portion 191 is connected to the outer frame portion 190, and the second end 191b2 is not connected to the outer frame portion 190. Both ends of the second extension portion 192 are connected to the outer frame portion 190. In another embodiment, either one of the first extension portion 191 and the second extension portion 192 is connected to the outer frame portion 190, and the other end is not connected to the outer frame portion 190. Any end of the extension portion can be connected to the outer frame portion 190 without causing a circuit break.

Please refer to FIG. 1A, FIG. 1C and FIG. 1D, any conductive portion of the outer frame portion 190 may include one or more first ends 190b1 and one or more second ends 190b2, and any first end 190b1 and the second end 190b2 adjacent thereto define a notch 21. In other words, the notch 21 is located on any conductive portion, dividing the conductive portion into two parts, and the conductive portion includes the first end 190b1 and the second end 190b2 separated by the notch 21. In one embodiment, without causing a circuit break, the outer frame portion 190 may include one or more notches 21 located on any one or more of the first conductive portion 190a1, the second conductive portion 190a2, the third conductive portion 190a3 and the fourth conductive portion 190a4. Referring to Figures 1A and 1D, in one embodiment, if the first end 190b1 and the second end 190b2 are connected by a virtual connection 22, the outer frame portion 190 and the virtual connection 22 can form a closed pattern. The closed pattern can correspond to the shape of the outer frame portion. In this embodiment, the closed pattern can be a rectangle, but is not limited to this. In other embodiments not shown, the closed pattern can also be other polygons, such as a triangle, a trapezoid, a parallelogram, or a pentagon, or can be a circle or an ellipse. In one embodiment, without causing a circuit break, any end of any extension portion that is not connected to the conductive portion is disconnected from the conductive portion through a notch 21. Referring to FIG. 1A , the second end 191b2 of the first extension portion 191 is not connected to the second conductive portion 190a2 of the outer frame portion 190, and a gap 21 is provided between the second end 191b2 and the second conductive portion 190a2. In other words, the second conductive portion 190a2 includes a first end 190b1 and a second end 190b2 that are not connected, the first extension portion 191 has a second end 191b2 that is not connected to the second conductive portion 190a2, and the first end 190b1, the second end 190b2 of the second conductive portion 190a2 and the second end 191b2 of the first extension portion 191 define a gap 21. The second end 191b2 of the first extension portion 191 and the first end 190b1 and the second end 190b2 of the outer frame portion 190 are separated from each other by the gap 21. The notch 21 is located between the first end 190b1 and the second end 190b2 of the outer frame portion 190 and the second end 191b2 of the first extension portion 191. Similarly, each notch 21 may be defined by the second end 191b2 of the first extension portion 191, the first end 190b1 and the second end 190b2 of the outer frame portion 190. In another embodiment of the present application, the first electrode 19 may not include any extension portion, and the notch 21 is only located on the outer frame portion 190, and the first end 190b1 and the adjacent second end 190b2 of any conductive portion of the outer frame portion 190 define the notch 21. In another embodiment of the present application, any end of any extension portion of the first electrode 19 that is not connected to the conductive portion is not provided corresponding to the notch 21, and the notch 21 is only located on any conductive portion, but not between any extension portion and the conductive portion. For example, the second end 191b2 of the first extension portion 191 not connected to the conductive portion is provided corresponding to the portion other than the first end 190b1 and the second end 190b2 of the second conductive portion 190a2 (not shown). Regardless of whether the notch 21 is defined by both ends of the outer frame portion 190, or the notch 21 is defined by one end of the extension portion and both ends of the outer frame portion 190, the yield of the subsequent manufacturing process can be improved to improve the reliability of the light-emitting element 1, and the details will be described later.

In one embodiment, in the first direction X of FIG. 1A, the first extension portion 191 has a width that may be the same as or different from the width of the second extension portion 192. In this embodiment, the first extension portion 191 and the second extension portion 192 have the same width. In one embodiment, in the second direction Y of FIG. 1A, the first conductive portion 190a1 and the second conductive portion 190a2 of the outer frame portion 190 respectively have a width, and in the first direction X of FIG. 1A, the third conductive portion 190a3 and/or the fourth conductive portion 190a4 respectively have a width. The width of each conductive portion may be the same as or different from the first extension portion 191 and/or the second extension portion 192. In another embodiment, the width of the first conductive portion 190a1, the second conductive portion 190a2, the third conductive portion 190a3 and/or the fourth conductive portion 190a4 is greater than the width of the first extension portion 191 and/or the second extension portion 192. In one embodiment, the width of the first extension portion 191 is between 3 micrometers ( ) to 25 microns ( ), 10 microns ( ) to 25 microns ( ), or 15 microns ( ) to 20 microns ( In one embodiment, the width of the second extension portion 192 is between 3 microns ( ) to 25 microns ( ), 10 microns ( ) to 25 microns ( ), or 15 microns ( ) to 20 microns ( ).

Referring to FIG. 1A , the number of the notches 21 may be one or more, which may be determined by the size of the light-emitting element 1. For example, when the area of the light-emitting element 1 is larger, the number of extensions of the first electrode 19 may be increased according to the increase in the area of the light-emitting element 1 to ensure current dispersion. The number of notches 21 may be increased accordingly. Alternatively, when the side length of the light-emitting element 1 increases, the number of extensions may also be increased accordingly, thereby increasing the number of notches 21 on the side with increased side length. In this embodiment, the number of notches 21 is exemplified as 2, but is not limited thereto. The position of the notch 21 may be set according to the position configuration of the outer frame portion 190 and/or the extension. In one embodiment, the notch 21 may be located at a corner where two conductive portions intersect, such as a corner between the second conductive portion 190a2 and the third conductive portion 190a3, or a corner between the second conductive portion 190a2 and the fourth conductive portion 190a4. Referring to FIGS. 1A and 1D, taking the second conductive portion 190a2 as an example, in the extension direction (first direction X) of the second conductive portion 190a2, there is a first distance D1 between the first end 190b1 and the second end 190b2. In other words, the notch 21 has a notch width that is the same as the first distance D1. In one embodiment, the first distance (notch width) D1 is smaller than the length L1 of the second conductive portion 190a2 in the first direction X. In one embodiment, the ratio of the first distance D1 between the first end 190b1 and the second end 190b2 of the second conductive portion 190a2 to the length L1 of the second conductive portion 190a2 in the first direction X is between 1:15 and 1:25, and in another embodiment, the ratio is between 1:16 and 1:20. When the ratio of the first distance D1 between the first end 190b1 and the second end 190b2 of the second conductive portion 190a2 to the length L1 of the second conductive portion 190a2 is within the aforementioned range, the yield of subsequent processes can be ensured to improve the reliability of the light emitting device 1, which will be described in detail later. If the ratio of the first distance D1 to the length L1 of the second conductive portion 190a2 in the first direction X is greater than 1:15-1:25, the proportion of the notch 21 is too large, resulting in a reduction in the area of the conductive portion and the extension portion of the outer frame portion 190 of the first electrode 19, making the current diffusion of the second semiconductor layer 172 uneven and affecting the light-emitting efficiency of the light-emitting element 1. If the ratio of the first distance D1 to the length L1 of the second conductive portion 190a2 in the first direction X is less than 1:15-1:25, the notch 21 is too small, affecting the yield of subsequent processes and causing a decrease in the reliability of the light-emitting element 1. In one embodiment, a first distance D1 between the first end 190b1 and the second end 190b2 of the second conductive portion 190a2 is greater than a width of the first extending portion 191 and/or the second extending portion 192 in the first direction X.

Referring to FIG. 1A and FIG. 1B , the first electrode 19 may further include an electrode pad 20. The electrode pad 20 may be disposed on the outer frame 190. In one embodiment, the electrode pad 20 may be disposed at a corner of the outer frame 190, that is, between two conductive portions of the outer frame 190, or disposed on any conductive portion of the outer frame 190. The number of the electrode pad 20 may include one or more, and the number of the electrode pad 20 may be adjusted according to the area of the light-emitting element 1 (semiconductor stack 17) or the size of the operating current. In this embodiment, there are two electrode pads 20, which are respectively disposed between the first conductive portion 190a1 and the third conductive portion 190a3, and between the first conductive portion 190a1 and the fourth conductive portion 190a4. In another embodiment, the electrode pad 20 may be disposed between the outer frame 190 and the first extension portion 191, or between the outer frame 190 and the second extension portion 192.

Please refer to FIG. 1A, FIG. 1B, FIG. 1C, FIG. 1D and FIG. 1E. Among them, FIG. 1E only shows the insulating layer 18, and is combined with other diagrams to clearly show the upper and lower positional relationship between the insulating layer 18 and the outer frame portion 190 and the first extension portion 191. The insulating layer 18 can be disposed on the upper surface 172s of the second semiconductor layer 172. The insulating layer 18 can cover a portion of the upper surface 172s of the second semiconductor layer 172, and can also extend to cover the side surface of the semiconductor stack 17. In one embodiment, the upper surface 172s of the second semiconductor layer 172 can be a rough upper surface. By means of the rough upper surface 172s of the second semiconductor layer 172, the light energy emitted by the active area 173 can be extracted to the outside with a greater probability, thereby improving the light extraction rate. The formation method of the rough upper surface 172s of the second semiconductor layer 172 will be described in detail later. The insulating layer 18 can smoothly cover the upper surface 172s of the second semiconductor layer 172, so the upper surface of the insulating layer 18 can include a concave-convex pattern. Referring to Figures 1A and 1B, the insulating layer 18 includes a first opening 18a corresponding to the first electrode 19. The insulating layer 18 can include one or more first openings 18a corresponding to the conductive portion and the extension portion. As shown in the cross-sectional schematic diagram of FIG. 1B , the number of the first openings 18a is 5, corresponding to the third conductive portion 190a3, the fourth conductive portion 190a4, the first extension portion 191, and the second extension portion 192, but the present invention is not limited thereto. Specifically, the insulating layer 18 includes the first openings 18a corresponding to the outer frame portion 190, the first extension portion 191, the second extension portion 192, and the electrode pad 20 of the first electrode 19. In one embodiment, the first opening 18a is provided between the upper surface 172s of the second semiconductor layer 172 and the first electrode 19, corresponding to the outer frame portion 190, the first extension portion 191, the second extension portion 192, and the electrode pad 20 of the first electrode 19. As shown in FIG. 1B and FIG. 1C , the first electrode 19 can pass through the first opening 18a and electrically connect to the second semiconductor layer 172 of the semiconductor stack 17. In one embodiment, a portion of the conductive portion and the extension portion of the first electrode 19 are in contact with the second semiconductor layer 172 through the first opening 18a, and the other portions extend outside the first opening 18a and cover the insulating layer 18. In other words, the first extension portion 191, the second extension portion 192, the first conductive portion 190a1, the second conductive portion 190a2, the third conductive portion 190a3, the fourth conductive portion 190a4, and a portion of the electrode pad 20 are in contact with the second semiconductor layer 172 through the first opening 18a, and the other portions extend out of the first opening 18a and cover the insulating layer 18. The outer frame portion 190 of the first electrode 19, the first extension portion 191, and the second extension portion 192 overlap the insulating layer 18 and the first opening 18a in the third direction Z perpendicular to the top surface of the supporting substrate 12. Referring to FIG. 1B , in this embodiment, the width of the first extension portion 191, the second extension portion 192, the third conductive portion 190a3, and the fourth conductive portion 190a4 of the first electrode 19 in the first direction X is greater than the width W2 of the first opening 18a of the insulating layer 18 in the first direction X. In one embodiment, the first distance D1 between the first end 190b1 and the second end 190b2 of the outer frame portion 190 is greater than the width W2 of the first opening 18a in the first direction X. In one embodiment, the width W2 may be between 2 microns ( ) to 10 microns ( ), or between 3 microns ( ) to 5 microns ( ). By designing the width W2 of the first opening 18a to be within the aforementioned range, the contact area of the outer frame portion 190 of the first electrode 19, the first extension portion 191, the second extension portion 192 and the second semiconductor layer 172 of the semiconductor stack 17 can be increased, thereby reducing the forward voltage (Vf) of the light-emitting element 1, so that the light-emitting element 1 has more stable electrical characteristics. Similarly, the insulating layer 18 below the electrode pad 20 of the first electrode 19 can have a first opening 18a, and the first opening 18a is filled in a manner similar to the conductive portion and the extension portion and extends to cover the insulating layer 18. In another embodiment, the insulating layer 18 below the electrode pad 20 does not have the first opening 18a, and the electrode pad 20 is directly formed on the insulating layer 18 without contacting the second semiconductor layer 172. By having the first electrode 19 cover the insulating layer 18 around the first opening 18a, moisture can be prevented from penetrating into the semiconductor stack 17 through a possible gap between the first electrode 19 and the insulating layer 18. However, the present invention is not limited thereto, and in another embodiment, the first electrode 19 is only located in the first opening 18a of the insulating layer 18, and does not extend to cover the insulating layer 18. The width of the first electrode 19 is substantially the same as the width of the first opening 18 a of the insulating layer 18 .

Referring to FIG. 1D and FIG. 1E , the first opening 18a of the insulating layer 18 may have one or more first end points 18a1 and one or more second end points 18a2 under the conductive portion at the notch 21 corresponding to any conductive portion of the outer frame portion 190. The first opening 18a of the insulating layer 18 under the extension portion may have a third end point at the notch 21 corresponding to any conductive portion of the outer frame portion 190. The first end point 18a1 and the second end point 18a2 of the first opening 18a of the insulating layer 18 may have a second distance D2 at the notch 21 corresponding to any conductive portion of the outer frame portion 190. In this embodiment, the first opening 18a of the insulating layer 18 may have a first end 18a1 and a second end 18a2 under the second conductive portion 190a2 at the notch 21 corresponding to the outer frame portion 190. The first opening 18a of the insulating layer 18 has a third end 18a3 at the second end 191b2 corresponding to the first extension portion 191. The first end 18a1 and the second end 18a2 of the first opening 18a of the insulating layer 18 have a second distance D2 at the notch 21 corresponding to the second conductive portion 190a2 of the outer frame portion 190. In one embodiment, the second distance D2 is between 50 microns ( ) and 80 microns ( ), or 60 microns ( ) and 70 microns ( ). In this embodiment, the second distance D2 between the first end 18a1 and the second end 18a2 of the first opening 18a of the insulating layer 18 is greater than the first distance D1 between the first end 190b1 and the second end 190b2 of the outer frame portion 190. By designing that the second distance D2 is greater than the first distance D1, the first electrode 19, that is, the outer frame portion 190, can completely cover the first opening 18a of the insulating layer 18, so that the contact area between the first electrode 19 and the second semiconductor layer 172 through the first opening 18a is maximized to improve the device characteristics. In addition, there is a distance between the first opening 18a and the first end 190b1 or the second end 190b2 to ensure the yield of the subsequent process and to improve the reliability of the light-emitting element, which will be described in detail later. The relative relationship between the extension portion and the third end 18a3 of the first opening 18a is similar to the above description and will not be repeated. The insulating layer 18 may include insulating materials; the insulating materials include but are not limited to silicon oxide ( _SiO2 ), silicon _nitride ( _SiNx or _Si3N4 ), aluminum oxide ( _{Al2O3 )} , titanium oxide ( _TiO2 ) or a combination of the above materials.

The first electrode 19 and the second electrode 11 may include a conductive material. The first electrode 19 and the second electrode 11 may include the same or different conductive materials. The conductive material of the first electrode 19 and the second electrode 11 may include a metal material or a transparent conductive material; for example, the metal material may include but is not limited to aluminum (Al), chromium (Cr), copper (Cu), tin (Sn), gold (Au), nickel (Ni), titanium (Ti), platinum (Pt), palladium (Pd), silver (Ag), lead (Pb), zinc (Zn), cadmium (Cd), antimony (Sb), cobalt (Co), rhodium (Rh), or any combination thereof. alloy, etc.; the transparent conductive material may include but is not limited to indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), aluminum zinc oxide (AZO), zinc tin oxide (ZTO), gallium zinc oxide (GZO), indium tungsten oxide (IWO), zinc oxide (ZnO), indium zinc oxide (IZO), titanium nitride (TiN), diamond-like carbon film (DLC) or graphene. In one embodiment, the first electrode 19 and the second electrode 11 respectively include a single layer or a multi-layer structure. The first electrode 19 and the second electrode 11 are respectively disposed on the first side 121 and the second side 122 of the supporting substrate 12 to form a vertical light-emitting element. Specifically, the electrode pad 20 of the first electrode 19 and the second electrode 11 can be electrically connected to an external power source respectively. After the current is injected through the electrode pad 20, the current is diffused laterally through the outer frame 190 and the first extension portion 191 and the second extension portion 192 and then injected into the semiconductor stack 17.

As shown in FIG. 1B and FIG. 1C , the light-emitting element 1 may further include a current blocking layer 16. The current blocking layer 16 may be disposed on the surface 171s of the first semiconductor layer 171. The current blocking layer 16 is located between the first semiconductor layer 171 and the supporting substrate 12. In one embodiment, the current blocking layer 16 may directly contact the first semiconductor layer 171. In one embodiment, a portion of the current blocking layer 16 is covered by the insulating layer 18. In one embodiment, the current blocking layer 16 may be disposed corresponding to the structure of the first electrode 19, overlapping the first electrode 19 in the third direction Z. Since the current blocking layer 16 is disposed corresponding to the first electrode 19, the current blocking layer 16 is also disposed corresponding to the position of the first opening 18a, and can overlap the first opening 18a in the third direction Z. The area of the first electrode 19 on the XY plane can be smaller than the area of the current blocking layer 16 on the XY plane to prevent the excessive area of the first electrode 19 from shielding the light emitted from the active area 173. In addition, in this embodiment, the first semiconductor layer 171 is a p-type semiconductor layer, and the second semiconductor layer 172 is an n-type semiconductor layer. The lateral diffusion speed of electrons in the second semiconductor layer 172 is greater than the lateral diffusion speed of holes in the first semiconductor layer 171. Therefore, the current (holes) injected from the second electrode 11 can be matched with the electrons that diffuse laterally faster through the larger current blocking layer 16, so that the light-emitting area in the active area 173 can avoid the light-shielding area where the first electrode 19 is located as much as possible, and concentrate the composite light emission outside the light-shielding area in the active area 173 to further reduce the light-shielding effect of the first electrode 19. The current blocking layer 16 may overlap or not overlap the gap 21 in the third direction Z. In one embodiment, the pattern of the current blocking layer 16 corresponds to the pattern of the first electrode 19, so that the position of the gap 21 does not overlap in the third direction Z, or the current blocking layer 16 overlaps only a portion of the gap 21. In another embodiment, the pattern of the current blocking layer 16 may correspond to the first electrode 19 and the gap 21 to form a continuous pattern, so that the position of the gap 21 overlaps in the third direction Z. The current blocking layer 16 may include a material with low _light absorption rate, such as silicon dioxide ( _SiO2 ), titanium dioxide ( _TiO2 ) or niobium pentoxide ( _Nb2O5 ). The material selection of the current blocking layer 16 can be selected and adjusted according to the wavelength of the light emitted by the active area 173.

As shown in FIG. 1B and FIG. 1C , the light emitting element 1 may further include a reflective layer 15. In one embodiment, the reflective layer 15 contacts the current blocking layer 16. The reflective layer 15 may be disposed on the surface 171s of the first semiconductor layer 171. In one embodiment, the reflective layer 15 may directly contact the first semiconductor layer 171 to form an ohmic contact. In one embodiment, a transparent conductive layer (not shown) made of materials such as indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), aluminum zinc oxide (AZO), zinc tin oxide (ZTO), gallium zinc oxide (GZO), indium tungsten oxide (IWO), zinc oxide (ZnO), indium zinc oxide (IZO), titanium nitride (TiN), diamond-like carbon film (DLC) or graphene may be included between the reflective layer 15 and the first semiconductor layer 171. The transparent conductive layer may directly contact the first semiconductor layer 171 to form an ohmic contact. The reflective layer 15 is located between the current blocking layer 16 and the supporting substrate 12. In one embodiment, the reflective layer 15 can be patterned between two adjacent current blocking layers 16, or formed between two adjacent current blocking layers 16 and extending onto a portion of the current blocking layer 16. The reflective layer 15 can include a metal material, such as silver (Ag), gold (Au), aluminum (Al), titanium (Ti), chromium (Cr), copper (Cu), nickel (Ni), platinum (Pt), ruthenium (Ru), tungsten (W), rhodium (Rh), or alloys or stacks of the above materials. In one embodiment, the reflective layer 15 may include a multi-layer structure (not shown), for example, the reflective layer 15 may include a stacked multi-layer structure, and the stacked multi-layer structure may be stacked in sequence along a direction perpendicular to the top surface to the bottom surface of the supporting substrate 12 (opposite to the third direction Z). The material selection of the reflective layer 15 may be selected and adjusted according to the wavelength of the light emitted by the active area 173. For example, when the light emitted by the active area 173 is light in the UV band, a metal with a higher reflectivity for light in the UV band may be selected as the material of the reflective layer 15, such as aluminum (Al). In another embodiment, when the light emitted by the active area 173 is light in the blue or green band, a material containing silver (Ag) may be selected for the first metal layer. In another embodiment, when a transparent conductive layer is included between the reflective layer 15 and the first semiconductor layer 171, a metal nitride layer may be included between the reflective layer 15 and the transparent conductive layer. The metal nitride layer includes titanium nitride (TiN) material.

The light emitting device 1 may further include a barrier layer 14, which is located between the reflective layer 15 and the supporting substrate 12. The barrier layer 14 may contact a portion of the reflective layer 15 and the current blocking layer 16. In one embodiment, the barrier layer 14 may include a first barrier layer 141 and a second barrier layer 142. The first barrier layer 141 may be disposed on the current blocking layer 16 and the reflective layer 15. The first barrier layer 141 and the semiconductor stack 17 are disposed on opposite sides of the current blocking layer 16 and/or the reflective layer 15, respectively. The first barrier layer 141 may cover the current blocking layer 16 and the reflective layer 15. The first barrier layer 141 can be used to prevent the material of the reflective layer 15 from diffusing during the manufacturing process and destroying the electrical properties of the light-emitting element 1.

The first barrier layer 141 may include a metal material, such as aluminum (Al), chromium (Cr), platinum (Pt), titanium (Ti), tungsten (W), zinc (Zn), rhodium (Rh), or an alloy or stack of the above materials. In one embodiment, the first barrier layer 141 may include a multi-layer structure (not shown), for example, the first barrier layer 141 may include a multi-layer structure of a stacked first metal layer, a second metal layer, and a third metal layer, and the first metal layer, the second metal layer, and the third metal layer may be stacked in sequence along the third direction Z opposite to the first barrier layer 141. The metal layer stacking method and material selection of the first barrier layer 141 can be selected and adjusted according to the wavelength of the light emitted by the active area 173. For example, when the light emitted by the active region 173 is light in the UV band, a metal with a higher reflectivity for light in the UV band can be selected as the material of the first barrier layer 141. For example, the first metal layer can include aluminum (Al), and the first barrier layer 141 assists the reflective layer 15 in reflecting the light emitted by the active region 173. The second metal layer can include titanium tungsten (TiW), and the third metal layer can include platinum (Pt). In another embodiment, the first barrier layer 141 can include a multi-layer structure of a stacked first metal layer and a second metal layer. The first metal layer and the second metal layer can be stacked in sequence along the third direction Z opposite to the first metal layer. The first metal layer can include titanium tungsten (TiW), and the second metal layer can include platinum (Pt). The number of pairs of the first metal layer and the second metal layer of the first barrier layer 141 can be one or more pairs.

The second barrier layer 142 may include a metal material, such as chromium (Cr), platinum (Pt), titanium (Ti), tungsten (W), zinc (Zn), or an alloy or a stack of the above materials. In one embodiment, when the second barrier layer 142 is a metal stack, the second barrier layer 142 may include a structure formed by alternating stacking of two or more metal layers, such as Cr/Pt, Cr/Ti, Cr/TiW, Cr/W, Cr/Zn, Ti/Pt, Ti/W, Ti/TiW, Ti/Zn, TiW/Pt, Pt/W, Pt/Zn, TiW/W, TiW/Zn, or W/Zn.

The light emitting element 1 may further include a bonding layer 13. The second barrier layer 142 and the bonding layer 13 may be sequentially disposed on the first barrier layer 141 along a direction opposite to the third direction Z. The second barrier layer 142 may be used to prevent the material of the bonding layer 13 from diffusing to the first barrier layer 141 and/or the reflective layer 15 during the manufacturing process, thereby affecting the reflectivity and conductive properties of the reflective layer 15 and/or the first barrier layer 141. The bonding layer 13 may be used to bond the supporting substrate 12, the semiconductor stack 17, and the above-mentioned stacked structures formed thereon. The bonding layer 13 may include a transparent conductive material or a metal material; the transparent conductive material includes but is not limited to indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), aluminum zinc oxide (AZO), zinc tin oxide (ZTO), gallium zinc oxide (GZO), zinc oxide (ZnO), gallium phosphide (GaP), indium caesium oxide (ICO), indium tungsten oxide (IW O), indium titanium oxide (ITiO), indium zinc oxide (IZO), indium gallium oxide (IGO), gallium aluminum zinc oxide (GAZO), graphene or a combination of the above materials; metal materials include but are not limited to copper (Cu), aluminum (Al), tin (Sn), gold (Au), silver (Ag), lead (Pb), titanium (Ti), nickel (Ni), platinum (Pt), tungsten (W), indium (In) or alloys or stacks of the above materials.

In one embodiment, the support substrate 12 includes a conductive material or a semiconductor material. The support substrate 12 may include a light-transmitting or light-impermeable material. The support substrate 12 may include a conductive and light-transmitting material including but not limited to a transparent conductive oxide (TCO), such as zinc oxide (ZnO); a conductive but light-impermeable material including but not limited to a metal material, such as aluminum (Al), copper (Cu), molybdenum (Mo), germanium (Ge) or tungsten (W) or an alloy or stack of the above materials; a semiconductor material including silicon (Si), silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), aluminum nitride (AlN), gallium phosphide (GaP), gallium arsenide phosphide (GaAsP), zinc selenide (ZnSe), zinc selenide (ZnSe) or indium phosphide (InP). In one embodiment, the supporting substrate 12 may include an insulating material, such as sapphire, diamond, glass, quartz, acrylic, or epoxy resin.

In one embodiment, the semiconductor stack 17 is a light-emitting stack, and the first semiconductor layer 171 and the second semiconductor layer 172 can be used as confinement layers, carrier supply layers, or contact layers. The first semiconductor layer 171 and the second semiconductor layer 172 can include semiconductor materials of different doping types to supply carriers, for example, the second semiconductor layer 172 includes an n-type semiconductor layer and the first semiconductor layer 171 includes a p-type semiconductor layer to provide electrons and holes, respectively; or the second semiconductor layer 172 includes a p-type semiconductor layer and the first semiconductor layer 171 includes an n-type semiconductor layer to provide holes and electrons, respectively. In this embodiment, the first semiconductor layer 171 includes a p-type semiconductor layer, and the second semiconductor layer 172 includes an n-type semiconductor layer. The active region 173 can be used as a light-emitting structure. The active region 173 is formed between the first semiconductor layer 171 and the second semiconductor layer 172. Electrons and holes are combined in the active region 173 under a current drive, and electrical energy is converted into light energy to emit a light ray. The first semiconductor layer 171, the active region 173, and the second semiconductor layer 172 can include the same series of III-V compound semiconductor materials, such as AlInGaAs series, AlGaInP series, InGaAsP series, or AlInGaN series. Among them, the AlInGaAs series can be expressed as (Al _x1 In _(1-x1) ) _1-x2 Ga _x2 As, the AlInGaP series can be expressed as (Al _x1 In _(1-x1) ) _1-x2 Ga _x2 P, the AlInGaN series can be expressed as (Al _x1 In _(1-x1) ) _1-x2 Ga _x2 N, and the InGaAsP series can be expressed as In _x1 Ga _1-x1 As _x2 P _1-x2 , where 0 x1 1,0 x2 1. The light-emitting element 1 is, for example, a light-emitting diode, and the wavelength of the light emitted by the light-emitting element 1 depends on the material composition of the active region 173. Specifically, the material of the active region 173 may include AlInGaAs series, InGaAsP series, AlGaInP series, InGaN series or AlGaN series. When the material of the active region 173 is AlInGaP series material, red light with a wavelength between 610 nm and 650 nm, or green light with a wavelength between 530 nm and 570 nm can be emitted. When the material of the active region 173 is InGaN series material, blue light with a wavelength between 400 nm and 490 nm, cyan light with a wavelength between 490 nm and 530 nm, or green light with a wavelength between 530 nm and 570 nm can be emitted. When the material of the active region 173 is AlGaN series or AlInGaN series material, ultraviolet light with a wavelength between 400 nm and 250 nm can be emitted. In one embodiment, the active region 173 may include a single heterostructure, a double heterostructure or a multiple quantum wells structure. In one embodiment, the active region 173 includes a multiple quantum well structure, and the active region 173 includes one or more quantum well layers and one or more barrier layers stacked one or more times alternately along the direction (third direction Z) perpendicular to the bottom surface to the top surface of the supporting substrate 12, and the energy barrier of the barrier layer is greater than that of the quantum well layer to limit the carrier distribution. In addition, the multiple quantum well layers can have the same or different material compositions and energy barriers, and this application is not limited to this. In one embodiment, the material of the active region 173 can be i-type, p-type or n-type semiconductor.

The following is an exemplary description of the manufacturing process of the light emitting element 1 according to an embodiment of the present application with reference to FIGS. 2A-2F, but the present application is not limited thereto. The manufacturing process illustrated in FIGS. 2A-2F is based on a single light emitting element 1, and the manufacturing process can also be used to obtain a plurality of light emitting elements 1.

Please refer to FIG. 2A. The semiconductor stack 203 can be grown on the growth substrate wafer 201, for example, by metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE) or sputtering or evaporation plasma deposition to sequentially grow a buffer layer 2034, a second semiconductor material layer 2032, an active material layer 2033 and a first semiconductor material layer 2031 on the growth substrate wafer 201. The second semiconductor material layer 2032 is between the buffer layer 2034 and the active material layer 2033. The active material layer 2033 is located between the first semiconductor material layer 2031 and the second semiconductor material layer 2032 .

Please refer to Figures 2B-2C. An insulating material layer 205 is formed on the surface 2031s of the first semiconductor material layer 2031. Then, the insulating material layer 205 is patterned, for example, by removing a portion of the insulating material layer 205 through a wet etching, dry etching or lift-off process to form a current blocking layer 16 and expose a portion of the surface 2031s (as shown in Figure 2C).

Next, as shown in FIG. 2D , a reflective layer 15 is formed on the exposed surface 2031s and the current blocking layer 16 by processes such as yellow light development etching, so that the reflective layer 15 and the first semiconductor material layer 2031 are electrically connected. In one embodiment, the reflective layer 15 can directly contact the first semiconductor material layer 2031 to form an ohmic contact. In one embodiment, a transparent conductive layer (not shown) is further included between the reflective layer 15 and the first semiconductor material layer 2031, and the transparent conductive layer directly contacts the first semiconductor material layer 2031 to form an ohmic contact.

Next, as shown in FIG. 2E , a first barrier layer 141 and a second barrier layer 142 are sequentially formed on the current blocking layer 16 and the reflective layer 15, for example, by deposition, sputtering or evaporation. Then, a bonding layer 13 is formed on the second barrier layer 142, and the second barrier layer 142 and the supporting substrate 12 are bonded by the bonding layer 13. In one embodiment, the bonding layer 13 can be formed on the supporting substrate 12, and then the supporting substrate 12 is bonded to the second barrier layer 142 through the bonding layer 13. In another embodiment, the bonding layer 13 may be partially formed on the second barrier layer 142 and partially formed on the supporting substrate 12, and then the two parts of the bonding layer 13 are bonded to each other so that the supporting substrate 12 is bonded to the second barrier layer 142 via the bonding layer 13. In one embodiment, the bonding of the second barrier layer 142, the bonding layer 13 and the supporting substrate 12 is performed, for example, by a hot pressing process. Then, the second electrode 11 may be formed on the supporting substrate 12 by deposition, sputtering or evaporation.

Next, as shown in FIG. 2F , the growth substrate wafer 201 on the second semiconductor material layer 2032 is removed. The removal method may be, for example, a laser lift off method or an etching method to remove the growth substrate wafer 201. In one embodiment, the buffer layer 2034 may be selectively subjected to a front etching process to remove the buffer layer 2034 and expose the second semiconductor material layer 2032. The front etching process may be dry etching or wet etching. In one embodiment, the front etching process used to remove the buffer layer 2034 is dry etching, for example, an inductively coupled plasma (ICP) etching method may be used. In one embodiment, after removing the buffer layer 2034, the surface of the second semiconductor material layer 2032 may be roughened. For example, the second semiconductor material layer 2032 may be etched to form a rough upper surface 172s. The etching process may be dry etching or wet etching. Next, the first semiconductor material layer 2031, the active material layer 2033 and the second semiconductor material layer 2032 may be patterned, and portions of the first semiconductor material layer 2031, the active material layer 2033 and the second semiconductor material layer 2032 may be removed to form the first semiconductor layer 171, the active region 173 and the second semiconductor layer 172, and a portion of the current blocking layer 16 may be exposed to form the chip separation region 207. The chip separation region 207 defines the periphery of the light emitting element 1. The method of patterning the first semiconductor material layer 2031, the active material layer 2033 and the second semiconductor material layer 2032 may include dry etching or wet etching.

Next, referring to FIG. 1B , a protective material layer (not shown) can be formed on the upper surface 172s and side walls of the second semiconductor layer 172, the side walls of the active region 173, the side walls of the first semiconductor layer 171, and the exposed upper surface of the current blocking layer 16 by deposition, sputtering or evaporation, and then a portion of the protective material layer is removed by wet etching, dry etching or a lift-off process to expose a portion of the upper surface 172s of the second semiconductor layer 172 to form an insulating layer 18. Next, a metal film layer may be formed on the insulating layer 18 by deposition, sputtering or evaporation, and the metal film layer other than the first electrode 19 may be removed by wet etching, dry etching or lift-off process to form the first electrode 19 as shown in FIG. 1B . Finally, the supporting substrate 12 below the chip separation region 207 and the stacked layers thereon may be cut along the chip separation region 207 to separate into a plurality of independent light-emitting elements 1.

FIG. 3A is a schematic top view of a light emitting element 3 according to an embodiment of the present application. FIG. 3B is a schematic cross-sectional view of the light emitting element 3 along the section line E-E' shown in FIG. 3A. The manufacturing process and structure of the light emitting element 3 are similar to those of the light emitting element 1. For the related description of the elements with the same symbols, similar manufacturing processes and structures, please refer to the description and drawings of the light emitting element 1. No further description will be given. The differences will be described later.

Please refer to Figures 3A-3B at the same time. The insulating layer 18 of the light-emitting element 3 has a first opening 18a and a second opening 18b, and the second opening 18b exposes a portion of the upper surface 172s of the second semiconductor layer 172. The second opening 18b is located on the second semiconductor layer 172 and is not covered by the first electrode 19. In this embodiment, the insulating layer 18 is patterned by the second opening 18b to form a patterned insulating layer corresponding to the structure of the first electrode 19. The conductive parts 190a1, 190a2, 190a3, 190a4, the extension parts 191, 192, and the electrode pad 20 can be respectively arranged corresponding to the outer frame part 190 of the first electrode 19, so that the insulating layer 18 has a pattern similar to part or all of the first electrode 19. The second opening 18b can be defined as a closed opening according to the arrangement of the insulating layer 18. In one embodiment, as shown in the schematic diagram of the upper view of Figure 3A, the insulating layer 18 below the extension parts 191 and 192 is not connected to the insulating layer 18 below the outer frame part 190, defining a non-closed second opening 18b. As shown in FIG. 3B , an insulating layer 18 is disposed between any two adjacent second openings 18b. In another embodiment, the insulating layer 18 below any extension portion 191, 192 is connected to the insulating layer 18 below the outer frame portion 190 to define a closed second opening 18b. The light-emitting element in the present application has a notch 21, so at least one of the second openings 18b in the insulating layer 18 disposed in the present embodiment is a non-closed second opening 18b, and the others may be applied according to the conditions of the light-emitting element and may include one or more closed second openings 18b. In one embodiment, as shown in the cross-sectional schematic diagram of FIG. 3B , the first opening 18a and the second opening 18b are disposed along the first direction X. In one embodiment, the first opening 18a and the second opening 18b may be arranged alternately along the first direction X. The first opening 18a has a width W2 in the first direction X. In one embodiment, the width W2 is between 2 micrometers (μm) and 10 micrometers (μm), or between 3 micrometers (μm) and 5 micrometers (μm). The widths of the plurality of second openings 18b may be the same or different from each other. The second opening 18b has a width W3 in the first direction X. In one embodiment, the width W3 is between 180 micrometers (μm) and 200 micrometers (μm). ) to 250 microns ( ), or 200 microns ( ) to 220 microns ( ). The width W3 of the second opening 18b in the first direction X is greater than the width W2 of the first opening 18a in the first direction X. The ratio of the width W2 of the first opening 18a in the first direction X to the width W3 of the second opening 18b in the first direction X is between 1:45 and 1:60, or between 1:50 and 1:55.

3A and 3B, the plurality of current blocking layers 16 may partially overlap or not overlap the second opening 18b of the insulating layer 18 in the direction perpendicular to the top surface of the supporting substrate 12 (third direction Z). In one embodiment, the plurality of current blocking layers 16 do not overlap the second opening 18b of the insulating layer 18 in the third direction Z.

The difference in the manufacturing process between the light emitting element 3 of this embodiment and the light emitting element 1 of the above embodiment mainly lies in the step of forming the insulating layer 18. Referring to FIG. 2F, a protective material layer (not shown) can be formed on the upper surface 172s and sidewalls of the second semiconductor layer 172, the sidewalls of the active region 173, the sidewalls of the first semiconductor layer 171, and the exposed upper surface of the current blocking layer 16 by deposition, sputtering or evaporation. Then, a yellow light development process can be used in combination with a wet etching, dry etching or a lift-off process to remove the protective material layer outside the predetermined opening. Finally, a reactant, such as a photoresist stripper, may be used to remove the photoresist to form an insulating layer 18 having a first opening 18a and a second opening 18b.

According to this embodiment, since the insulating layer 18 has a second opening 18b to expose a portion of the upper surface 172s of the second semiconductor layer 172, the area of the upper surface 172s of the second semiconductor layer 172 covered by the insulating layer 18 can be reduced, which can reduce the light absorption of the insulating layer 18 and thereby improve the light extraction efficiency of the light-emitting element 3.

In the above-mentioned embodiments, in the process of forming the first electrode 19, a photoresist can be formed by a yellow light development process, and then the metal film layer outside the first electrode 19 can be removed by wet etching, dry etching or lift-off. In one embodiment, in the step of forming the first electrode 19 by the photoresist and lift-off process, a photoresist is firstly set on the insulating layer 18 or the second semiconductor layer 172 outside the predetermined position of forming the first electrode 19, and a metal film layer is evaporated on the photoresist and the insulating layer 18 not covered by the photoresist. Then, the metal film layer located above the photoresist can be removed by lift-off, and then the photoresist is removed to form the first electrode 19. In another embodiment, in the step of forming the first electrode 19 by a photoresist-etching process, a metal film layer is first formed on the insulating layer 18 and the second semiconductor layer 172 over a whole surface, and then a photoresist is placed on the metal film layer at the predetermined position for forming the first electrode 19, and then the metal film layer not covered by the photoresist is removed by wet etching or dry etching, and finally the photoresist on the metal film layer is removed to expose the remaining metal film layer to form the first electrode 19.

However, when the metal film layer located above the photoresist is removed by the above lift-off method, part of the metal film layer will remain on the photoresist surface of the light-emitting element 1 and will not be removed cleanly. After the subsequent photoresist removal process, the metal film layer originally remaining on the photoresist will remain on the light-emitting area (the surface of the insulating layer 18 or the second semiconductor layer 172) of the light-emitting element 1 after the photoresist is removed, causing the problem of metal shading and affecting the light-emitting efficiency of the light-emitting element 1. Similarly, when the metal film layer not covered by the photoresist is removed by etching, it is easy for the metal film layer to remain due to incomplete reaction with the etchant and cannot be removed, causing the problem of residual metal shading. In order to avoid the problem of light blocking caused by the metal film remaining on the light-emitting element 1, how to completely remove the metal film to be removed is the primary issue to be solved.

In one embodiment, when removing the metal film layer not covered by the photoresist by wet etching, a notch 21 is set in the outer frame portion 190 of the first electrode 19, so that the corresponding photoresist thereon also has a notch formed in the peripheral area. Therefore, the etchant can have a better cyclic reaction with the inside and outside of the outer frame portion 190 through the notch to increase its etching efficiency, so that the metal film layer to be removed inside and outside the outer frame portion 190 is removed cleanly.

In another embodiment, when the metal film layer above the photoresist is removed by lifting off, a notch 21 is provided in the outer frame portion 190 of the first electrode 19, so that the metal film layer to be removed on the photoresist inside and outside the outer frame portion 190 can be connected to the inner and outer metal film layers of the outer frame portion 190 through a connected area at the notch 21. When the metal film layer is lifted off with an adhesive film, such as a blue film, the metal film layer to be removed on the photoresist is connected at the notch 21, so that when the blue film is lifted off by adhesion, the contact area between the blue film and the inner and outer metal film layers as a whole is increased, thereby allowing the metal film layer to be removed inside and outside the outer frame portion 190 of the light-emitting element 1 to be lifted off together and completely removed. In addition, a notch 21 is provided in the outer frame portion 190 of the first electrode 19. After the metal film layer is removed, in the process of removing the photoresist, the reactant for removing the photoresist, such as a photoresist stripper, can diffuse from the position of the notch 21 inside and outside, so that the reactant and the photoresist to be removed can fully react, thereby completely removing the photoresist, thereby improving the process yield of the light-emitting element 1 and the reliability of the light-emitting element 1.

FIG. 4 is a top view schematic diagram of a light emitting element 4 according to an embodiment of the present application. The manufacturing process and structure of the light emitting element 4 are similar to those of the light emitting elements 1 and 3. For the related descriptions of the elements with the same symbols, similar manufacturing processes and structures, please refer to the descriptions and drawings of the light emitting elements 1 and 3. The descriptions will not be repeated here. The differences will be described later.

Please refer to Figure 4. The first electrode 19 of the light-emitting element 4 includes a first extension portion 191 and a second extension portion 192, which respectively have first ends 191b1 and 192b1 connected to the outer frame portion 190, and second ends 191b2 and 192b2 not connected to the outer frame portion 190. Among them, the second end 191b2 of the first extension portion 191 is set corresponding to the notch 21. In one embodiment, in the second direction Y, the first extension portion 191 and/or the second extension portion 192 may have a variable width. In one embodiment, the first extension portion 191 and/or the second extension portion 192 has a gradually decreasing width in the direction opposite to the second direction Y. One or more conductive portions of the outer frame portion 190 may have a variable width. In one embodiment, the third conductive portion 190a3 and/or the fourth conductive portion 190a4 of the outer frame portion 190 has a gradually decreasing width in a direction opposite to the second direction Y. The electrode pad 20 is located between the first conductive portion 190a1 of the outer frame portion 190 and the second extension portion 192. In this embodiment, the number of the notch 21 is exemplified as one, but is not limited thereto. As described above, whether in the step of forming the first electrode 19 by the photoresist and lift-off process, or in the step of forming the first electrode 19 by the photoresist and etching process, a notch 21 can be provided in the outer frame 190, and in the structure where the second ends 191b2, 192b2 of some or all of the extensions 191, 192 surrounded by the outer frame 190 are disconnected from the outer frame 190, in the process of removing the metal film layer and the photoresist as described above, the notch 21 can provide a similar function. In this embodiment, the relevant description between the insulating layer 18 and the second opening 18b is referred to the description and drawings of the light-emitting element 3, and will not be repeated here.

According to different applications, the light-emitting elements 1, 3, and 4 may be packaged. Please refer to FIG. 5, which is a cross-sectional schematic diagram of a light-emitting package 80 according to an embodiment of the present application. The light-emitting package 80 according to the embodiment may include a packaging wall 805, a packaging substrate 801, external electrodes 813 and 814 mounted on the packaging substrate 801, light-emitting elements 1, 3, and 4 mounted in the packaging wall 805 and electrically connected to the external electrodes 813 and 814, and a packaging material 840 (which may include a phosphor to surround the light-emitting elements 1, 3, and 4). The external electrodes 813 and 814 are electrically insulated from each other, and provide power to the light-emitting elements 1, 3, and 4 through the wire 830. In addition, the external electrodes 813 and 814 can reflect the light emitted from the light emitting elements 1, 3, 4 to improve the light extraction efficiency, and discharge the heat emitted from the light emitting elements 1, 3, 4 to the outside. The light emitting package 80 can be applied to a backlight unit, a lighting unit, a display device, an indicator, a lamp, a street lamp, a lighting device for a vehicle, a display device for a vehicle, or a smart watch, but is not limited thereto.

FIG. 6 is a schematic diagram of a light-emitting device 90 according to an embodiment of the present application. The light-emitting device 90 includes a lampshade 901, a reflector 902, a light-emitting module 905, a lamp holder 906, a heat sink 907, a connecting portion 908, and an electrical connecting element 909. The light-emitting module 905 includes a supporting portion 903 and a plurality of light-emitting units 904 located on the supporting portion 903. The plurality of light-emitting units 904 may be the light-emitting elements 1, 3, 4 or the light-emitting package 80 in the aforementioned embodiments.

In summary, although the present invention has been disclosed as above by the embodiments, it is not intended to limit the present invention. Those with ordinary knowledge in the technical field to which the present invention belongs can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the attached patent application.

1,3,4: light-emitting element 11: second electrode 12: supporting substrate 13: bonding layer 14: barrier layer 15: reflective layer 16: current blocking layer 17: semiconductor stack 18: insulating layer 18a: first opening 18b: second opening 18a1: first end point 18a2: second end point 18a3: third end point 19: first electrode 20: electrode pad 21: notch 22: virtual connection 80: light-emitting package 90: light-emitting device 121: first side 122: second side 141: first barrier layer 142: second barrier layer 171: first semiconductor layer 172: second semiconductor layer 173: active region 171s, 172s: surface 190: outer frame 190a1: first conductive portion 190a2: second conductive portion 190a3: third conductive portion 190a4: fourth conductive portion 190b1: first end 190b2: second end 191: first extension portion 191b1: first end 191b2: second end 192: second extension portion 192b1: first end 192b2: second end 201: growth substrate wafer 203: semiconductor stack 205: insulating material layer 2031: First semiconductor layer 2031s: Surface 2032: Second semiconductor layer 2033: Active region 2034: Buffer layer 207: Chip separation region 801: Package substrate 805: Package wall 813,814: External electrodes 830: Wires 840: Package material 901: Lampshade 902: Reflector 903: Carrier 904: Light-emitting unit 905: Light-emitting module 906: Lamp holder 907: Heat sink 908: Connector 909: Electrical connection element D1,D2,D3: Distance L1: Length W1, W2, W3, W4: width X: first direction Y: second direction Z: third direction

FIG. 1A is a schematic diagram showing a top view of a light-emitting element 1 according to an embodiment of the present application. FIG. 1B is a schematic diagram showing a cross section of the light-emitting element 1 along the section line B-B' shown in FIG. 1A. FIG. 1C is a schematic diagram showing a cross section of the light-emitting element 1 along the section line C-C' shown in FIG. 1A. FIG. 1D is an enlarged schematic diagram showing the light-emitting element 1 shown in the region D shown in FIG. 1A. FIG. 1E is an enlarged schematic diagram showing the insulating layer 18 shown in the region D shown in FIG. 1A. FIG. 2A-2F are schematic diagrams showing partial manufacturing steps of the light-emitting element 1 according to an embodiment of the present application. FIG. 3A is a schematic diagram showing a top view of the light-emitting element 3 according to an embodiment of the present application. FIG. 3B is a schematic cross-sectional view of the light-emitting element 3 along the section line E-E' shown in FIG. 3A. FIG. 4 is a schematic top view of the light-emitting element 4 according to an embodiment of the present application. FIG. 5 is a schematic cross-sectional view of the light-emitting package 80 according to an embodiment of the present application. FIG. 6 is a schematic view of the light-emitting device 90 according to an embodiment of the present application.

1: Light-emitting element

18: Insulation layer

19: First electrode

190: Outer frame

190a1: First conductive part

190a2: Second conductive part

190a3: The third conductive part

190a4: The fourth conductive part

191: First extension

191b1: First end

191b2: Second end

192: Second extension

192b1: First end

192b2: Second end

20:Electrode pad

21: Gap

L1: Length

X: First direction

Y: Second direction

Z: Third direction

Claims (19)

A light-emitting element comprises: A supporting substrate having a first side and a second side opposite to the first side; A semiconductor stack located on the first side; wherein the semiconductor stack comprises a first semiconductor layer, a second semiconductor layer located on the first semiconductor layer, and an active region located between the first semiconductor layer and the second semiconductor layer; An insulating layer located on the second semiconductor layer; wherein, in a cross-sectional view, the insulating layer comprises one or more first openings, and the one or more first openings are arranged on the second semiconductor layer along a first direction; A first electrode, located on the one or more first openings, and electrically connected to the second semiconductor layer through the one or more first openings; and A second electrode, located on the second side; Wherein the first electrode includes an outer frame portion, and the outer frame portion includes one or more notches. A light-emitting element as described in claim 1, wherein the outer frame portion includes one or more first ends and one or more second ends, and each of the one or more first ends and each of the one or more second ends defines each of the one or more notches. The light-emitting element as described in claim 2, wherein there is a virtual connection between the first end and the second end, and the outer frame and the virtual connection form a closed pattern. The light-emitting element as described in claim 2, wherein the first electrode further comprises one or more first extension portions, which are surrounded by the outer frame portion and extend along a second direction; wherein the one or more first extension portions respectively comprise two ends, one end is connected to the outer frame portion, and the other end is separated from the first end and the second end by the one or more notches. The light-emitting element as described in claim 4, wherein the first electrode further comprises a second extension portion, which is surrounded by the outer frame portion and extends along the second direction; wherein the second extension portion comprises two ends, both of which are connected to the outer frame portion. The light-emitting element as described in claim 4, wherein the first electrode further comprises: an electrode pad connected to the outer frame; wherein the first electrode further comprises one or more second extensions, which are surrounded by the outer frame and extend along the second direction, wherein the one or more second extensions respectively comprise two ends, one end connected to the electrode pad, and the other end spaced apart from the outer frame. A light-emitting element as described in claim 2, wherein the one or more first openings of the insulating layer include a first end point and a second end point which are arranged corresponding to and opposite to the one or more notches, a first distance is provided between the first end and the second end of the outer frame portion, a second distance is provided between the first end point and the second end point of the one or more first openings, and the first distance is smaller than the second distance. A light-emitting element as described in claim 4, wherein a width of the one or more first openings in the first direction is smaller than a width of the one or more first extensions in the first direction. The light emitting device as claimed in claim 4, wherein the width of the one or more first extension portions in the first direction is between 10 Up to 25 . The light-emitting element as described in claim 1, wherein the first electrode further covers a portion of the insulating layer. The light-emitting element as described in claim 1, wherein the second semiconductor layer has a rough upper surface. The light-emitting element as described in claim 1 further comprises: A current blocking layer located between the first semiconductor layer and the supporting substrate; wherein the current blocking layer is arranged corresponding to the first electrode. A light-emitting element as described in claim 12, wherein the insulating layer extends to cover the side surface of the semiconductor stack and a portion of the current blocking layer. The light-emitting element as described in claim 1 further comprises: a current blocking layer located between the first semiconductor layer and the supporting substrate; a reflective layer located between the current blocking layer and the supporting substrate; and a barrier layer located between the reflective layer and the supporting substrate; wherein the current blocking layer contacts the barrier layer and the reflective layer. The light-emitting element as described in claim 1, wherein the insulating layer further comprises: One or more second openings located on the second semiconductor layer, and the one or more first openings and the one or more second openings are arranged along the first direction. A light-emitting element as described in claim 15, wherein the one or more second openings expose a portion of the second semiconductor layer and are not covered by the first electrode. The light-emitting element as described in claim 15, wherein the one or more first openings have a first width in the first direction, the one or more second openings have a second width in the first direction, and the first width is smaller than the second width. The light-emitting element as described in claim 17, wherein the ratio of the first width to the second width is between 1:45 and 1:60. The light-emitting element as described in claim 15 further comprises: A current blocking layer, located between the first semiconductor layer and the supporting substrate; wherein the current blocking layer is arranged corresponding to the first electrode, and the current blocking layer does not overlap the one or more second openings in a third direction perpendicular to a top surface of the supporting substrate.

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