TW202426944A - Automatic inspection method for through hole vias and connector pins of pcb - Google Patents

Abstract

An automatic inspection method for through hole vias and connector pins of PCB, implemented by a computer device, comprising the following steps: (A) the computer device obtains at least one target circuit board design data from a plurality of circuit board design data according to an inspection and screening data; (B) the computer device determines that the at least one target circuit board design data corresponds to a via group type or a connector pin type; (C) when the computer device determines that it corresponds to the via group type, for each target circuit board design data, the computer device generates at least one via group inspection result information according to the target circuit board design data and at least one via group inspection rule; and (D) when the computer device determines that it corresponds to the connector pin type, for each target circuit board design data, the computer device generates a connector pin inspection result information based on the target circuit board design data and a connector pin inspection rule.

Description

Automatic inspection method for through holes and connector pins of printed circuit boards

The present invention relates to an inspection method, in particular to an automatic inspection method for through holes and connector pins of a printed circuit board.

Generally, when laying out a printed circuit board (PCB), impedance discontinuity often occurs at vias and connector pins. Therefore, after the PCB design is completed, SI engineers need to visually inspect the vias and connector pins to ensure that the design of the vias and connector pins is correct.

However, there are a large number of through holes and connector pins on a PCB, and manual inspection is often outdated, and it is inevitable that some of them will be missed.

Therefore, the object of the present invention is to provide a method for automatically inspecting through holes and connector pins of a printed circuit board.

Therefore, the method for automatically checking through holes and connector pins of a printed circuit board of the present invention is implemented by a computer device, which stores a plurality of circuit board design data corresponding to a plurality of through hole groups and a plurality of connector pins, a check and screening data, at least one through hole group check rule, and a connector pin check rule. Each circuit board design data corresponds to a through hole group or a connector pin of a differential pair line electrical connection. The check and screening data includes a specified type, which is a through hole group type or a connector pin type. The method includes step (A), step (B), step (C), and step (D).

In the step (A), the computer device obtains at least one target circuit board design data that meets the inspection and screening data from the circuit board design data according to the inspection and screening data.

In the step (B), the computer device determines that the at least one target circuit board design data corresponds to the through hole group type or the connector pin type.

In the step (C), when it is determined that the at least one target circuit board design data corresponds to the through hole group type, for each target circuit board design data, the computer device generates at least one through hole group inspection result information corresponding to the target circuit board design data based on the target circuit board design data and the at least one through hole group inspection rule, and the at least one through hole group inspection result information corresponds to the at least one through hole group inspection rule respectively.

In the step (D), when it is determined that the at least one target circuit board design data corresponds to the connector pin type, for each target circuit board design data, the computer device generates connector pin check result information corresponding to the target circuit board design data based on the target circuit board design data and the connector pin check rule.

The effect of the present invention is that: by using the computer device to determine whether the at least one target circuit board design data corresponds to the through hole group type or the connector pin type, the at least one through hole group inspection result information or the connector pin inspection result information is automatically generated for each target circuit board design data, thereby greatly saving the time of manual inspection and reducing the probability of error.

Before the present invention is described in detail, it should be noted that similar components are represented by the same reference numerals in the following description.

Referring to FIG. 1 , a computer system for implementing an embodiment of the method for automatically inspecting through holes and connector pins of a printed circuit board of the present invention is described. The computer system includes a storage unit 11 and a processing unit 12 electrically connected to the storage unit 11. The computer system is, for example, a desktop computer, a tablet computer, a notebook computer, a server, or a smart phone, but is not limited thereto. The through hole (via) is a blind via, a buried via, a combination of the above two (at the same coordinate), or a through hole (through hole via), but is not limited thereto.

The storage unit 11 stores a plurality of circuit board design data respectively corresponding to a plurality of through hole groups and a plurality of connector pins, a plurality of through hole group inspection preset data respectively corresponding to the through hole groups, an inspection screening data, a first through hole group inspection rule, a second through hole group inspection rule, and a connector pin inspection rule.

Each circuit board design data corresponds to a through hole group or a connector pin electrically connected to a differential pair line. Each circuit board design data includes a line name, an impedance value, coordinate information related to the through hole group or the connector pin on the printed circuit board, at least one passing layer code related to the number of layers passed by the differential pair line, multiple all layer codes related to all layers of the printed circuit board, and multiple layer codes where the clear area is located. Among them, the at least one passing layer code has a starting point layer code related to a preset check starting point layer of the differential pair line, wherein the check starting point layer is the electrical connection between the differential pair line and the through hole group or the connector pin.

It is worth mentioning that since the differential pair circuit is two parallel signal lines of approximately equal length, one signal line transmits a positive signal and the other signal line transmits a negative signal, each through hole group has two through holes for allowing the signal lines to pass through respectively.

It is worth noting that in the present embodiment, the printed circuit board has a total of 12 layers, and the layer number codes are, for example, Top, L2, L3, L4, L5, L6, L7, L8, L9, L11, and Bottom. Each layer number code corresponds to a board layer type, and the board layer type is, for example, a ground layer type, a power layer type, or a routing layer type, where L2 corresponds to the ground layer type, L4 corresponds to the power layer type, and the Top, L3, L5~L11 and Bottom layers all correspond to the routing layer type. In other embodiments, the total number of layers of the printed circuit board and the board layer type layer corresponding to each layer number code may be slightly different according to the board layer configuration of each manufacturer, but is not limited to this.

If a circuit board design data corresponds to a through hole group of a differential pair line electrical connection, the circuit board design data further includes at least one avoidance area size parameter corresponding to the at least one through hole layer number code, and at least one through hole center distance corresponding to the at least one through hole layer number code.

The through hole group inspection preset data respectively correspond to the through hole groups, and each through hole group inspection preset data includes an ideal avoidance area size parameter and an ideal through hole center distance.

It should be noted that in the present embodiment, the avoidance area is in the shape of a capsule, and the avoidance area size parameters of the circuit board design data and the ideal avoidance area size parameters of the through hole group inspection preset data are the short axis of the avoidance area, but are not limited thereto.

The inspection and screening data includes a specified line name, a specified type, and a specified impedance value.

The first through-hole group inspection rule is whether at least one avoidance area size parameter and at least one through-hole center distance of a circuit board design data meet a target through-hole group inspection preset data. The second through-hole group inspection rule is whether, among all the multiple layer codes of the circuit board design data, except for at least one through layer code of the circuit board design data, the layer codes corresponding to the multiple through-hole group inspection board layer types are included in the layer codes where the multiple clear areas of the circuit board design data are located, wherein the through-hole group inspection board layer types are selected according to the impedance value of the corresponding differential pair line. At least two of the routing layer type, the power layer type and the ground layer type. In the present embodiment, the specified impedance value of the differential pair is 85 ohms, and the corresponding through-hole group inspection board layer types include the power layer type and the ground layer type; in another embodiment, the impedance value corresponding to the differential pair is 100 ohms, and the through-hole group inspection board layer types corresponding to the differential pair include all board layer types, that is, the through-hole group inspection board layer types include routing layer types, power layer types and ground layer types. The connector pin check rule is whether all target layer codes adjacent to a starting point layer code of the circuit board design data and meeting a connector pin check layer type are included in layer codes of multiple clear areas of the circuit board design data among multiple layer codes of a circuit board design data, wherein the connector pin check layer type is a ground layer.

It is worth noting that in this embodiment, the circuit board design data is obtained from a circuit board layout drawing file (PCB layout BRD file), and the inspection filter data is set by the user. The user indicates the differential pair line to be inspected by setting at least one of a specified line name, a specified type, and a specified impedance value. The specified type is a through hole group type or a connector pin type. The clear area is a clear area where no conductive material is set and is located in a layer other than the layer through which the differential pair line passes and is used to isolate the position of the through hole group or the connector pin. , the avoidance area is an isolation area without conductive material, which is located on the layer through which the differential pair lines pass and is used to isolate the pads of the through-hole group from other conductive wires or blocks with conductive materials, a clear area and an avoidance area such as an anti-pad. In other embodiments, the storage unit 11 also stores other circuit board design data that is different from the circuit board design data and is related to multiple other circuits other than the differential pair lines, but is not limited to this.

1 and 2, the embodiment of the method for automatically inspecting through holes and connector pins of a printed circuit board of the present invention is described below. The steps included in the embodiment are described below.

In step 21, the processing unit 12 obtains at least one target circuit board design data that meets the inspection and screening data from the circuit board design data according to the inspection and screening data.

In step 22, the processing unit 12 determines whether the at least one target circuit board design data corresponds to the through hole group type or the connector pin type. When it is determined that the at least one target circuit board design data corresponds to the through hole group type, the process proceeds to steps 23 and 25; and when it is determined that the at least one target circuit board design data corresponds to the connector pin type, the process proceeds to step 26.

In step 23, the processing unit 12 obtains at least one target via group inspection preset data respectively corresponding to the at least one target circuit board design data from the via group inspection preset data.

In step 24, for each target circuit board design data, the processing unit 12 generates first via group inspection result information corresponding to the target circuit board design data according to the target circuit board design data, a target via group inspection preset data corresponding to the target circuit board design data, and the first via group inspection rule.

Specifically, for each target circuit board design data, the processing unit 12 compares whether at least one avoidance area size parameter of the target circuit board design data is consistent with an ideal avoidance area size parameter of the target through-hole inspection preset data, and compares whether at least one through-hole center distance of the target circuit board design data is consistent with an ideal through-hole center distance of the target through-hole inspection preset data, so as to generate the first through-hole group inspection result information. If the at least one avoidance area size parameter is consistent with the ideal avoidance area size parameter, and the at least one through-hole center distance is consistent with the ideal through-hole center distance, the first through-hole group inspection result information indicates a pass. If one of the at least one avoidance area size parameters is inconsistent with the ideal avoidance area size parameter, or one of the at least one through-hole center distance is inconsistent with the ideal through-hole center distance, then the first through-hole group inspection result information indicates an error. During the inspection and comparison, when the difference between the two is less than the allowable error range, the two are still considered to be consistent. For example: if there is a difference of less than 1 mil, the two are still determined to be consistent. The allowable error range can also be 2 mils or 0.5 mils, but is not limited to this.

It is worth mentioning that in step 24, for each target circuit board design data, at least one passing layer code of the target circuit board design data is the first checking layer code.

In step 25, for each target via inspection preset data, the processing unit 12 generates second via group inspection result information corresponding to the target circuit board design data according to the target circuit board design data and the second via group inspection rule.

With reference to FIG. 3 , step 25 includes the following sub-steps.

In sub-step 251, for each target circuit board design data, the processing unit 12 deducts the at least one passing layer code from the layer codes of the target circuit board design data to obtain multiple candidate inspection layer codes, and then screens out multiple second inspection layer codes corresponding to the through-hole group inspection layer types from the candidate inspection layer codes.

In sub-step 252, for each target circuit board design data, the processing unit 12 determines whether the second inspection layer number codes are included in the layer number codes where the plurality of clear areas of the target circuit board design data are located, so as to generate the second through hole group inspection result information. Among them, if the second inspection layer number codes are included in the layer number codes where the clear space areas are located, it means that the layers corresponding to the second inspection layer number codes have corresponding clear space areas, and the second through-hole group inspection result information indicates a pass; if the second inspection layer number codes are not included in the layer number codes where the clear space areas are located, it means that the layers corresponding to the second inspection layer number codes do not have corresponding clear space areas, and the second through-hole group inspection result information indicates an error.

It is worth noting that in other embodiments, the storage unit 11 may only store the first through hole group inspection rule or the second through hole group inspection rule, that is, in step 22, when it is determined that the at least one target circuit board design data corresponds to the through hole group type, the process only performs steps 23 and 24 and only generates the first through hole group inspection result information, or only performs step 25 and only generates the second through hole group inspection result information.

In step 26, for each target circuit board design data, the processing unit 12 generates connector pin check result information corresponding to the target circuit board design data according to the target circuit board design data and the connector pin check rule.

With reference to FIG. 4 , step 26 includes the following sub-steps.

In sub-step 261, for each target circuit board design data, the processing unit 12 obtains a third inspection layer code adjacent to the start point layer code and corresponding to the connector pin inspection layer type according to the start point layer code of the target circuit board design data.

In sub-step 262, for each target circuit board design data, the processing unit 12 determines whether the third check layer number code is included in the layer number codes where multiple clear areas of the target circuit board design data are located, so as to generate the connector pin check result information. Among them, if the third check layer number code is included in the layer number code where the clear space area is located, it means that the layer number corresponding to the third check layer number code has a corresponding clear space area, and the connector pin inspection result information indicates a pass; if the third check layer number code is not included in the layer number code where the clear space area is located, it means that the layer number corresponding to the third check layer number code has no corresponding clear space area, and the connector pin inspection result information indicates an error.

It is noteworthy that in the present embodiment, each inspection result information includes coordinate information of the circuit board design data corresponding to the inspection result information, the line name of the circuit board design data corresponding to the inspection result information, the starting point layer code of the circuit board design data corresponding to the inspection result information, at least one inspection layer code, and an inspection result indicating a pass or error, but is not limited to this.

For example, the designated line name of the inspection and screening data is, for example, P5E_SSD, the designated type is, for example, a through-hole group, and the designated impedance value is, for example, 85 ohms (a designated impedance value commonly used in differential pair wiring). In step 21, the processing unit 12 obtains a first target circuit board design data that meets the inspection and screening data, and a second target circuit board design data. The line name of the first target circuit board design data is P5E_SSD0_RX_D (N/P＜2＞), the coordinate information is (1037.35 38.01) and (1058.57 59.23), the passed layer code is Bottom and L11, that is, the first check layer code is Bottom and L11, where the starting point layer code is Bottom, the layer code of the clear area is Top, L2-10, the avoidance area size parameters located at the first check layer code Bottom and L11 are both 40mils, and the through hole center distance is 40mils. The line name of the second target circuit board design data is P5E_SSD0_RX_D (N/P＜2＞), the coordinate information is (15243.74 37.74), and (15264.96 58.96), and the through layer code group is Bottom, L6-7, 9, 11, that is, the first check layer code is Bottom, L6-7, 9, 11, where the starting point board layer code is Bottom, the layer code of the clear area is Top, L2-5, L8, L10, the avoidance area size parameters located at the first check layer code Bottom, L6-7, 9, 11 are all 40mils, and the through hole center distance is all 40mils. In step 22, the processing unit 12 determines that the first target circuit board design data and the second target circuit board design data correspond to the through hole group type. In step 23, the processing unit 12 obtains the first target through hole group inspection preset data and the second target through hole group inspection preset data corresponding to the first target circuit board design data and the second target circuit board design data, respectively, from the through hole group inspection preset data, and the first and second target through hole group inspection preset data include the same ideal impedance of 85 ohms, the ideal through hole center distance of 40 mils, and the ideal clear area size parameter of 40 mils (hereinafter represented as 85/40/40). In step 24, for the first target circuit board design data, the processing unit 12 compares whether the area size parameters corresponding to the pass layer codes Bottom and L11 are all 40 mils, and compares whether the through hole center distances corresponding to the pass layer codes Bottom and L11 are all 40 mils, so as to generate a first through hole group inspection result information (as shown in the second row of Table 1 below). Similarly, in step 24, for the second target circuit board design data, the processing unit 12 compares whether the avoidance area size parameters corresponding to the pass layer codes Bottom, L6-7, 9, 11 are all 40 mils, and compares whether the through hole center distances corresponding to the pass layer codes Bottom, L6-7, 9, 11 are all 40 mils, to generate another first through hole group inspection result information (as shown in the third row of Table 1 below). Among them, All Layers Pass means that all layers of the inspection have passed. In step 25, for the first target circuit board design data, the processing unit 12 deducts the passing layer codes L11 and Bottom from all the layer codes Top, L2-11, and Bottom to obtain candidate inspection layer codes Top and L2-10, and then selects the inspection layers corresponding to the through hole groups from the candidate inspection layer codes Top and L2-10. Check the board layer type (the specified impedance value is 85 ohms and the corresponding through hole group inspection type is the ground layer type and the power layer type) and the second inspection layer number codes are L2 and L4, and then determine whether the second inspection layer number codes L2 and L4 are included in the layer number codes of the clear space areas, which are Top, L2-10, to generate a second through hole group inspection result information (as shown in the 4th column of Table 1 below). Similarly, in step 25, for the second target circuit board design data, the processing unit 12 deducts the passing layer codes L6-7, 9, 11 and Bottom from all the layer codes Top, L2-11, Bottom to obtain candidate inspection layer codes Top, L2-5, 8, and then selects the corresponding layer codes from the candidate inspection layer codes Top, L2-5, 8. The second inspection layer codes of the through hole group inspection board layer type (the through hole group inspection type corresponding to the specified impedance value of 85 ohms is the ground layer type and the power layer type) are L2 and L4, and then it is determined whether the second inspection layer codes L2 and L4 are included in the layer code of the clear area, Top, L2-10, to generate another second through hole group inspection result information (as shown in the 5th column of Table 1 below). Table 1 Line Name Starting point layer code Coordinate information Check layer code Examination results P5E_SSD0_RX_D(N/P＜2＞) Bottom (1037.35 38.01);(1058.57 59.23) Bottom, L11 85/40/40/All Layers Pass P5E_SSD0_RX_D(N/P＜2＞) Bottom (15243.74 37.74);(15264.96 58.96) Bottom, L6-7,9,11 85/40/40/All Layers Pass P5E_SSD0_RX_D(N/P＜2＞) Bottom (1037.35 38.01);(1058.57 59.23) L2, 4 Via Void Pass P5E_SSD0_RX_D(N/P＜2＞) Bottom (15243.74 37.74);(15264.96 58.96) L2, 4 Via without Void

For another example, the designated line name of the inspection and screening data is, for example, P5E_SSD11, the designated type is, for example, a connector pin, and the designated impedance value is, for example, 85 ohms. In step 21, a third target circuit board design data and a fourth target circuit board design data that meet the inspection and screening data are obtained. The line name of the third target circuit board design data is P5E_SSD11_C_TX_DN<2>, the coordinate information is (15644.41 626.62), the passing layer code and the starting point board layer code are Top, and the layer codes of the clear area are L2-11 and Bottom. The line name of the fourth target circuit board design data is P5E_SSD11_C_TX_DP＜2＞, the coordinate information is (15644.41 626.62), the layer code and the starting point layer code are Top, and the layer codes of the clear area are L2-11 and Bottom. In step 22, the processing unit 12 determines that the third target circuit board design data and the fourth target circuit board design data correspond to the connector pin type. In step 26, for the third target circuit board design data, the processing unit 12 obtains a third check layer code L2 adjacent to the starting point layer code Top and corresponding to the ground layer type, and then determines whether the third check layer code L2 is included in the layer codes L2-11 and Bottom where the clear areas are located to generate a connector pin check result information (as shown in the second row of Table 2 below). Similarly, in step 26, for the fourth target circuit board design data, the processing unit 12 obtains a third check layer code L2 adjacent to the starting point layer code Top and corresponding to the ground layer type, and then determines whether the third check layer code L2 is included in the layer codes L2-11 and Bottom where the clear areas are located, so as to generate another connector pin check result information (as shown in the third row of Table 2 below). Table 2 Line Name Starting point layer code Coordinate information Check layer code Examination results P5E_SSD11_C_TX_DN＜2＞ TOP (15612.91 626.62) L2 SMD Pin without Void P5E_SSD11_C_TX_DP＜2＞ TOP (15644.41 626.62) L2 SMD Pin without Void

In summary, the method for automatically inspecting through-holes and connector pins of a printed circuit board of the present invention determines whether the at least one target circuit board design data corresponds to the through-hole group type or the connector pin type by the processing unit 12. When the at least one target circuit board design data corresponds to the through-hole group type, the processing unit 12 obtains the at least one target through-hole group inspection preset data, and generates at least one first through-hole group inspection result information according to the at least one target circuit board design data, the target through-hole inspection preset data corresponding to the at least one target circuit board design data, and the first through-hole group inspection rule, and then generates at least one second through-hole group inspection result information according to the at least one target circuit board design data and the second through-hole group inspection rule. When the at least one target circuit board design data corresponds to the connector pin type, at least one connector pin inspection result information is generated according to the at least one target circuit board design data and the connector pin inspection rule. Thus, the processing unit 12 automatically generates the inspection result, which greatly saves the time of manual inspection and reduces the probability of error, so the purpose of the present invention can be achieved.

However, the above is only an embodiment of the present invention and should not be used to limit the scope of implementation of the present invention. All simple equivalent changes and modifications made according to the scope of the patent application of the present invention and the content of the patent specification are still within the scope of the present patent.

11: Storage unit 12: Processing unit 21~26: Steps 251, 252: Sub-steps 261, 262: Sub-steps

Other features and effects of the present invention will be clearly presented in the implementation method with reference to the drawings, in which: FIG. 1 is a block diagram illustrating a computer system for implementing an embodiment of the method for automatically inspecting through holes and connector pins of a printed circuit board of the present invention; FIG. 2 is a flow chart illustrating the embodiment of the method for automatically inspecting through holes and connector pins of a printed circuit board of the present invention; FIG. 3 is a flow chart to assist in illustrating the sub-steps of step 25 of FIG. 2; and FIG. 4 is a flow chart to assist in illustrating the sub-steps of step 26 of FIG. 2.

21~26: Steps

Claims (9)

A method for automatically checking through-holes and connector pins of a printed circuit board is implemented by a computer device, which stores a plurality of circuit board design data corresponding to a plurality of through-hole groups and a plurality of connector pins, a check filter data, at least one through-hole group check rule, and a connector pin check rule. Each circuit board design data corresponds to a through-hole group or a connector pin electrically connected to a differential pair of lines. The check filter data includes a specified type, which is a through-hole group type or a connector pin type. The method comprises the following steps: (A) obtaining at least one target circuit board design data that meets the check filter data from the circuit board design data according to the check filter data; (B) determining that the at least one target circuit board design data corresponds to the through hole group type or the connector pin type; (C) when it is determined that the at least one target circuit board design data corresponds to the through hole group type, for each target circuit board design data, generating at least one through hole group inspection result information corresponding to the target circuit board design data according to the target circuit board design data and the at least one through hole group inspection rule, and the at least one through hole group inspection result information respectively corresponds to the at least one through hole group inspection rule; and (D) When it is determined that the at least one target circuit board design data corresponds to the connector pin type, for each target circuit board design data, a connector pin check result information corresponding to the target circuit board design data is generated according to the target circuit board design data and the connector pin check rule. As described in claim 1, the method for automatically inspecting through holes and connector pins of a printed circuit board, each circuit board design data also includes an impedance value, and the inspection screening data also includes a specified circuit name and a specified impedance value, wherein, in step (A), the circuit name of the at least one target circuit board design data includes the specified circuit name, and the impedance value of the at least one target circuit board design data is the same as the specified impedance value. The method for automatically inspecting through holes and connector pins of a printed circuit board as described in claim 1, wherein the computer device further stores a plurality of through hole group inspection preset data corresponding to the through hole groups, and the computer device stores a through hole group inspection rule, wherein the through hole group inspection rule is whether at least one avoidance area size parameter and at least one through hole center distance of a circuit board design data meet a target through hole group inspection preset data, each corresponding to the through hole groups The circuit board design data includes at least one passing layer code related to the number of layers passed by the differential pair line, at least one avoidance area size parameter corresponding to the at least one passing layer code, and at least one through-hole center distance corresponding to the at least one passing layer code, and each through-hole group inspection preset data includes an ideal avoidance area size parameter and an ideal through-hole center distance, wherein step (C) includes the following sub-steps: (C-1) obtaining at least one target through-hole group inspection preset data corresponding to the at least one target circuit board design data from the through-hole group inspection preset data; and (C-2) for each target circuit board design data, comparing whether at least one avoidance area size parameter of the target circuit board design data is consistent with an ideal avoidance area size parameter of the target through-hole inspection preset data, and comparing whether at least one through-hole center distance of the target circuit board design data is consistent with an ideal through-hole center distance of the target through-hole inspection preset data, so as to generate a through-hole group inspection result information. A method for automatically inspecting through holes and connector pins of a printed circuit board as described in claim 3, wherein, in sub-step (C-2), if the at least one avoidance area size parameter is consistent with the ideal avoidance area size parameter, and the at least one through-hole center distance is consistent with the ideal through-hole center distance, then the through-hole group inspection result information indicates a pass; if one of the at least one avoidance area size parameter is inconsistent with the ideal avoidance area size parameter, or one of the at least one through-hole center distances is inconsistent with the ideal through-hole center distance, then the through-hole group inspection result information indicates an error. The method for automatically checking through holes and connector pins of a printed circuit board as described in claim 1, wherein the computer device stores a through hole group checking rule, and each circuit board design data includes at least one through layer code related to the layer through which the differential pair line passes, a plurality of all layer codes related to all layers of the printed circuit board, and a plurality of layer codes where the clear area is located, and each all layer code The through hole group inspection rule is that among all the multiple layer codes of a circuit board design data, except for at least one through layer code of the circuit board design data, the layer codes corresponding to the multiple through hole groups are checked to see whether they are included in the layer codes of the multiple clear areas of the circuit board design data, wherein step (C) includes the following sub-steps: (C-1) For each target circuit board design data, deduct the at least one pass layer code from the layer codes of the target circuit board design data to obtain multiple candidate inspection layer codes, and then screen multiple inspection layer codes corresponding to the through hole group inspection layer types from the candidate inspection layers; and (C-2) For each target circuit board design data, determine whether the inspection layer codes are included in the layer codes of the multiple clear areas of the target circuit board design data to generate a through hole group inspection result information. A method for automatically inspecting through holes and connector pins of a printed circuit board as described in claim 5, wherein, in sub-step (C-2), if the inspection layer number codes are included in the layer number codes where the clear space areas are located, then the through hole group inspection result information indicates a pass; if the inspection layer number codes are not included in the layer number codes where the clear space areas are located, then the through hole group inspection result information indicates an error. The method for automatically inspecting through holes and connector pins of a printed circuit board as described in claim 1, the computer device also stores a plurality of through hole group inspection preset data corresponding to the through hole groups, the computer device stores a first through hole group inspection rule, and a second through hole group inspection rule, each circuit board design data includes at least one through layer code related to the layer through which the differential pair line passes, a plurality of all layer codes related to all layers of the printed circuit board, and a plurality of layer codes where the clear area is located, each all layer code corresponds to a board layer type, the first through hole group inspection rule is whether at least one avoidance area size parameter and at least one through hole center distance of a circuit board design data meet a target through hole group inspection preset data, each corresponding to the The circuit board design data of the through hole group includes at least one passing layer code related to the layer passed by the differential pair line, at least one avoidance area size parameter corresponding to the at least one passing layer code, and at least one through hole center distance corresponding to the at least one passing layer code. Each through hole group inspection preset data includes an ideal avoidance area size parameter and an ideal through hole center distance. The second through hole group inspection rule is that among all the multiple layer codes of a circuit board design data, except for at least one passing layer code of the circuit board design data, the layer codes corresponding to the multiple through hole group inspection board layer types are included in the layer codes of the multiple clear areas of the circuit board design data. Step (C) includes the following sub-steps: (C-1) obtaining at least one target through-hole group inspection preset data respectively corresponding to the at least one target circuit board design data from the through-hole group inspection preset data; (C-2) for each target circuit board design data, generating a first through-hole group inspection result information corresponding to the target circuit board design data according to the target circuit board design data, a target through-hole inspection preset data corresponding to the target circuit board design data, and the first through-hole group inspection rule; and (C-3) for each target through-hole inspection preset data, generating a second through-hole group inspection result information corresponding to the target circuit board design data according to the target circuit board design data and the second through-hole group inspection rule. As described in claim 1, the through-hole and connector pin automatic inspection method of the printed circuit board, each circuit board design data includes at least one through-layer code related to the layer through which the differential pair line passes, a plurality of all-layer codes related to all layers of the printed circuit board, and a plurality of layer codes where the clear area is located, each all-layer code corresponds to a board layer type, and the at least one through-layer code has a layer code related to the differential pair line. The connector pin check rule is to check whether all target layer codes adjacent to a starting point layer code of the circuit board design data and conforming to a connector pin check board layer type are included in the layer codes of multiple clear areas of the circuit board design data, wherein step (D) includes the following sub-steps: (D-1) For each target circuit board design data, according to the starting point layer code of the target circuit board design data, obtain a check layer code adjacent to the starting point layer code and corresponding to the connector pin check layer type; and (D-2) For each target circuit board design data, determine whether the check layer code is included in the layer codes of multiple clear areas of the target circuit board design data to generate the connector pin check result information. A method for automatically inspecting through holes and connector pins of a printed circuit board as described in claim 8, wherein, in sub-step (D-2), if the inspection layer code is included in the layer code where the clear space areas are located, then the connector pin inspection result information indicates a pass; if the inspection layer code is not included in the layer code where the clear space areas are located, then the connector pin inspection result information indicates an error.

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